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| REJ09B0269-0100 32 SuperH TM SH7712 Hardware Manual Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7700 Series SH7712 HD6417712 Rev.1.00 Revision Date: Dec. 27, 2005 Rev. 1.00 Dec. 27, 2005 Page ii of xlii Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 1.00 Dec. 27, 2005 Page iii of xlii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 1.00 Dec. 27, 2005 Page iv of xlii Rev. 1.00 Dec. 27, 2005 Page v of xlii Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 1.00 Dec. 27, 2005 Page vi of xlii Rev. 1.00 Dec. 27, 2005 Page vii of xlii Preface The SH7712 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-3/SH-3E/SH3-DSP Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7712 Product Code HD6417712 * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-3/SH-3E/SH3-DSP Programming Manual. Rev. 1.00 Dec. 27, 2005 Page viii of xlii Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Bit order: Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Related Manuals: An overbar is added to a low-active signal: xxxx The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7712 manuals: Document Title SH7712 Hardware Manual SH-3/SH-3E/SH3-DSP Programming Manual Document No. This manual ADE-602-096B User's manuals for development tools: Document Title SuperH RISC engine C/C++ Compiler,Assembler,Optimizing Linkage Editor Compiler Package V.9.00 User's Manual SuperHTM RISC engine High-performance Embedded Workshop 3 Users Manual SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial TM Document No. REJ10B0152-0101 REJ10B0025-0200 REJ10B0023-0200 Application note: Document Title SuperH RISC engine C/C++ Compiler Package Application Note Document No. REJ05B0463-0100 Rev. 1.00 Dec. 27, 2005 Page ix of xlii Abbreviations ACIA AUD BSC CPG DMA DMAC etu FIFO H-UDI INTC JTAG LSB MMU MSB PFC RISC RTC SCIF SIOF TLB TMU UART UBC WDT Asynchronous communication interface adapter Advanced user debugger Bus state controller Clock pulse generator Direct memory access Direct memory access controller Elementary time unit First-in first-out User debugging interface Interrupt controller Joint test action group Least significant bit Memory management unit Most significant bit Pin function controller Reduced instruction set computer Realtime clock Serial communication interface with FIFO Serial I/O with FIFO Translation lookaside buffer Timer unit Universal asynchronous receiver/transmitter User break controller Watchdog timer Rev. 1.00 Dec. 27, 2005 Page x of xlii Rev. 1.00 Dec. 27, 2005 Page xi of xlii Contents Section 1 Overview and Pin Function ................................................................... 1 1.1 1.2 1.3 Features.................................................................................................................................. 1 Block Diagram....................................................................................................................... 7 Pin Description ...................................................................................................................... 8 1.3.1 Pin Assignment......................................................................................................... 8 1.3.2 Pin Functions .......................................................................................................... 19 Section 2 CPU ..................................................................................................... 27 2.1 Processing States and Processing Modes............................................................................. 27 2.1.1 Processing States .................................................................................................... 27 2.1.2 Processing Modes ................................................................................................... 28 Memory Map ....................................................................................................................... 29 2.2.1 Logical Address Space............................................................................................ 29 2.2.2 External Memory Space.......................................................................................... 30 Register Descriptions........................................................................................................... 32 2.3.1 General Registers.................................................................................................... 35 2.3.2 System Registers..................................................................................................... 36 2.3.3 Program Counter..................................................................................................... 37 2.3.4 Control Registers .................................................................................................... 38 Data Formats........................................................................................................................ 42 2.4.1 Register Data Format .............................................................................................. 42 2.4.2 Memory Data Formats ............................................................................................ 42 Features of CPU Core Instructions ...................................................................................... 44 2.5.1 Instruction Execution Method ................................................................................ 44 2.5.2 CPU Instruction Addressing Modes ....................................................................... 45 2.5.3 CPU Instruction Formats ........................................................................................ 48 Instruction Set ...................................................................................................................... 52 2.6.1 CPU Instruction Set Based on Functions................................................................ 52 2.6.2 Operation Code Map............................................................................................... 66 2.2 2.3 2.4 2.5 2.6 Section 3 DSP Operating Unit............................................................................. 71 3.1 3.2 DSP Extended Functions ..................................................................................................... 71 DSP Mode Resources .......................................................................................................... 73 3.2.1 Processing Modes ................................................................................................... 73 3.2.2 DSP Mode Memory Map........................................................................................ 73 3.2.3 CPU Register Sets................................................................................................... 74 Rev. 1.00 Dec. 27, 2005 Page xii of xlii 3.3 3.4 3.5 3.6 3.2.4 DSP Registers ......................................................................................................... 77 CPU Extended Instructions.................................................................................................. 78 3.3.1 Repeat Control Instructions .................................................................................... 78 3.3.2 Extended Repeat Control Instructions .................................................................... 88 DSP Data Transfer Instructions ........................................................................................... 93 3.4.1 General Registers.................................................................................................... 97 3.4.2 DSP Data Addressing ............................................................................................. 99 3.4.3 Modulo Addressing............................................................................................... 100 3.4.4 Memory Data Formats .......................................................................................... 103 3.4.5 Instruction Formats of Double and Single Transfer Instructions .......................... 103 DSP Data Operation Instructions ....................................................................................... 106 3.5.1 DSP Registers ....................................................................................................... 106 3.5.2 DSP Operation Instruction Set.............................................................................. 111 3.5.3 DSP-Type Data Formats ....................................................................................... 116 3.5.4 ALU Fixed-Point Operations................................................................................ 118 3.5.5 ALU Integer Operations ....................................................................................... 123 3.5.6 ALU Logical Operations....................................................................................... 125 3.5.7 Fixed-Point Multiply Operation............................................................................ 126 3.5.8 Shift Operations .................................................................................................... 128 3.5.9 Most Significant Bit Detection Operation............................................................. 132 3.5.10 Rounding Operation.............................................................................................. 135 3.5.11 Overflow Protection.............................................................................................. 137 3.5.12 Local Data Move Instruction ................................................................................ 138 3.5.13 Operand Conflict................................................................................................... 139 DSP Extended Function Instruction Set............................................................................. 140 3.6.1 CPU Extended Instructions................................................................................... 140 3.6.2 Double-Data Transfer Instructions........................................................................ 142 3.6.3 Single-Data Transfer Instructions ......................................................................... 143 3.6.4 DSP Operation Instructions .................................................................................. 145 3.6.5 Operation Code Map in DSP Mode ...................................................................... 151 Section 4 Exception Handling ...........................................................................155 4.1 Register Descriptions ......................................................................................................... 155 4.1.1 TRAPA Exception Register (TRA) ...................................................................... 156 4.1.2 Exception Event Register (EXPEVT)................................................................... 157 4.1.3 Interrupt Event Register (INTEVT)...................................................................... 157 4.1.4 Interrupt Event Register 2 (INTEVT2)................................................................. 158 4.1.5 Exception Address Register (TEA)....................................................................... 158 Exception Handling Function ............................................................................................ 159 4.2.1 Exception Handling Flow ..................................................................................... 159 Rev. 1.00 Dec. 27, 2005 Page xiii of xlii 4.2 4.3 4.4 4.5 4.2.2 Exception Vector Addresses................................................................................. 160 4.2.3 Exception Codes ................................................................................................... 160 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ......................... 160 4.2.5 Exception Source Acceptance Timing and Priority .............................................. 161 Individual Exception Operations ....................................................................................... 165 4.3.1 Resets.................................................................................................................... 165 4.3.2 General Exceptions............................................................................................... 166 4.3.3 General Exceptions (MMU Exceptions)............................................................... 169 Exception Processing while DSP Extension Function is Valid ......................................... 172 4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception .................... 172 4.4.2 CPU Address Error ............................................................................................... 172 4.4.3 Exception in Repeat Control Period ..................................................................... 172 Usage Notes ....................................................................................................................... 179 Section 5 Memory Management Unit (MMU).................................................. 181 5.1 5.2 Role of MMU .................................................................................................................... 181 5.1.1 MMU of This LSI................................................................................................. 183 Register Descriptions......................................................................................................... 189 5.2.1 Page Table Entry Register High (PTEH).............................................................. 190 5.2.2 Page Table Entry Register Low (PTEL) ............................................................... 191 5.2.3 Translation Table Base Register (TTB) ................................................................ 191 5.2.4 MMU Control Register (MMUCR) ...................................................................... 191 TLB Functions ................................................................................................................... 193 5.3.1 Configuration of the TLB ..................................................................................... 193 5.3.2 TLB Indexing........................................................................................................ 195 5.3.3 TLB Address Comparison .................................................................................... 196 5.3.4 Page Management Information............................................................................. 198 MMU Functions................................................................................................................. 200 5.4.1 MMU Hardware Management.............................................................................. 200 5.4.2 MMU Software Management ............................................................................... 200 5.4.3 MMU Instruction (LDTLB).................................................................................. 201 5.4.4 Avoiding Synonym Problems............................................................................... 202 MMU Exceptions............................................................................................................... 205 5.5.1 TLB Miss Exception............................................................................................. 205 5.5.2 TLB Protection Violation Exception .................................................................... 206 5.5.3 TLB Invalid Exception ......................................................................................... 207 5.5.4 Initial Page Write Exception................................................................................. 208 5.5.5 MMU Exception in Repeat Loop.......................................................................... 209 Memory-Mapped TLB....................................................................................................... 211 5.6.1 Address Array....................................................................................................... 211 5.3 5.4 5.5 5.6 Rev. 1.00 Dec. 27, 2005 Page xiv of xlii 5.7 5.6.2 Data Array ............................................................................................................ 211 5.6.3 Usage Examples.................................................................................................... 213 Usage Note......................................................................................................................... 213 Section 6 Cache .................................................................................................215 6.1 6.2 Features.............................................................................................................................. 215 6.1.1 Cache Structure..................................................................................................... 215 Register Descriptions ......................................................................................................... 217 6.2.1 Cache Control Register 1 (CCR1) ........................................................................ 217 6.2.2 Cache Control Register 2 (CCR2) ........................................................................ 218 6.2.3 Cache Control Register 3 (CCR3) ........................................................................ 221 Operation ........................................................................................................................... 222 6.3.1 Searching the Cache.............................................................................................. 222 6.3.2 Read Access.......................................................................................................... 223 6.3.3 Prefetch Operation ................................................................................................ 224 6.3.4 Write Access ......................................................................................................... 224 6.3.5 Write-Back Buffer ................................................................................................ 224 6.3.6 Coherency of Cache and External Memory .......................................................... 225 Memory-Mapped Cache .................................................................................................... 226 6.4.1 Address Array ....................................................................................................... 226 6.4.2 Data Array ............................................................................................................ 227 6.4.3 Usage Examples.................................................................................................... 230 6.3 6.4 Section 7 X/Y Memory......................................................................................231 7.1 7.2 Features.............................................................................................................................. 231 Operation ........................................................................................................................... 232 7.2.1 Access from CPU.................................................................................................. 232 7.2.2 Access from DSP .................................................................................................. 232 7.2.3 Access from DMAC and E-DMAC ...................................................................... 233 Usage Notes ....................................................................................................................... 233 7.3.1 Page Conflict ........................................................................................................ 233 7.3.2 Bus Conflict .......................................................................................................... 233 7.3.3 MMU and Cache Settings..................................................................................... 233 7.3.4 Sleep Mode ........................................................................................................... 234 7.3.5 Address Error........................................................................................................ 234 7.3 Section 8 Interrupt Controller (INTC) ...............................................................235 8.1 8.2 Features.............................................................................................................................. 235 8.1.1 Block Diagram...................................................................................................... 235 Input/Output Pins ............................................................................................................... 237 Rev. 1.00 Dec. 27, 2005 Page xv of xlii 8.3 8.4 8.5 Interrupt Sources................................................................................................................ 237 8.3.1 NMI Interrupt........................................................................................................ 237 8.3.2 IRQ Interrupts....................................................................................................... 238 8.3.3 IRL Interrupts ....................................................................................................... 238 8.3.4 On-Chip Peripheral Module Interrupts ................................................................. 239 8.3.5 Interrupt Exception Handling and Priority............................................................ 240 Register Descriptions......................................................................................................... 246 8.4.1 Interrupt Priority Registers A to I (IPRA to IPRI)................................................ 246 8.4.2 Interrupt Control Register 0 (ICR0)...................................................................... 248 8.4.3 Interrupt Control Register 1 (ICR1)...................................................................... 249 8.4.4 Interrupt Request Register 0 (IRR0) ..................................................................... 251 8.4.5 Interrupt Request Register 1 (IRR1) ..................................................................... 251 8.4.6 Interrupt Request Register 2 (IRR2) ..................................................................... 253 8.4.7 Interrupt Request Register 3 (IRR3) ..................................................................... 254 8.4.8 Interrupt Request Register 4 (IRR4) ..................................................................... 255 8.4.9 Interrupt Request Register 5 (IRR5) ..................................................................... 256 8.4.10 Interrupt Request Register 7 (IRR7) ..................................................................... 257 8.4.11 Interrupt Request Register 8 (IRR8) ..................................................................... 258 Operation ........................................................................................................................... 260 8.5.1 Interrupt Sequence ................................................................................................ 260 8.5.2 Multiple Interrupts ................................................................................................ 262 Section 9 User Break Controller........................................................................ 263 9.1 9.2 Features.............................................................................................................................. 263 Register Descriptions......................................................................................................... 266 9.2.1 Break Address Register A (BARA)...................................................................... 266 9.2.2 Break Address Mask Register A (BAMRA)......................................................... 267 9.2.3 Break Bus Cycle Register A (BBRA)................................................................... 267 9.2.4 Break Address Register B (BARB) ...................................................................... 269 9.2.5 Break Address Mask Register B (BAMRB) ......................................................... 270 9.2.6 Break Data Register B (BDRB)............................................................................ 270 9.2.7 Break Data Mask Register B (BDMRB)............................................................... 271 9.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 272 9.2.9 Break Control Register (BRCR) ........................................................................... 274 9.2.10 Execution Times Break Register (BETR)............................................................. 278 9.2.11 Branch Source Register (BRSR)........................................................................... 279 9.2.12 Branch Destination Register (BRDR)................................................................... 280 9.2.13 Break ASID Register A (BASRA) ....................................................................... 280 9.2.14 Break ASID Register B (BASRB)........................................................................ 281 Operation ........................................................................................................................... 281 9.3 Rev. 1.00 Dec. 27, 2005 Page xvi of xlii 9.4 9.3.1 Flow of the User Break Operation ........................................................................ 281 9.3.2 Break on Instruction Fetch Cycle.......................................................................... 283 9.3.3 Break on Data Access Cycle................................................................................. 283 9.3.4 Break on X/Y-Memory Bus Cycle........................................................................ 285 9.3.5 Sequential Break ................................................................................................... 285 9.3.6 Value of Saved Program Counter ......................................................................... 286 9.3.7 PC Trace ............................................................................................................... 287 9.3.8 Usage Examples.................................................................................................... 287 Usage Notes ....................................................................................................................... 292 Section 10 Power-Down Modes ........................................................................295 10.1 Overview............................................................................................................................ 295 10.1.1 Power-Down Modes ............................................................................................. 295 10.1.2 Reset ..................................................................................................................... 296 10.1.3 Input/Output Pins.................................................................................................. 298 10.2 Register Descriptions ......................................................................................................... 298 10.2.1 Standby Control Register (STBCR)...................................................................... 298 10.2.2 Standby Control Register 2 (STBCR2)................................................................. 300 10.2.3 Standby Control Register 3 (STBCR3)................................................................. 301 10.3 Operation ........................................................................................................................... 302 10.3.1 Sleep Mode ........................................................................................................... 302 10.3.2 Software Standby Mode........................................................................................ 303 10.3.3 Module Standby Function..................................................................................... 305 10.3.4 STATUS Pin Change Timings.............................................................................. 306 Section 11 On-Chip Oscillation Circuits ...........................................................311 11.1 Overview............................................................................................................................ 311 11.1.1 Features................................................................................................................. 311 11.2 Overview of CPG............................................................................................................... 313 11.2.1 CPG Block Diagram ............................................................................................. 313 11.2.2 Input/Output Pins.................................................................................................. 315 11.3 Clock Operating Modes ..................................................................................................... 315 11.4 Register Description........................................................................................................... 320 11.4.1 Frequency Control Register (FRQCR) ................................................................. 320 11.5 Changing Frequency .......................................................................................................... 322 11.5.1 Changing Multiplication Rate............................................................................... 322 11.5.2 Changing Division Ratio....................................................................................... 322 11.6 Overview of WDT ............................................................................................................. 323 11.6.1 Block Diagram of WDT........................................................................................ 323 11.7 Register Descriptions of WDT........................................................................................... 324 Rev. 1.00 Dec. 27, 2005 Page xvii of xlii 11.7.1 Watchdog Timer Counter (WTCNT).................................................................... 324 11.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 324 11.7.3 Notes on Register Access ..................................................................................... 326 11.8 Using WDT........................................................................................................................ 327 11.8.1 Canceling Standbys .............................................................................................. 327 11.8.2 Changing Frequency ............................................................................................. 328 11.8.3 Using Watchdog Timer Mode .............................................................................. 328 11.8.4 Using Interval Timer Mode .................................................................................. 328 11.9 Notes on Board Design ...................................................................................................... 329 Section 12 Bus State Controller (BSC) ............................................................. 331 12.1 Features.............................................................................................................................. 331 12.2 Input/Output Pins............................................................................................................... 334 12.3 Area Overview................................................................................................................... 336 12.3.1 Area Division........................................................................................................ 336 12.3.2 Shadow Area......................................................................................................... 336 12.3.3 Address Map......................................................................................................... 338 12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 340 12.3.5 Data Alignment..................................................................................................... 340 12.4 Register Descriptions......................................................................................................... 341 12.4.1 Common Control Register (CMNCR) .................................................................. 342 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) ..... 345 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)... 351 12.4.4 SDRAM Control Register (SDCR)....................................................................... 378 12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 381 12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 382 12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 383 12.5 Operation ........................................................................................................................... 384 12.5.1 Endian/Access Size and Data Alignment.............................................................. 384 12.5.2 Normal Space Interface ........................................................................................ 390 12.5.3 Access Wait Control ............................................................................................. 396 12.5.4 CSn Assert Period Expansion ............................................................................... 398 12.5.5 SDRAM Interface ................................................................................................. 399 12.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 440 12.5.7 Byte-Selection SRAM Interface ........................................................................... 442 12.5.8 PCMCIA Interface................................................................................................ 447 12.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 453 12.5.10 Wait between Access Cycles ................................................................................ 454 12.5.11 Bus Arbitration ..................................................................................................... 454 12.5.12 Others.................................................................................................................... 456 Rev. 1.00 Dec. 27, 2005 Page xviii of xlii Section 13 Direct Memory Access Controller (DMAC) ...................................459 13.1 Features.............................................................................................................................. 459 13.2 Input/Output Pins ............................................................................................................... 461 13.3 Register Descriptions ......................................................................................................... 462 13.3.1 DMA Source Address Register (SAR) ................................................................. 463 13.3.2 DMA Destination Address Register (DAR) ......................................................... 463 13.3.3 DMA Transfer Count Register (DMATCR) ......................................................... 464 13.3.4 DMA Channel Control Register (CHCR) ............................................................. 464 13.3.5 DMA Operation Register (DMAOR) ................................................................... 469 13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2) ................... 471 13.4 Operation ........................................................................................................................... 474 13.4.1 DMA Transfer Flow ............................................................................................. 474 13.4.2 DMA Transfer Requests ....................................................................................... 477 13.4.3 Channel Priority.................................................................................................... 479 13.4.4 DMA Transfer Types............................................................................................ 482 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 489 13.5 Usage Note......................................................................................................................... 493 Section 14 Timer Unit (TMU) ...........................................................................495 14.1 Features.............................................................................................................................. 495 14.1.1 Block Diagram...................................................................................................... 495 14.2 Register Descriptions ......................................................................................................... 497 14.2.1 Timer Start Register (TSTR) ................................................................................ 497 14.2.2 Timer Control Registers (TCR) ............................................................................ 498 14.2.3 Timer Constant Registers (TCOR) ....................................................................... 499 14.2.4 Timer Counters (TCNT) ....................................................................................... 499 14.3 TMU Operation.................................................................................................................. 500 14.3.1 Counter Operation................................................................................................. 500 14.4 Interrupts............................................................................................................................ 503 14.4.1 Status Flag Set Timing.......................................................................................... 503 14.4.2 Status Flag Clear Timing ...................................................................................... 503 14.4.3 Interrupt Sources and Priorities ............................................................................ 504 14.5 Usage Notes ....................................................................................................................... 504 14.5.1 Writing to Registers .............................................................................................. 504 14.5.2 Reading Registers ................................................................................................. 504 Section 15 Realtime Clock (RTC) .....................................................................505 15.1 Feature ............................................................................................................................... 505 15.2 Input/Output Pins ............................................................................................................... 507 15.3 Register Descriptions ......................................................................................................... 507 Rev. 1.00 Dec. 27, 2005 Page xix of xlii 15.3.1 64-Hz Counter (R64CNT) .................................................................................... 508 15.3.2 Second Counter (RSECCNT) ............................................................................... 508 15.3.3 Minute Counter (RMINCNT)............................................................................... 509 15.3.4 Hour Counter (RHRCNT) .................................................................................... 509 15.3.5 Day of Week Counter (RWKCNT) ...................................................................... 510 15.3.6 Date Counter (RDAYCNT) .................................................................................. 512 15.3.7 Month Counter (RMONCNT) .............................................................................. 512 15.3.8 Year Counter (RYRCNT)..................................................................................... 513 15.3.9 Second Alarm Register (RSECAR) ...................................................................... 514 15.3.10 Minute Alarm Register (RMINAR)...................................................................... 514 15.3.11 Hour Alarm Register (RHRAR) ........................................................................... 515 15.3.12 Day of Week Alarm Register (RWKAR) ............................................................. 516 15.3.13 Date Alarm Register (RDAYAR)......................................................................... 517 15.3.14 Month Alarm Register (RMONAR) ..................................................................... 518 15.3.15 Year Alarm Register (RYRAR)............................................................................ 519 15.3.16 RTC Control Register 1 (RCR1)........................................................................... 520 15.3.17 RTC Control Register 2 (RCR2)........................................................................... 522 15.3.18 RTC Control Register 3 (RCR3)........................................................................... 524 15.4 Operation ........................................................................................................................... 525 15.4.1 Initial Settings of Registers after Power-On ......................................................... 525 15.4.2 Setting Time ......................................................................................................... 525 15.4.3 Reading Time........................................................................................................ 525 15.4.4 Alarm Function..................................................................................................... 527 15.4.5 Crystal Oscillator Circuit ...................................................................................... 528 15.5 Usage Notes ....................................................................................................................... 529 15.5.1 Register Writing during RTC Count..................................................................... 529 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts................................................ 529 15.5.3 Transition to Standby Mode after Setting Register............................................... 529 15.5.4 Usage Note about RTC Power Supply.................................................................. 530 Section 16 Serial Communication Interface with FIFO (SCIF)........................ 531 16.1 Features.............................................................................................................................. 531 16.2 Input/Output Pins............................................................................................................... 534 16.3 Register Descriptions......................................................................................................... 535 16.3.1 Receive Shift Register (SCRSR) .......................................................................... 536 16.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 536 16.3.3 Transmit Shift Register (SCTSR) ......................................................................... 537 16.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 537 16.3.5 Serial Mode Register (SCSMR)............................................................................ 537 16.3.6 Serial Control Register (SCSCR).......................................................................... 541 Rev. 1.00 Dec. 27, 2005 Page xx of xlii 16.3.7 Serial Status Register (SCFSR) ............................................................................ 545 16.3.8 Bit Rate Register (SCBRR) .................................................................................. 553 16.3.9 FIFO Control Register (SCFCR) .......................................................................... 554 16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 556 16.3.11 Line Status Register (SCLSR) .............................................................................. 558 16.4 Operation ........................................................................................................................... 559 16.4.1 Overview............................................................................................................... 559 16.4.2 Serial Operation in Asynchronous Mode.............................................................. 561 16.4.3 Serial Operation in Clock Synchronous Mode...................................................... 572 16.5 SCIF Interrupt Sources and DMAC................................................................................... 582 16.6 Usage Notes ....................................................................................................................... 583 Section 17 Serial I/O with FIFO (SIOF)............................................................587 17.1 Features.............................................................................................................................. 587 17.1.1 Block Diagram...................................................................................................... 588 17.2 Input/Output Pins ............................................................................................................... 589 17.3 Register Descriptions ......................................................................................................... 590 17.3.1 SIOF Mode Register (SIMDR) ............................................................................. 591 17.3.2 Serial Clock Select Register (SISCR)................................................................... 593 17.3.3 Serial Transmit Data Assign Register (SITDAR) ................................................. 594 17.3.4 Serial Receive Data Assign Register (SIRDAR) .................................................. 595 17.3.5 Serial Control Data Assign Register (SICDAR) ................................................... 596 17.3.6 SIOF Control Register (SICTR) ........................................................................... 598 17.3.7 SIOF FIFO Control Register (SIFCTR)................................................................ 601 17.3.8 SIOF Status Register (SISTR) .............................................................................. 603 17.3.9 SIOF Interrupt Enable Register (SIIER) ............................................................... 607 17.3.10 Serial Transmit Data Register (SITDR)................................................................ 609 17.3.11 Serial Receive Data Register (SIRDR) ................................................................. 610 17.3.12 Serial Transmit Control Data Register (SITCR) ................................................... 611 17.3.13 Serial Receive Control Data Register (SIRCR) .................................................... 612 17.4 Operation ........................................................................................................................... 613 17.4.1 Serial Clocks ......................................................................................................... 613 17.4.2 Serial Timing ........................................................................................................ 614 17.4.3 Transfer Data Format............................................................................................ 616 17.4.4 Register Allocation of Transfer Data .................................................................... 617 17.4.5 Control Data Interface .......................................................................................... 620 17.4.6 FIFO...................................................................................................................... 621 17.4.7 Transmission and Reception Procedures .............................................................. 623 17.4.8 Interrupts............................................................................................................... 628 17.4.9 Transmission and Reception Timing .................................................................... 630 Rev. 1.00 Dec. 27, 2005 Page xxi of xlii 17.5 Usage Notes ....................................................................................................................... 635 Section 18 Ethernet Controller (EtherC) ........................................................... 637 18.1 Features.............................................................................................................................. 637 18.2 Input/Output Pins............................................................................................................... 639 18.3 Register Descriptions......................................................................................................... 641 18.3.1 Software Reset Register (ARSTR) ....................................................................... 644 18.3.2 EtherC Mode Register (ECMR)............................................................................ 645 18.3.3 EtherC Status Register (ECSR) ............................................................................ 648 18.3.4 EtherC Interrupt Permission Register (ECSIPR) .................................................. 649 18.3.5 PHY Interface Register (PIR) ............................................................................... 650 18.3.6 MAC Address High Register (MAHR) ................................................................ 651 18.3.7 MAC Address Low Register (MALR) ................................................................. 651 18.3.8 Receive Frame Length Register (RFLR) .............................................................. 652 18.3.9 PHY Status Register (PSR)................................................................................... 653 18.3.10 Transmit Retry Over Counter Register (TROCR) ................................................ 653 18.3.11 Delayed Collision Detect Counter Register (CDCR)............................................ 654 18.3.12 Lost Carrier Counter Register (LCCR)................................................................. 654 18.3.13 Carrier Not Detect Counter Register (CNDCR) ................................................... 654 18.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 655 18.3.15 Frame Receive Error Counter Register (FRECR)................................................. 655 18.3.16 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 655 18.3.17 Too-Long Frame Receive Counter Register (TLFRCR) ...................................... 656 18.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 656 18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)........................... 657 18.3.20 IPG Register (IPGR)............................................................................................. 657 18.3.21 TSU Counter Reset Register (TSU_CTRST) ....................................................... 658 18.3.22 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) ............................................ 658 18.3.23 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) ............................................ 659 18.3.24 Relay FIFO Size Select Register (TSU_FCM) ..................................................... 660 18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) ..................... 661 18.3.26 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) ..................... 662 18.3.27 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)............ 663 18.3.28 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1)............ 664 18.3.29 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)...................... 666 18.3.30 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)...................... 667 18.3.31 Relay Function Set Register (Common) (TSU_FWSLC)..................................... 669 18.3.32 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAGM0) .................. 671 18.3.33 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAGM1) .................. 672 18.3.34 Relay Status Register (TSU_FWSR) .................................................................... 673 Rev. 1.00 Dec. 27, 2005 Page xxii of xlii 18.3.35 Relay Status Interrupt Mask Register (TSU_FWINMK)...................................... 675 18.3.36 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0).............................. 679 18.3.37 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1).............................. 680 18.3.38 CAM Entry Table Busy Register (TSU_ADSBSY) ............................................. 681 18.3.39 CAM Entry Table Enable Register (TSU_TEN) .................................................. 682 18.3.40 CAM Entry Table POST1 Register (TSU_POST1).............................................. 686 18.3.41 CAM Entry Table POST2 Register (TSU_POST2).............................................. 689 18.3.42 CAM Entry Table POST3 Register (TSU_POST3).............................................. 692 18.3.43 CAM Entry Table POST4 Register (TSU_POST4).............................................. 695 18.3.44 CAM Entry Table 0 to 31 H Registers (TSU_ADRH0 to TSU_ADRH31).......... 698 18.3.45 CAM Entry Table 0 to 31 L Registers (TSU_ADRL0 to TSU_ADRL31) ........... 699 18.3.46 Transmit Frame Counter Register (Port 0) (Normal Transmission Only) (TXNLCR0) ......................................................................................................... 699 18.3.47 Transmit Frame Counter Register (Port 0) (Normal and Error Transmission) (TXALCR0) ......................................................................................................... 700 18.3.48 Receive Frame Counter Register (Port 0) (Normal Reception Only) (RXNLCR0) ......................................................................................................... 700 18.3.49 Receive Frame Counter Register (Port 0) (Normal and Error Reception) (RXALCR0) ......................................................................................................... 701 18.3.50 Relay Frame Counter Register (Port 1 to 0) (Normal Relay Only) (FWNLCR0)......................................................................................................... 701 18.3.51 Relay Frame Counter Register (Port 1 to 0) (Normal and Error Relay) (FWALCR0)......................................................................................................... 702 18.3.52 Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (TXNLCR1) ......................................................................................................... 702 18.3.53 Transmit Frame Counter Register (Port 1) (Normal and Error Transmission) (TXALCR1) ......................................................................................................... 703 18.3.54 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1) ......................................................................................................... 703 18.3.55 Receive Frame Counter Register (Port 1) (Normal and Error Reception) (RXALCR1) ......................................................................................................... 704 18.3.56 Relay Frame Counter Register (Port 0 to 1) (Normal Relay Only) (FWNLCR1)......................................................................................................... 704 18.3.57 Relay Frame Counter Register (Port 0 to 1) (Normal and Error Relay) (FWALCR1)......................................................................................................... 705 18.4 Operation ........................................................................................................................... 706 18.4.1 Transmission......................................................................................................... 707 18.4.2 Reception .............................................................................................................. 709 18.4.3 Relay ..................................................................................................................... 711 18.4.4 CAM Function ...................................................................................................... 711 Rev. 1.00 Dec. 27, 2005 Page xxiii of xlii 18.4.5 MII Frame Timing ................................................................................................ 717 18.4.6 Accessing MII Registers....................................................................................... 719 18.4.7 Magic Packet Detection ........................................................................................ 722 18.4.8 Operation by IPG Setting...................................................................................... 723 18.4.9 Direction for IEEE802.1Q Qtag ........................................................................... 723 18.5 Connection to LSI.............................................................................................................. 725 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)....................................................................................... 727 19.1 Features.............................................................................................................................. 727 19.2 Register Descriptions......................................................................................................... 728 19.2.1 E-DMAC Mode Register (EDMR)....................................................................... 730 19.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 731 19.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 732 19.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 733 19.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 734 19.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 734 19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 740 19.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 743 19.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 744 19.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 745 19.2.11 FIFO Depth Register (FDR) ................................................................................. 747 19.2.12 Receiving Method Control Register (RMCR) ...................................................... 748 19.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 749 19.2.14 Receive Buffer Write Address Register (RBWAR).............................................. 750 19.2.15 Receive Descriptor Fetch Address Register (RDFAR)......................................... 750 19.2.16 Transmit Buffer Read Address Register (TBRAR) .............................................. 750 19.2.17 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 751 19.2.18 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 751 19.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 753 19.3 Operation ........................................................................................................................... 753 19.3.1 Descriptors and Descriptor List ............................................................................ 754 19.3.2 Transmission......................................................................................................... 767 19.3.3 Reception .............................................................................................................. 769 19.3.4 Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/ Multi-Descriptor) ........................................................................ 771 19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY)................................................ 773 19.4 Usage Notes ....................................................................................................................... 776 19.4.1 Using of EDTRR and EDRRR ............................................................................. 776 19.4.2 Endian Support in E-DMAC................................................................................. 777 Rev. 1.00 Dec. 27, 2005 Page xxiv of xlii Section 20 Pin Function Controller (PFC).........................................................779 20.1 Overview............................................................................................................................ 779 20.2 Register Configuration....................................................................................................... 780 20.3 Register Descriptions ......................................................................................................... 781 20.3.1 Port A Control Register (PACR) .......................................................................... 781 20.3.2 Port B Control Register (PBCR)........................................................................... 782 20.3.3 Port C Control Register (PCCR)........................................................................... 783 20.3.4 Ethernet Controller Pin Control Register (PETCR).............................................. 784 Section 21 I/O Ports ...........................................................................................787 21.1 Overview............................................................................................................................ 787 21.2 Register Descriptions ......................................................................................................... 787 21.2.1 Port A Data Register (PADR)............................................................................... 787 21.2.2 Port B Data Register (PBDR) ............................................................................... 788 21.2.3 Port C Data Register (PCDR) ............................................................................... 790 Section 22 User Debugging Interface (H-UDI) .................................................791 22.1 Features.............................................................................................................................. 791 22.2 Input/Output Pins ............................................................................................................... 792 22.3 Register Descriptions ......................................................................................................... 793 22.3.1 Bypass Register (SDBPR) .................................................................................... 793 22.3.2 Instruction Register (SDIR) .................................................................................. 793 22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 794 22.3.4 ID Register (SDID)............................................................................................... 801 22.4 Operation ........................................................................................................................... 802 22.4.1 TAP Controller ..................................................................................................... 802 22.4.2 Reset Configuration .............................................................................................. 803 22.4.3 TDO Output Timing ............................................................................................. 803 22.4.4 H-UDI Reset ......................................................................................................... 804 22.4.5 H-UDI Interrupt .................................................................................................... 804 22.5 Boundary Scan ................................................................................................................... 805 22.5.1 Supported Instructions .......................................................................................... 805 22.5.2 Points for Attention............................................................................................... 806 22.6 Usage Notes ....................................................................................................................... 806 22.7 Advanced User Debugger (AUD)...................................................................................... 806 Section 23 List of Registers ...............................................................................807 23.1 Register Addresses (by functional module, in order of the corresponding section numbers) ................................................................................................................ 808 23.2 Register Bits....................................................................................................................... 821 Rev. 1.00 Dec. 27, 2005 Page xxv of xlii 23.3 Register States in Each Operating Mode ........................................................................... 845 Section 24 Electrical Characteristics ................................................................. 855 24.1 Absolute Maximum Ratings .............................................................................................. 855 24.2 DC Characteristics ............................................................................................................. 857 24.3 AC Characteristics ............................................................................................................. 859 24.3.1 Clock Timing ........................................................................................................ 860 24.3.2 Control Signal Timing .......................................................................................... 865 24.3.3 AC Bus Timing..................................................................................................... 868 24.3.4 Basic Timing......................................................................................................... 870 24.3.5 Burst ROM Timing............................................................................................... 874 24.3.6 Synchronous DRAM Timing................................................................................ 875 24.3.7 DMAC Signal Timing .......................................................................................... 901 24.3.8 RTC Signal Timing............................................................................................... 902 24.3.9 SCIF Module Signal Timing................................................................................. 903 24.3.10 SIOF Module Signal Timing ................................................................................ 904 24.3.11 Ethernet Controller Timing................................................................................... 908 24.3.12 Port Input/Output Timing ..................................................................................... 912 24.3.13 H-UDI Related Pin Timing................................................................................... 913 24.3.14 AC Characteristics Measurement Conditions ....................................................... 915 24.4 Delay Time Variation Due to Load Capacitance ............................................................... 916 Appendix A. B. ......................................................................................................... 917 Pin States and States of Unused Pins ................................................................................. 917 Package Dimensions .......................................................................................................... 925 Index ......................................................................................................... 929 Rev. 1.00 Dec. 27, 2005 Page xxvi of xlii Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Overview Block Diagram .............................................................................................................. 7 Pin Assignment (HQFP2828-256(FP-256G/GV)) ........................................................ 8 Pin Assignment (P-LFBGA1717-256(BP-256H/HV)).................................................. 9 CPU Processing State Transitions........................................................................................ 28 Logical Address to External Memory Space Mapping................................................ 31 Register Configuration in Each Processing Mode....................................................... 34 General Registers ........................................................................................................ 36 System Registers and Program Counter ...................................................................... 37 Control Register Configuration ................................................................................... 41 Data Format on Memory (Big Endian Mode) ............................................................. 43 Data Format on Memory (Little Endian Mode) .......................................................... 43 Section 3 DSP Operating Unit Figure 3.1 DSP Instruction Format............................................................................................... 72 Figure 3.2 CPU Registers in DSP Mode....................................................................................... 74 Figure 3.3 DSP Register Configuration ........................................................................................ 77 Figure 3.4 DSP Registers and Bus Connections ........................................................................... 94 Figure 3.5 General Registers (DSP Mode) ................................................................................... 97 Figure 3.6 Sample Parallel Instruction Program......................................................................... 113 Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 115 Figure 3.8 Data Formats ............................................................................................................. 117 Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 118 Figure 3.10 Operation Sequence Example.................................................................................. 120 Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 121 Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 121 Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 122 Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 123 Figure 3.15 ALU Logical Operation Flow ................................................................................. 125 Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 127 Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 129 Figure 3.18 Logical Shift Operation Flow.................................................................................. 131 Figure 3.19 PDMSB Operation Flow ......................................................................................... 133 Figure 3.20 Rounding Operation Flow ....................................................................................... 136 Figure 3.21 Definition of Rounding Operation........................................................................... 136 Figure 3.22 Local Data Move Instruction Flow.......................................................................... 138 Rev. 1.00 Dec. 27, 2005 Page xxvii of xlii Section 4 Exception Handling Figure 4.1 Register Bit Configuration ........................................................................................ 156 Section 5 Memory Management Unit (MMU) Figure 5.1 MMU Functions ........................................................................................................ 183 Figure 5.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 185 Figure 5.3 Virtual Address Space (MMUCR.AT = 0)................................................................ 186 Figure 5.4 P4 Area...................................................................................................................... 187 Figure 5.5 External Memory Space ............................................................................................ 188 Figure 5.6 Overall Configuration of the TLB............................................................................. 193 Figure 5.7 Virtual Address and TLB Structure........................................................................... 194 Figure 5.8 TLB Indexing (IX = 1) .............................................................................................. 195 Figure 5.9 TLB Indexing (IX = 0) .............................................................................................. 196 Figure 5.10 Objects of Address Comparison.............................................................................. 197 Figure 5.11 Operation of LDTLB Instruction............................................................................. 202 Figure 5.12 Synonym Problem (32-kbyte Cache) ...................................................................... 204 Figure 5.13 MMU Exception Generation Flowchart .................................................................. 210 Figure 5.14 Specifying Address and Data for Memory-Mapped TLB Access ........................... 212 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Cache Cache Structure ......................................................................................................... 215 Cache Search Scheme ............................................................................................... 223 Write-Back Buffer Configuration.............................................................................. 225 Specifying Address and Data for Memory-Mapped Cache Access (16 kbytes mode)...................................................................................................... 228 Figure 6.5 Specifying Address and Data for Memory-Mapped Cache Access (32 kbytes mode)...................................................................................................... 229 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Interrupt Controller (INTC) Block Diagram of INTC............................................................................................ 236 Example of IRL Interrupt Connection....................................................................... 239 Interrupt Operation Flowchart................................................................................... 261 Section 9 User Break Controller Figure 9.1 Block Diagram of User Break Controller.................................................................. 265 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Power-Down Modes Canceling Standby Mode with STBCR.STBY........................................................ 305 STATUS Output at Power-On Reset....................................................................... 306 STATUS Output at Manual Reset........................................................................... 307 STATUS Output when Software Standby Mode is Canceled by Interrupt ............. 307 STATUS Output when Software Standby Mode is Canceled by Power-on Reset ....................................................................................................... 308 Rev. 1.00 Dec. 27, 2005 Page xxviii of xlii Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 STATUS Output when Software Standby Mode is Canceled by Manual Reset ..... 308 STATUS Output when Sleep Mode is Canceled by Interrupt................................. 309 STATUS Output when Sleep Mode is Canceled by Power-on Reset...................... 309 STATUS Output when Sleep Mode is Canceled by Manual Reset......................... 310 On-Chip Oscillation Circuits Block Diagram of CPG ........................................................................................... 313 Block Diagram of WDT .......................................................................................... 323 Writing to WTCNT and WTCSR............................................................................ 327 Points for Attention when Using Crystal Resonator................................................ 329 Points for Attention when Using PLL Oscillator Circuit ........................................ 330 Bus State Controller (BSC) Block Diagram of BSC............................................................................................ 333 Address Space ......................................................................................................... 337 Normal Space Basic Access Timing (Access Wait 0)............................................. 390 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)...... 392 Figure 12.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0)...... 393 Figure 12.6 Example of 32-Bit Data-Width SRAM Connection ................................................ 394 Figure 12.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 395 Figure 12.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 395 Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only) ............................... 396 Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion by WAIT Signal)........................................................................................................ 397 Figure 12.11 CSn Assert Period Expansion................................................................................ 398 Figure 12.12 Example of 32-Bit Data-Width SDRAM Connection ........................................... 400 Figure 12.13 Example of 16-Bit Data-Width SDRAM Connection ........................................... 401 Figure 12.14 Burst Read Basic Timing (Auto Precharge) .......................................................... 416 Figure 12.15 Burst Read Wait Specification Timing (Auto Precharge) ..................................... 417 Figure 12.16 Basic Timing for Single Read (Auto Precharge)................................................... 418 Figure 12.17 Basic Timing for Burst Write (Auto Precharge).................................................... 420 Figure 12.18 Basic Timing for Single Write (Auto-Precharge).................................................. 421 Figure 12.19 Burst Read Timing (No Auto Precharge) .............................................................. 423 Figure 12.20 Burst Read Timing (Bank Active, Same Row Address) ....................................... 424 Figure 12.21 Burst Read Timing (Bank Active, Different Row Addresses) .............................. 425 Figure 12.22 Single Write Timing (No Auto Precharge)............................................................ 426 Figure 12.23 Single Write Timing (Bank Active, Same Row Address) ..................................... 427 Figure 12.24 Single Write Timing (Bank Active, Different Row Addresses) ............................ 428 Figure 12.25 Auto-Refresh Timing ............................................................................................ 430 Rev. 1.00 Dec. 27, 2005 Page xxix of xlii Figure 12.26 Figure 12.27 Figure 12.28 Figure 12.29 Figure 12.30 Figure 12.31 Figure 12.32 Figure 12.33 Figure 12.34 Figure 12.35 Figure 12.36 Figure 12.37 Figure 12.38 Figure 12.39 Figure 12.40 Figure 12.41 Figure 12.42 Figure 12.43 Figure 12.44 Figure 12.45 Figure 12.46 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Self-Refresh Timing .............................................................................................. 432 Access Timing in Low-Frequency Mode .............................................................. 433 Access Timing in Power-Down Mode .................................................................. 434 Write Timing for SDRAM Mode Register (Based on JEDEC)............................. 437 EMRS Command Issue Timing............................................................................. 439 Transition Timing in Deep Power-Down Mode.................................................... 440 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits, 16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2, Access Wait for 2nd Time and after = 1).............................................................. 442 Basic Access Timing for Byte-Selection SRAM (BAS = 0) ................................. 443 Basic Access Timing for Byte-Selection SRAM (BAS = 1) ................................. 444 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)........... 445 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............. 446 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............. 446 Example of PCMCIA Interface Connection.......................................................... 448 Basic Access Timing for PCMCIA Memory Card Interface................................. 449 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Wait = 1, Hardware Wait = 1) .............................. 449 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B10, CS6BWCR.SA[1:0] = B10)................................................................................. 450 Basic Timing for PCMCIA I/O Card Interface ..................................................... 451 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Wait = 1, Hardware Wait = 1) .............................. 452 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Waits = 3) .......................... 452 Burst ROM (Clock Synchronous) Access Timing (Burst Length = 8, Wait Cycles inserted in First Access = 2, Wait Cycles inserted in Second and Subsequent Accesses = 1)..................................................................................... 453 Bus Arbitration Timing ......................................................................................... 456 Direct Memory Access Controller (DMAC) Block Diagram of DMAC ....................................................................................... 460 DMA Transfer Flowchart........................................................................................ 476 Round-Robin Mode................................................................................................. 480 Changes in Channel Priority in Round-Robin Mode............................................... 481 Data Flow in Dual Address Mode ........................................................................... 483 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary memory, Destination: Ordinary memory) ................................. 484 Figure 13.7 Data Flow in Single Address Mode......................................................................... 485 Figure 13.8 Example of DMA Transfer Timing in Single Address Mode ................................. 486 Rev. 1.00 Dec. 27, 2005 Page xxx of xlii Figure 13.9 DMA Transfer Example in Cycle-Steal Mode (Dual Address, DREQ Low Level Detection)......................................................... 487 Figure 13.10 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)....................................................... 487 Figure 13.11 Bus State when Multiple Channels are Operating ................................................. 489 Figure 13.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 490 Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 490 Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 491 Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection .................... 491 Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection) ............... 491 Figure 13.17 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle = 1, Longword Access to 16-bit Device)...................................................................... 492 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Timer Unit (TMU) TMU Block Diagram............................................................................................... 496 Setting Count Operation .......................................................................................... 501 Auto-Reload Count Operation................................................................................. 501 Count Timing when Internal Clock Is Operating .................................................... 502 UNF Set Timing ...................................................................................................... 503 Status Flag Clear Timing......................................................................................... 503 Realtime Clock (RTC) RTC Block Diagram................................................................................................ 506 Setting Time ............................................................................................................ 525 Reading Time .......................................................................................................... 526 Using Alarm Function ............................................................................................. 527 Example of Crystal Oscillator Circuit Connection .................................................. 528 Using Periodic Interrupt Function ........................................................................... 529 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 Block Diagram of SCIF........................................................................................... 533 Figure 16.2 Data Format in Asynchronous Communication (Example of 8-Bit Data with Parity and 2 Stop Bits) ............................................................................................ 561 Figure 16.3 Sample the SCIF Initialization Flowchart ............................................................... 564 Figure 16.4 Sample Serial Transmission Flowchart ................................................................... 565 Figure 16.5 Example of Transmit Operation (Example of 8-Bit Data with Parity and 1 Stop Bit) ............................................................................................................... 567 Figure 16.6 Sample Serial Reception Flowchart (1)................................................................... 568 Figure 16.7 Sample Serial Reception Flowchart (2)................................................................... 569 Figure 16.8 Example of SCIF Receive Operation (Example of 8-Bit Data with Parity and 1 Stop Bit) ............................................................................................................... 571 Figure 16.9 CTS Control Operation ........................................................................................... 571 Rev. 1.00 Dec. 27, 2005 Page xxxi of xlii Figure 16.10 Figure 16.11 Figure 16.12 Figure 16.13 Figure 16.14 Figure 16.15 Figure 16.16 Figure 16.17 Figure 16.18 Figure 16.19 Figure 16.20 RTS Control Operation ......................................................................................... 572 Data Format in Clock Synchronous Communication............................................ 572 Sample the SCIF Initialization Flowchart ............................................................. 574 Sample Serial Transmission Flowchart ................................................................. 575 Example of the SCIF Transmit Operation............................................................. 576 Sample Serial Reception Flowchart ...................................................................... 577 Sample Serial Reception Flowchart ...................................................................... 578 Example of the SCIF Receive Operation .............................................................. 579 Sample Serial Data Transmission/Reception Flowchart ....................................... 581 Receive Data Sampling Timing in Asynchronous Mode ...................................... 584 Sample Transfer of Synchronous Clock by DMAC .............................................. 585 Section 17 Serial I/O with FIFO (SIOF) Figure 17.1 Block Diagram of SIOF .......................................................................................... 588 Figure 17.2 Serial Clock Supply................................................................................................. 613 Figure 17.3 Serial Data Synchronization Timing ....................................................................... 615 Figure 17.4 SIOF Transmit/Receive Timing .............................................................................. 616 Figure 17.5 Transmit/Receive Data Bit Alignment .................................................................... 618 Figure 17.6 Control Data Bit Alignment .................................................................................... 619 Figure 17.7 Control Data Interface (Slot Position)..................................................................... 620 Figure 17.8 Control Data Interface (Secondary FS) ................................................................... 621 Figure 17.9 Example of Transmission Operation in Master Mode............................................. 624 Figure 17.10 Example of Reception Operation in Master Mode ................................................ 625 Figure 17.11 Example of Transmission Operation in Slave Mode............................................. 626 Figure 17.12 Example of Reception Operation in Slave Mode .................................................. 627 Figure 17.13 Transmission and Reception Timings (8-Bit Monaural Data (1)) ......................... 631 Figure 17.14 Transmission and Reception Timings (8-Bit Monaural Data (2)) ......................... 631 Figure 17.15 Transmission and Reception Timings (16-Bit Monaural Data (1)) ....................... 632 Figure 17.16 Transmission and Reception Timings (16-Bit Stereo Data (1)) ............................ 632 Figure 17.17 Transmission and Reception Timings (16-Bit Stereo Data (2)) ............................ 633 Figure 17.18 Transmission and Reception Timings (16-Bit Stereo Data (3)) ............................ 633 Figure 17.19 Transmission and Reception Timings (16-Bit Monaural Data (2)) ....................... 634 Section 18 Ethernet Controller (EtherC) Figure 18.1 Configuration of EtherC.......................................................................................... 638 Figure 18.2 EtherC Data Path and Various Settings................................................................... 707 Figure 18.3 EtherC Transmitter State Transitions ...................................................................... 708 Figure 18.4 EtherC Receiver State Transmissions ..................................................................... 710 Figure 18.5 Example of External CAM Connection .................................................................. 714 Figure 18.6 External CAM Signal Timing ................................................................................. 716 Figure 18.7 (1) MII Frame Transmit Timing (Normal Transmission)........................................ 717 Rev. 1.00 Dec. 27, 2005 Page xxxii of xlii Figure 18.7 (2) MII Frame Transmit Timing (Collision)............................................................ 717 Figure 18.7 (3) MII Frame Transmit Timing (Transmit Error)................................................... 718 Figure 18.7 (4) MII Frame Receive Timing (Normal Reception)............................................... 718 Figure 18.7 (5) MII Frame Receive Timing (Reception Error (1))............................................. 718 Figure 18.7 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 718 Figure 18.8 MII Management Frame Format ............................................................................. 719 Figure 18.9 (1) 1-Bit Data Write Flowchart ............................................................................... 720 Figure 18.9 (2) Bus Release Flowchart (TA in Read in Figure 18.8) ......................................... 721 Figure 18.9 (3) 1-Bit Data Read Flowchart ................................................................................ 721 Figure 18.9 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 18.8)................ 722 Figure 18.10 Changing IPG and Transmission Efficiency ......................................................... 723 Figure 18.11 Diagram of Qtag Additional Functions ................................................................. 724 Figure 18.12 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)...... 724 Figure 18.13 Example of Connection to DP83847 ..................................................................... 725 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 728 Figure 19.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 755 Figure 19.3 Relationship between Receive Descriptor and Receive Buffer ............................... 761 Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) ................................ 768 Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor) ............................... 770 Figure 19.6 E-DMAC Operation after Transmit Error ............................................................... 771 Figure 19.7 E-DMAC Operation after Receive Error................................................................. 772 Figure 19.8 Configuration of ARBUSY ..................................................................................... 773 Figure 19.9 Summary of Receive FIFO Overflow Alert Signal ................................................. 774 Figure 19.10 ARBUSY Signal Change and Minimum Pulse Width Depending on Increase and Decrease of FIFO ............................................................................. 775 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Figure 24.4 Figure 24.5 Figure 24.6 Figure 24.7 User Debugging Interface (H-UDI) Block Diagram of H-UDI........................................................................................ 791 TAP Controller State Transitions ............................................................................ 802 H-UDI Data Transfer Timing.................................................................................. 804 H-UDI Reset............................................................................................................ 804 Electrical Characteristics Power On/Off Sequence .......................................................................................... 856 EXTAL Clock Input Timing ................................................................................... 861 CKIO Clock Input Timing....................................................................................... 861 CKIO Clock Output Timing.................................................................................... 862 Power-On Oscillation Settling Time ....................................................................... 862 Oscillation Settling Time at Standby Return (Return by Reset).............................. 862 Oscillation Settling Time at Standby Return (Return by NMI)............................... 863 Rev. 1.00 Dec. 27, 2005 Page xxxiii of xlii Figure 24.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0 and IRL3 to IRL0)......................................................... 863 Figure 24.9 PLL Synchronization Settling Time by Reset or NMI ............................................ 863 Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts ................................. 864 Figure 24.11 PLL Synchronization Settling Time when Frequency Multiplication Ratio Modified...................................................................................................... 864 Figure 24.12 Reset Input Timing................................................................................................ 866 Figure 24.13 Interrupt Signal Input Timing................................................................................ 866 Figure 24.14 Bus Release Timing .............................................................................................. 866 Figure 24.15 Pin Drive Timing at Standby................................................................................. 867 Figure 24.16 IRQOUT Output Delay Time................................................................................ 867 Figure 24.17 Basic Bus Cycle (No Wait) ................................................................................... 870 Figure 24.18 Basic Bus Cycle (One Software Wait) .................................................................. 871 Figure 24.19 Basic Bus Cycle (One External Wait) ................................................................... 872 Figure 24.20 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM bit = 0), No Idle Cycle Setting) .......................................................................................... 873 Figure 24.21 Burst ROM Read Cycle (One Access Wait, One External Wait, One Burst Wait, Two Bursts)................................................................................ 874 Figure 24.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle)........................................... 875 Figure 24.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)........................................... 876 Figure 24.24 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4), (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)............... 877 Figure 24.25 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4), (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle)............... 878 Figure 24.26 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 2 Cycle) ..................................................................... 879 Figure 24.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle) ........................................ 880 Figure 24.28 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4), (Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) ........................................ 881 Figure 24.29 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4), (Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) ........................................ 882 Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, ACTV + READ Commands, CAS Latency = 2, TRCD = 1 Cycle) .................................................................................................. 883 Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, READ Command, Same Row Address, CAS Latency = 2, TRCD = 1 Cycle) .................................................................... 884 Rev. 1.00 Dec. 27, 2005 Page xxxiv of xlii Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, PRE + ACTV + READ Commands, Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)............................................. 885 Figure 24.33 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, ACTV + WRITE Commands, TRCD = 1 Cycle, TRWL = 1 Cycle) ................................................................................................. 886 Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, WRITE Command, Same Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle) .................................................................... 887 Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, PRE + ACTV + WRITE Commands, Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle) ............................. 888 Figure 24.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle) .............................. 889 Figure 24.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle) ................................ 890 Figure 24.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle)................... 891 Figure 24.39 PCMCIA Memory Card Interface Bus Timing ..................................................... 892 Figure 24.40 PCMCIA Memory Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, One Software Wait, One Hardware Wait)............................ 893 Figure 24.41 PCMCIA I/O Card Interface Bus Timing.............................................................. 894 Figure 24.42 PCMCIA I/O Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, One Software Wait, One Hardware Wait)............................ 895 Figure 24.43 REFOUT Delay Time ........................................................................................... 895 Figure 24.44 Access Timing in Low-Frequency Mode (Auto Precharge).................................. 897 Figure 24.45 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode) ......................................................................................... 898 Figure 24.46 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode) ......................................................................................... 899 Figure 24.47 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle, Low-Frequency Mode) ......................................................................................... 900 Figure 24.48 DREQn Input Timing ............................................................................................ 901 Figure 24.49 TENDn, DACKn Output Timing .......................................................................... 901 Figure 24.50 Oscillation Settling Time when RTC Crystal Oscillator is Turned On ................. 902 Figure 24.51 SCIFnCK Input Clock Timing .............................................................................. 903 Figure 24.52 SCIF Input/Output Timing in Clock Synchronous Mode...................................... 904 Figure 24.53 SIOMCLK Input Timing....................................................................................... 905 Figure 24.54 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time)............... 905 Figure 24.55 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time).............. 906 Figure 24.56 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time)............... 906 Figure 24.57 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time).............. 907 Figure 24.58 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2)..................... 907 Rev. 1.00 Dec. 27, 2005 Page xxxv of xlii Figure 24.59 Figure 24.60 Figure 24.61 Figure 24.62 Figure 24.63 Figure 24.64 Figure 24.65 Figure 24.66 Figure 24.67 Figure 24.68 Figure 24.69 Figure 24.70 Figure 24.71 Figure 24.72 Figure 24.73 Figure 24.74 Figure 24.75 Figure 24.76 MII Transmit Timing (Normal Operation)............................................................ 909 MII Transmit Timing (Case of Conflict)............................................................... 909 MII Receive Timing (Normal Operation) ............................................................. 910 MII Receive Timing (Case of Error) ..................................................................... 910 MDIO Input Timing .............................................................................................. 910 MDIO Output Timing ........................................................................................... 910 WOL Output Timing ............................................................................................. 911 EXOUT Output Timing......................................................................................... 911 CAMSEN Input Timing ........................................................................................ 911 ARBUBY Output Timing ..................................................................................... 911 I/O Port Timing ..................................................................................................... 912 TCK Input Timing................................................................................................. 913 TRST Input Timing (Reset Hold).......................................................................... 914 H-UDI Data Transfer Timing................................................................................ 914 ASEMD0 Input Timing......................................................................................... 914 ASEBRKAK Delay Time ..................................................................................... 914 Output Load Circuit .............................................................................................. 915 Load Capacitance vs. Delay Time......................................................................... 916 Appendix Figure B.1 Package Dimensions (HQFP2828-256 (FP-256G/GV))........................................... 926 Figure B.2 Package Dimensions (P-LFBGA1717-256 (BP-256H/HV)) .................................... 927 Rev. 1.00 Dec. 27, 2005 Page xxxvi of xlii Tables Section 1 Overview Table 1.1 Pin Assigument ....................................................................................................... 10 Table 1.2 Pin Functions .......................................................................................................... 19 Section 2 CPU Table 2.1 Logical Address Space............................................................................................ 30 Table 2.2 Register Initial Values............................................................................................. 33 Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions......................... 45 Table 2.4 CPU Instruction Formats ........................................................................................ 49 Table 2.5 CPU Instruction Types............................................................................................ 52 Table 2.6 Data Transfer Instructions....................................................................................... 56 Table 2.7 Arithmetic Operation Instructions .......................................................................... 58 Table 2.8 Logic Operation Instructions .................................................................................. 60 Table 2.9 Shift Instructions..................................................................................................... 61 Table 2.10 Branch Instructions ................................................................................................. 62 Table 2.11 System Control Instructions.................................................................................... 63 Table 2.12 Operation Code Map............................................................................................... 66 Section 3 DSP Operating Unit Table 3.1 Logical Address Space............................................................................................ 73 Table 3.2 Operation of SR Bits in Each Processing Mode ..................................................... 76 Table 3.3 RS and RE Setting Rule.......................................................................................... 82 Table 3.4 Repeat Control Instructions .................................................................................... 82 Table 3.5 Repeat Control Macros ........................................................................................... 83 Table 3.6 DSP Mode Extended System Control Instructions ................................................. 84 Table 3.7 PC Value during Repeat Control (When RC[11:0] 2) ......................................... 87 Table 3.8 Extended Repeat Control Instructions .................................................................... 91 Table 3.9 Extended System Control Instructions in DSP Mode ............................................. 96 Table 3.10 Overview of Data Transfer Instructions.................................................................. 99 Table 3.11 Modulo Addressing Control Instructions.............................................................. 101 Table 3.12 Double Data Transfer Instruction Formats ........................................................... 104 Table 3.13 Single Data Transfer Instruction Formats ............................................................. 105 Table 3.14 Destination Register in DSP Instructions.............................................................. 107 Table 3.15 Source Register in DSP Operations ...................................................................... 108 Table 3.16 DSR Register Bits................................................................................................. 109 Table 3.17 DSP Operation Instruction Formats ...................................................................... 112 Table 3.18 Correspondence between DSP Instruction Operands and Registers ..................... 112 Table 3.19 DC Bit Update Definitions.................................................................................... 114 Rev. 1.00 Dec. 27, 2005 Page xxxvii of xlii Table 3.20 Table 3.21 Table 3.22 Table 3.23 Table 3.24 Table 3.25 Table 3.26 Table 3.27 Table 3.28 Table 3.29 Table 3.30 Table 3.31 Table 3.32 Table 3.33 Table 3.34 Table 3.35 Table 3.36 Table 3.37 Table 3.38 Table 3.39 Table 3.40 Examples of NOPX and NOPY Instruction Codes............................................... 116 Variation of ALU Fixed-Point Operations............................................................ 119 Correspondence between Operands and Registers ............................................... 119 Variation of ALU Integer Operations ................................................................... 124 Variation of ALU Logical Operations .................................................................. 125 Variation of Fixed-Point Multiply Operation ....................................................... 127 Correspondence between Operands and Registers ............................................... 127 Variation of Shift Operations................................................................................ 128 Operation Definition of PDMSB .......................................................................... 134 Variation of PDMSB Operation............................................................................ 135 Variation of Rounding Operation ......................................................................... 136 Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 137 Definition of Overflow Protection for Integer Arithmetic Operations.................. 137 Variation of Local Data Move Operations............................................................ 138 Correspondence between Operands and Registers ............................................... 139 DSP Mode Extended System Control Instructions ............................................... 140 Double Data Transfer Instruction ......................................................................... 142 Single Data Transfer Instructions ......................................................................... 143 Correspondence between DSP Data Transfer Operands and Registers ................ 144 DSP Operation Instructions .................................................................................. 145 Operation Code Map............................................................................................. 151 Section 4 Exception Handling Table 4.1 Exception Event Vectors ...................................................................................... 163 Table 4.2 Instruction Positions and Restriction Types.......................................................... 173 Table 4.3 SPC Value when Re-Execution Type Exception Occurs in Repeat Control (RC[11:0] 2) ...................................................................................................... 176 Table 4.4 Exception Acceptance in Repeat Loop ................................................................. 177 Table 4.5 Instruction Where a Specific Exception Occurs when Memory Access Exception Occurs in Repeat Control (SR.RC[11:0] 1) ...................................... 178 Section 5 Memory Management Unit (MMU) Table 5.1 Access States Designated by D, C, and PR Bits ................................................... 199 Section 6 Cache Table 6.1 LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 216 Table 6.2 Way Replacement when a PREF Instruction Misses the Cache ........................... 220 Table 6.3 Way Replacement when Instructions other than the PREF Instruction Miss the Cache...................................................................................................... 220 Table 6.4 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 220 Table 6.5 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 221 Table 6.6 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 221 Rev. 1.00 Dec. 27, 2005 Page xxxviii of xlii Section 7 X/Y Memory Table 7.1 X/Y Memory Logical Addresses .......................................................................... 231 Table 7.2 MMU and Cache Settings..................................................................................... 234 Section 8 Interrupt Controller (INTC) Table 8.1 Pin Configuration.................................................................................................. 237 Table 8.2 Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 240 Table 8.3 Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 243 Table 8.4 Interrupt Level and INTEVT Code....................................................................... 245 Table 8.5 Interrupt Sources and IPRA to IPRI ..................................................................... 247 Section 9 User Break Controller Table 9.1 Specifying Break Address Register ...................................................................... 269 Table 9.2 Specifying Break Data Register............................................................................ 271 Table 9.3 Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 284 Section 10 Power-Down Modes Table 10.1 States of Power-Down Modes .............................................................................. 296 Table 10.2 Pin Configuration.................................................................................................. 298 Table 10.3 Register States in Software Standby Mode........................................................... 303 Section 11 On-Chip Oscillation Circuits Table 11.1 Pin Configuration.................................................................................................. 315 Table 11.2 Clock Operating Modes ........................................................................................ 315 Table 11.3 Possible Combination of Clock Mode and FRQCR Values.................................. 317 Section 12 Bus State Controller (BSC) Table 12.1 Pin Configuration.................................................................................................. 334 Table 12.2 Address Space Map 1 (CMNCR.MAP = 0).......................................................... 338 Table 12.3 Address Space Map 2 (CMNCR.MAP = 1).......................................................... 339 Table 12.4 Correspondence between External Pins (MD3 and MD4), Memory Type of CS0, and Memory Bus Width............................................................................... 340 Table 12.5 Correspondence between External Pin (MD5) and Endians ................................. 340 Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment ......................... 384 Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment ......................... 385 Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment........................... 386 Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment ...................... 387 Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment ...................... 388 Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment ........................ 389 Table 12.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1............................................................................ 402 Table 12.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2............................................................................ 404 Rev. 1.00 Dec. 27, 2005 Page xxxix of xlii Table 12.13 Table 12.13 Table 12.14 Table 12.15 Table 12.15 Table 12.16 Table 12.16 Table 12.17 Table 12.17 Table 12.18 Table 12.19 Table 12.20 Table 12.21 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 ........................................................................... 405 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 ........................................................................... 406 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)............................................................................... 408 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 ........................................................................... 409 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-2 ........................................................................... 410 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 ........................................................................... 411 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-2 ........................................................................... 412 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-1 ........................................................................... 413 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-2 ........................................................................... 414 Relationship between Access Size and Number of Bursts.................................... 415 Access Address in SDRAM Mode Register Write ............................................... 435 Output Addresses when EMRS Command is Issued ............................................ 438 Relationship between Bus Width, Access Size, and Number of Bursts................ 441 Section 13 Direct Memory Access Controller (DMAC) Table 13.1 Pin Configuration.................................................................................................. 461 Table 13.2 DMARS Setting.................................................................................................... 474 Table 13.3 Selecting External Request Modes with RS Bits .................................................. 477 Table 13.4 Selecting External Request Detection with DL, DS Bits ...................................... 478 Table 13.5 Selecting External Request Detection with DO Bit .............................................. 478 Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 479 Table 13.7 Supported DMA Transfers.................................................................................... 482 Table 13.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 488 Section 14 Timer Unit (TMU) Table 14.1 TMU Interrupt Sources......................................................................................... 504 Section 15 Realtime Clock (RTC) Table 15.1 Pin Configuration.................................................................................................. 507 Table 15.2 Recommended Oscillator Circuit Constants (Recommended Values).................. 528 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 Pin Configuration.................................................................................................. 534 Rev. 1.00 Dec. 27, 2005 Page xl of xlii Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Relationship between n and Clock........................................................................ 553 SCSMR Settings for Serial Transfer Format Selection......................................... 560 SCSMR and SCSCR Settings for the SCIF Clock Source Selection .................... 560 Serial Transfer Formats......................................................................................... 562 The SCIF Interrupt Sources .................................................................................. 583 Section 17 Serial I/O with FIFO (SIOF) Table 17.1 Pin Configuration.................................................................................................. 589 Table 17.2 SIOF Serial Clock Frequency ............................................................................... 614 Table 17.3 Serial Transfer Modes........................................................................................... 616 Table 17.4 Frame Length........................................................................................................ 617 Table 17.5 Audio Mode Specification for Transmit Data....................................................... 619 Table 17.6 Audio Mode Specification for Receive Data ........................................................ 619 Table 17.7 Setting for Number of Control Data Channels...................................................... 620 Table 17.8 Conditions to Issue Transmit Request .................................................................. 622 Table 17.9 Conditions to Issue Receive Request .................................................................... 622 Table 17.10 Transmission and Reception Reset ....................................................................... 628 Table 17.11 SIOF Interrupt Sources ......................................................................................... 629 Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag.......................................... 630 Section 18 Ethernet Controller (EtherC) Table 18.1 Pin Configuration.................................................................................................. 639 Table 18.2 Transfer Frame Processing (Without CAM)......................................................... 711 Table 18.3 Reception Frame Process...................................................................................... 713 Table 18.4 Relay Frame Process (With CAM) ....................................................................... 713 Table 18.5 Receive Frame Process (When External CAM Logic is Used)............................. 715 Table 18.6 Relay Frame Process (When External CAM Logic is Used) ................................ 716 Section 20 Pin Function Controller (PFC) Table 20.1 List of Multiplexed Pins (1).................................................................................. 779 Table 20.2 List of Multiplexed Pins (2).................................................................................. 780 Section 21 I/O Ports Table 21.1 Port A Data Register (PADR) Read/Write Operations ......................................... 788 Table 21.2 Port B Data Register (PBDR) Read/Write Operations (1) .................................... 789 Table 21.3 Port B Data Register (PBDR) Read/Write Operations (2) .................................... 789 Table 21.4 Port C Data Register (PCDR) Read/Write Operations.......................................... 790 Section 22 User Debugging Interface (H-UDI) Table 22.1 Pin Configuration.................................................................................................. 792 Table 22.2 H-UDI Commands................................................................................................ 794 Table 22.3 This LSI's Pins and Boundary Scan Register Bits................................................ 795 Table 22.4 Reset Configuration .............................................................................................. 803 Rev. 1.00 Dec. 27, 2005 Page xli of xlii Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings ................................................................................. 855 Table 24.2 DC Characteristics (1) .......................................................................................... 857 Table 24.2 DC Characteristics (2) .......................................................................................... 858 Table 24.3 Permitted Output Current Values.......................................................................... 859 Table 24.4 Maximum Operating Frequencies......................................................................... 859 Table 24.5 Clock Timing ........................................................................................................ 860 Table 24.6 Control Signal Timing .......................................................................................... 865 Table 24.7 Bus Timing (1)...................................................................................................... 868 Table 24.8 Bus Timing (2)...................................................................................................... 896 Table 24.9 DMAC Signal Timing .......................................................................................... 901 Table 24.10 RTC Signal Timing............................................................................................... 902 Table 24.11 SCIF Module Signal Timing................................................................................. 903 Table 24.12 SIOF Module Signal Timing ................................................................................ 904 Table 24.13 Ethernet Controller Timing................................................................................... 908 Table 24.14 Port Input/Output Timing ..................................................................................... 912 Table 24.15 H-UDI Related Pin Timing................................................................................... 913 Rev. 1.00 Dec. 27, 2005 Page xlii of xlii Section 1 Overview and Pin Function Section 1 Overview and Pin Function This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the SuperH architecture. Its core is a RISC-type CPU with a Digital Signal Processor (DSP) as a functional extension. A single chip microprocessor integrates peripheral functions required for building an Ethernet system. The LSI comprises two channels of Ethernet controllers. They include a media access controller (MAC) and a media independent interface (MII) standard unit that conforms to the IEE802.3u standard and provide 10/100 Mbps LAN connection. The LSI has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip X/Y memory, and an interrupt controller for system configuration to enable flexible system design. It supports highspeed data transfer using an on-chip direct memory access controller (DMAC). Its external memory access support provides direct connection to various types of memory. The strong on-chip power saving function reduces power consumption even during high-speed operation. 1.1 Features The features of this LSI are shown below. CPU: * * * * Original Renesas-Technology SuperH architecture Compatible with SH-1, SH-2, and SH-3 at object code level 32-bit internal data bus Various groups of built-in registers General registers: Sixteen 32-bit registers (including eight 32-bit bank registers) Control registers: Five 32-bit registers System registers: Four 32-bit registers * Supports RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load/store architecture Delayed branch instructions Instruction set based on C language * Instruction execution time: one instruction/cycle for basic instructions * Logical address space: 4 Gbytes Rev. 1.00 Dec. 27, 2005 Page 1 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function * Space identifier ASID: 8 bits, 256 logical address spaces * Supports five-stage pipeline DSP: * * * * * Mixture of 16-bit and 32-bit instructions 32-/40-bit internal data bus Multiplier, ALU, and barrel shifter 16-bit x 16-bit 32-bit one cycle multiplier Large-capacity DSP data registers Six 32-bit data registers Two 40-bit data registers Supports extended harvard architecture for DSP data bus Two data buses One instruction bus Maximum four parallel operations ALU, multiply, and two load/store Two addressing units to generate addresses for two memory access Supports DSP data addressing modes Increment and indexing (with or without modulo addressing) Zero-overhead repeat loop control Conditional execution instructions Supports user DSP mode and privileged DSP mode * * * * * * * Memory management unit (MMU): * 4 Gbytes of address space, 256 address spaces (8-bit ASID) * Page unit sharing * Supports multiple page sizes 1 kbyte or 4 kbytes * Supports 128-entry, 4-way set associative TLB * Supports software selection of replacement way and random-replacement algorithms * Contents of TLB are directly accessible by address mapping Rev. 1.00 Dec. 27, 2005 Page 2 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Cache memory: * * * * 32-kbyte cache, mixture of instructions and data 512-entry, 4-way set associative, 16-byte block length Write-back, write-through, LRU replacement algorithm 1-stage write-back buffer X/Y memory: * Three independent read/write ports 8-/16-/32-bit access from the CPU Maximum two 16-bit accesses from the DSP 8-/16-/32-bit access from the DMAC or E-DMAC * A total of 16 kbytes memory (8-kbyte RAM each for X- and Y-memory) Interrupt controller (INTC): * * * * * * Supports seven external interrupt pins (NMI, IRQ5 to IRQ0) Supports fifteen level interrupt pins (IRL3 to IRL0) Supports one interrupt request output pin (IRQOUT) On-chip peripheral interrupt: Priority level is independently selected for each module Supports software vector mode Selection of falling/rising/high/low User break controller (UBC): * Address, data value, access type, and data size are available for setting as break conditions * Supports the sequential break function * Two break channels On-Chip Oscillation Circuits: * Clock source selectable between an external supply (EXTAL or CKIO) and crystal resonator The internal clock and peripheral clock can be adjusted by setting the PLL circuit and division ratio. * Three types of clocks generated: CPU clock (I clock): 200 MHz (max) Bus clock (B clock): 66 MHz (max) Peripheral clock (P clock): 33 MHz (max) Rev. 1.00 Dec. 27, 2005 Page 3 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function * Supports power-down modes: Sleep mode Software standby mode Module standby mode * A single channel on-chip watch dog timer Watchdog timer mode and interval timer mode is selectable. An interrupt can be generated in interval timer mode. Bus state controller (BSC): * Physical address space is divided into eight areas: area 0, areas 2 to 4; each a maximum of 64 Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum of 32 Mbytes. * The following features are settable for each area. Bus size (8, 16 or 32 bits): The supported bus size differs for each area. Number of access wait cycles: Numbers of wait-state cycles during reading and writing are independently selectable for some areas. Setting of idle wait cycles: For the same area or different area. Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, burst ROM (synchronization/asynchronous), SDRAM and PCMCIA. * Outputs chip select signal (CS0, CS2 to CS4, CS5A/B, and CS6A/B) for corresponding area (The CS assert/negate timing can be selected by software.) Direct memory access controller (DMAC): * Six channels. Two of these channels (ch0 and ch1) support external requests. * Supports burst mode and cycle-stealing mode Timer unit (TMU): * 3-channel auto reload 32-bit on-chip timer * 4 types of counter input clocks can be selected Realtime clock (RTC)*1: * On-chip clock, calendar, and alarm * On-chip 32 kHz crystal oscillator with 1/256-second resolution (interrupt cycle) Rev. 1.00 Dec. 27, 2005 Page 4 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Serial communication interface with FIFO (SCIF): * * * * * * 16 bytes each for transmit/receive FIFO Two channels (SCIF0 and SCIF1) CTS/RTS (flow control) support Asynchronous and synchronous modes Full-duplex communication support DMA transfer Serial I/O with FIFO (SIOF): * * * * * 64 bytes each for transmit/receive FIFO 8-/16-/16-bit stereo-audio input/output supported Two channels (SIOF0 and SIOF1) DMA transfer Frame synchronous signal Ethernet controller (EtherC): * * * * * * * * * * * * MAC (Media Access Control) Data frame assembly/disassembly (frame format conforming to IEEE802.3u) CSMA/CD link management (collision prevention and collision processing) CRC processing Full-duplex transmit/receive support Detects short frames and long frames Conforms to MII (Media Independent Interface) standard *2 Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream Station management (STA function) 10/100 Mbps transfer rate adjustable WOL (Wake-On-LAN) signal output with Magic Packet*3 detection CAM sense signal input Ethernet Controller Direct Memory Access Controller (E-DMAC): * * * * EtherC Transfer between external and internal memories 16-byte burst transfer Single address transfer Chain block transfer Rev. 1.00 Dec. 27, 2005 Page 5 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function * Transfer data width: 32 bits * Address space: 4 Gbytes * On-chip FIFO (2-kbytes each for transmit/receive) User debugging interface (H-UDI): * Supports the E10A emulator * Realtime branch trace * 1-kbyte of on-chip RAM for executing the high-speed emulation program Notes: 1. As the power supply is connected, power should always be supplied to all power supplies even if only RTC operates. 2. +5 V I/O is not supported. 3. Magic Packet is the registered trademark of Advanced Micro Devices Inc. Product Lineup: Power supply voltage Abbreviation SH7712 I/O Internal Maximum operating frequency Type name 200 MHz Package 3.3 V 0.3 V 1.5 V 0.1 V HD6417712BP/BPV 256-pin CSP (BP-256H/HV) HD6417712F/FV 256-pin HQFP (FP-256G/GV) Rev. 1.00 Dec. 27, 2005 Page 6 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function 1.2 Block Diagram User break controller (UBC) Advanced user debugger (AUD) SuperH CPU core DSP core L bus CPU bus (I clock) X bus Y bus X/Y memory Instructions/data for CPU/DSP 16 kbytes Cache access controller (CCN) Cache memory 32 kbytes Memory management unit (MMU) Internal bus (B clock) Bus state controller (BSC) Peripheral bus controller Direct memory access controller (DMAC) Transmit FIFO (2 kbytes) Ethernet controller direct memory access controller (E-DMAC) Receive FIFO (2 kbytes) Ethernet controller 0 (EtherC0) Transfer FIFO Transfer FIFO (3 kbytes) (3 kbytes) Ethernet 0 External bus Transmit FIFO (2 kbytes) Receive FIFO (2 kbytes) Ethernet controller 1 (EtherC1) Ethernet 1 Peripheral bus (P clock) 128-byte SRAM Serial I/O with FIFO (SIOF)* Serial communication interface with FIFO (SCIF)* User debugging interface (H-UDI) Interrupt controller (INTC) Realtime clock (RTC) Timer unit (TMU) On-chip oscillation circuits (CPG) (WDT) Note: * SCIF and SIOF have two channels respectively. Figure 1.1 Block Diagram Rev. 1.00 Dec. 27, 2005 Page 7 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function 1.3 1.3.1 Pin Description Pin Assignment VccQ(3.3V) VssQ(0V) VccQ(3.3V) MD5 MD4 VssQ(0V) VssQ(0V) VccQ(3.3V) CAMSEN0/IRQ4 EXOUT0/TEND0 LNKSTA0 WOL0 MDIO0 MDC0 ERXD03 Vss(0V) Vcc(1.5V) ERXD02 ERXD01 ERXD00 RX-DV0 RX-CLK0 RX-ER0 TX-ER0 VssQ(0V) VccQ(3.3V) TX-CLK0 TX-EN0 ETXD00 ETXD01 ETXD02 ETXD03 COL0 Vss(0V) Vcc(1.5V) CRS0 CAMSEN1/IRQ5 EXOUT1/TEND1 LNKSTA1 WOL1 MDIO1 MDC1 ERXD13 VssQ(0V) VccQ(3.3V) Vss(0V) Vcc(1.5V) ERXD12 ERXD11 ERXD10 RX-DV1 RX-CLK1 RX-ER1 TX-ER1 TX-CLK1 VssQ(0V) VccQ(3.3V) TX-EN1 ETXD10 ETXD11 ETXD12 ETXD13 COL1 CRS1 Rev. 1.00 Dec. 27, 2005 Page 8 of 932 REJ09B0269-0100 REFOUT/IRQOUT/ARBUSY BREQ VccQ(3.3V) VssQ(0V) BACK CS0 CS4 CS5A CS6A WAIT RD BS VccQ(3.3V) VssQ(0V) Vcc(1.5V) Vss(0V) D0 D1 D2 D3 D4 D5 D6 D7 VccQ(3.3V) VssQ(0V) D8 D9 D10 D11 D12 D13 D14 D15 Vcc(1.5V) Vss(0V) WE0(BE0)/DQMLL WE1(BE1)/DQMLU/WE RD/WR CKIO CAS CKE VccQ(3.3V) VssQ(0V) RAS CS2 CS3 A0 Vcc(1.5V) Vss(0V) A1 A2 A3 A4 A5 A6 VccQ(3.3V) VssQ(0V) A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VccQ-RTC(3.3V) XTAL2 EXTAL2 VssQ-RTC(0V) ASEMD0 TDI TMS TDO TRST TCK ASEBRKAK AUDSYNC AUDCK Vcc(1.5V) Vss(0V) VccQ(3.3V) VssQ(0V) AUDATA3 AUDATA2 AUDATA1 AUDATA0 RESETM RESETP NMI IRQ0/IRL0 IRQ1/IRL1 IRQ2/IRL2 IRQ3/IRL3 Vcc(1.5V) Vss(0V) STATUS0 STATUS1 CKIO2 DACK0 VccQ(3.3V) VssQ(0V) DACK1 DREQ0 DREQ1 PTC0/SCK_SIO1 PTC1/SIOMCLK1 PTC2/RXD_SIO1 Vcc(1.5V) Vss(0V) PTC3/TXD_SIO1 PTC4/SIOFSYNC1 PTC5/CE2A PTC6/CE2B VccQ(3.3V) VssQ(0V) PTC7/IOIS16 CS5B/CE1A CS6B/CE1B VssQ(0V) MD0 MD1 MD2 MD3 Vcc-PLL1(1.5V) Vss-PLL1(0V) Vcc-PLL2(1.5V) Vss-PLL2(0V) XTAL EXTAL 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 HQFP2828-256 (FP-256G/GV) Top view 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VccQ(3.3V) PTA7/SIOFSYNC0 PTA6/TXD_SIO0 PTA5/RXD_SIO0 PTA4/SIOMCLK0 PTA3/SCK_SIO0 VssQ(0V) VccQ(3.3V) PTA2/SCIF0CK PTA1/TXD0 PTA0/RXD0 PTB7/RTS0 PTB6/CTS0 PTB5/SCIF1CK Vss(0V) Vcc(1.5V) PTB4/TXD1 PTB3/RXD1 PTB2/RTS1 PTB1/CTS1 VssQ(0V) VccQ(3.3V) PTB0 A25 A24 A23 A22 A21 Vss(0V) Vcc(1.5V) A20 A19 A18 D31 D30 VssQ(0V) VccQ(3.3V) D29 D28 D27 D26 D25 D24 D23 Vss(0V) Vcc(1.5V) VssQ(0V) VccQ(3.3V) D22 D21 D20 D19 D18 D17 D16 VssQ(0V) VccQ(3.3V) WE3(BE3)/DQMUU/ICIOWR WE2(BE2)/DQMUL/ICIORD A17 A16 A15 A14 A13 Figure 1.2 Pin Assignment (HQFP2828-256(FP-256G/GV)) Section 1 Overview and Pin Function INDEX 1 A B C D E F G H J K L M N P R T U V W Y EXTAL 2 MD3 REFOUT/ IRQOUT/ ARBUSY 3 MD1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TMS 19 VssQRTC 20 VccQ VssQ CAMSEN0/ /IRQ4 CS5B/ PTC6/ CE1A CE2B MD2 Vss-PLL1 PTC2/ PTC4/ SIOFSYNC1 RXD_SIO1 DREQ0 DACK0 PTC0/ SCK_SIO1 STATUS STATUS 1 0 IRQ2/ IRL2 RESETP AUDATA0 VssQ AUDCK TRST IRQ0/ IRL0 AUDATA2 Vss ASEBRKAK VssQ CS4 CS6A VccQ XTAL VssQ VssQ Vss Vcc VssQ Vcc IRQ3/ IRL3 Vss VccQASEMD0 EXTAL2 XTAL2 RTC TDI TDO EXOUT0/ TEND0 PTC7/ PTC5/ BREQ Vcc-PLL1Vss-PLL2 Vcc-PLL2 IOIS16 CE2A VccQ CS5A CS0 BS Vss D3 MD0 CS6B/ VccQ CE1B DREQ1 VccQ NMI AUDATA1 VccQ IRQ1/ AUDATA3 IRL1 RESETM AUDSYNC VssQ VssQ PTC3/ PTC1/ TXD_SIO1 SIOMCLK1 DACK1 CKIO2 Vcc TCK VccQ VccQ MDIO0 BACK RD Vcc D2 WAIT VssQ WOL0 Vss MD5 MD4 Vcc D0 MDC0 LNKSTA0 ERXD01 D4 D6 D1 D5 ERXD00 ERXD02 ERXD03 RX-ER0 TX-ER0 RX-CLK0 RX-DV0 TX-CLK0 D8 D12 VccQ D10 D7 D9 VssQ D11 P-LFBGA1717-256 (BP-256H/HV) Top view TX-EN0 VccQ VssQ ETXD02 ETXD03 ETXD01 ETXD00 COL0 D13 D15 WE1(BE1)/ DQMLU/ WE Vss Vcc D14 WE0(BE0)/ DQMLL Vcc CAMSEN1/ IRQ5 CRS0 Vss EXOUT1/ TEND1 CKIO RD/WR VssQ VccQ LNKSTA1 MDIO1 WOL1 VccQ Vss CAS RAS Vcc ERXD13 MDC1 CKE CS2 A0 Vss CS3 A1 Vcc ERXD11 ERXD10 VssQ A4 RX-DV1 RX-ER1 TX-ER1 ERXD12 A8 A9 A3 PTB1/ CTS1 TX-CLK1 ETXD10 ETXD11 RX-CLK1 A2 VccQ A10 A5 D16 WE2(BE2)/ DQMUL/ ICIORD D20 VssQ D24 D28 D30 A19 A21 A25 Vcc PTB7/ PTA1/ VccQ RTS0 TXD0 ETXD13 VssQ A6 VssQ A11 A13 A16 A7 A14 WE3(BE3)/ DQMUU/ ICIOWR VccQ D18 D17 VccQ D22 D21 D23 Vss Vcc D25 D26 D27 D29 VccQ Vcc Vss A23 A24 PTB3/ VccQ RXD1 VssQ A22 Vss PTB5/ PTA5/ PTA6/ PTA3/ SCIF1CK RXD-SIO0 TXD-SIO0 SCK-SIO0 COL1 TX-EN1 CRS1 ETXD12 VssQ VccQ A15 VssQ A17 D19 VssQ D31 PTA0/ RXD0 PTA4/ SIOMCLK0 VccQ PTA7/ SIOFSYNC0 A12 A18 A20 PTB2/ PTB4/ PTB6/ PTB0 RTS1 TXD1 CTS0 PTA2/ SCIF0CLK Figure 1.3 Pin Assignment (P-LFBGA1717-256(BP-256H/HV)) Rev. 1.00 Dec. 27, 2005 Page 9 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Table 1.1 Pin No. (FP-256G/GV) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Assigument Pin No. (BP-256H/HV) Pin Name REFOUT/IRQOUT/ ARBUSY BREQ VccQ VssQ BACK CS0 CS4 CS5A CS6A WAIT RD BS VccQ VssQ Vcc Vss D0 D1 D2 D3 D4 D5 D6 D7 VccQ VssQ D8 D9 D10 I/O Description B2 C2 D2 B1 E2 E3 C1 D3 D1 E4 F2 F3 E1 F4 G2 G3 F1 G4 H2 H3 G1 H4 H1 J3 J2 J4 J1 K3 K2 O/O/O Bus release request output I Bus request I/O power supply (3.3 V) I/O power supply (0 V) O O O O O I O O Bus acknowledge Chip select 0 Chip select 4 Chip select 5 A Chip select 6 A Hardware wait request Read strobe Bus cycle start signal I/O power supply (3.3 V) I/O power supply (0 V) Internal power supply (1.5 V) Internal power supply (0 V) IO IO IO IO IO IO IO IO Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus I/O power supply (3.3 V) I/O power supply (0 V) IO IO IO Data bus Data bus Data bus Rev. 1.00 Dec. 27, 2005 Page 10 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pin No. (BP-256H/HV) Pin Name D11 D12 D13 D14 D15 Vcc Vss WE0(BE0)/DQMLL WE1(BE1)/DQMLU/ WE RD/WR CKIO CAS CKE VccQ VssQ RAS CS2 CS3 A0 Vcc Vss A1 A2 A3 A4 A5 A6 VccQ VssQ A7 I/O IO IO IO IO IO Description Data bus Data bus Data bus Data bus Data bus Internal power supply (1.5 V) Internal power supply (0 V) K4 K1 L1 L4 M1 L3 L2 M4 N1 M3 M2 N4 P1 N3 N2 P4 R1 P3 T1 R4 P2 R3 U1 T4 R2 U4 V1 U2 W1 V3 O/O D7 to D0-select signal/DQM (SDRAM) O/O/O D15 to D8-select signal/DQM (SDRAM)/PCMCIA write cycle strobe O IO O O Read/write System clock I/O CAS (SDRAM) CK enable (SDRAM) I/O power supply (3.3 V) I/O power supply (0 V) O O O O RAS (SDRAM) Chip select 2 Chip select 3 Address bus Internal power supply (1.5 V) Internal power supply (0 V) O O O O O O Address bus Address bus Address bus Address bus Address bus Address bus I/O power supply (3.3 V) I/O power supply (0 V) O Address bus Rev. 1.00 Dec. 27, 2005 Page 11 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Pin No. (BP-256H/HV) Pin Name A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 WE2(BE2)/DQMUL/ ICIORD WE3(BE3)/DQMUU/ ICIOWR VccQ VssQ D16 D17 D18 D19 D20 D21 D22 VccQ VssQ Vcc Vss D23 D24 D25 D26 I/O O O O O O O O O O O Description Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus T2 T3 U3 V2 Y1 W2 W3 W4 Y2 W5 V5 Y3 V4 Y4 U5 W6 V6 Y5 U6 W7 V7 Y6 U7 W8 V8 Y7 U8 Y8 V9 O/O/O D23 to D16-select signal/DQM (SDRAM)/PCMCIA I/O read O/O/O D31 to D24-select signal/DQM (SDRAM)/PCMCIA I/O write I/O power supply (3.3 V) I/O power supply (0 V) IO IO IO IO IO IO IO Data bus Data bus Data bus Data bus Data bus Data bus Data bus I/O power supply (3.3 V) I/O power supply (0 V) Internal power supply (1.5 V) Internal power supply (0 V) IO IO IO IO Data bus Data bus Data bus Data bus Rev. 1.00 Dec. 27, 2005 Page 12 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Pin No. (BP-256H/HV) Pin Name D27 D28 D29 VccQ VssQ D30 D31 A18 A19 A20 Vcc Vss A21 A22 A23 A24 A25 PTB0 VccQ VssQ PTB1/CTS1 PTB2/RTS1 PTB3/RXD1 PTB4/TXD1 Vcc Vss PTB5/SCIF1CK PTB6/CTS0 PTB7/RTS0 PTA0/RXD0 PTA1/TXD0 I/O IO IO IO Description Data bus Data bus Data bus I/O power supply (3.3 V) I/O power supply (0 V) W9 U9 Y9 V10 W10 U10 Y10 Y11 U11 Y12 V11 W11 U12 Y13 V12 W12 U13 Y14 V13 W13 U14 Y15 V14 Y16 U15 W14 V15 Y17 U16 W15 U17 IO IO O O O Data bus Data bus Address bus Address bus Address bus Internal power supply (1.5 V) Internal power supply (0 V) O O O O O IO Address bus Address bus Address bus Address bus Address bus I/O port B I/O power supply (3.3 V) I/O power supply (0 V) IO/I IO/O IO/I IO/O I/O port B/SCIF1 transmit clear I/O port B/SCIF1 transmit request I/O port B/SCIF1 receive data I/O port B/SCIF1 transmit data Internal power supply (1.5 V) Internal power supply (0 V) IO/IO IO/I IO/O IO/I IO/O I/O port B/SCIF1 serial clock I/O port B/SCIF0 transmit clear I/O port B/SCIF0 transmit request I/O port A/SCIF0 receive data I/O port A/SCIF0 transmit data Rev. 1.00 Dec. 27, 2005 Page 13 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Pin No. (BP-256H/HV) Pin Name PTA2/SCIF0CK VccQ VssQ PTA3/SCK_SIO0 PTA4/SIOMCLK0 PTA5/RXD_SIO0 PTA6/TXD_SIO0 PTA7/SIOFSYNC0 VccQ CRS1 COL1 ETXD13 ETXD12 ETXD11 ETXD10 TX-EN1 VccQ VssQ TX-CLK1 TX-ER1 RX-ER1 RX-CLK1 RX-DV1 ERXD10 ERXD11 ERXD12 Vcc Vss VccQ VssQ I/O IO/IO Description I/O port A/SCIF0 serial clock I/O power supply (3.3 V) I/O power supply (0 V) Y18 W17 Y19 V18 W16 V16 V17 W18 Y20 W19 V19 U19 W20 T19 T18 V20 U18 U20 T17 R19 R18 T20 R17 P19 P18 R20 P17 N19 N18 P20 IO/IO IO/I IO/I IO/O IO/IO I/O port A/SIOF0 communication clock I/O port A/SIOF0 clock input I/O port A/SIOF0 receive data I/O port A/SIOF0 transmit data I/O port A/SIOF0 frame sync I/O power supply (3.3 V) I I O O O O O MAC1 carrier detection MAC1 collision detection MAC1 transmit data 3 MAC1 transmit data 2 MAC1 transmit data 1 MAC1 transmit data 0 MAC1 transmit enable I/O power supply (3.3 V) I/O power supply (0 V) I O I I I I I I MAC1 transmit clock MAC1 transmit error MAC1 receive error MAC1 receive clock MAC1 receive data valid MAC1 receive data 0 MAC1 receive data 1 MAC1 receive data 2 Internal power supply (1.5 V) Internal power supply (0 V) I/O power supply (3.3 V) I/O power supply (0 V) Rev. 1.00 Dec. 27, 2005 Page 14 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Pin No. (BP-256H/HV) Pin Name ERXD13 MDC1 MDIO1 WOL1 LNKSTA1 EXOUT1/TEND1 CAMSEN1/IRQ5 CRS0 Vcc Vss COL0 ETXD03 ETXD02 ETXD01 ETXD00 TX-EN0 TX-CLK0 VccQ VssQ TX-ER0 RX-ER0 RX-CLK0 RX-DV0 ERXD00 ERXD01 ERXD02 Vcc Vss ERXD03 I/O I O IO O I O/O I/I I Description MAC1 receive data 3 MAC1 management data clock MAC1 management data I/O MAC1 Wake-On-LAN MAC1 link status MAC1 general-purpose external output/DMA transfer end notification 1 MAC1 CAM input/external interrupt request MAC0 carrier detection Internal power supply (1.5 V) Internal power supply (0 V) N17 N20 M18 M19 M17 M20 L18 L19 L17 L20 K20 K17 J20 K18 K19 J17 H20 J18 J19 H17 G20 H18 H19 G17 F20 G18 E20 F17 G19 I O O O O O I MAC0 collision detection MAC0 transmit data 3 MAC0 transmit data 2 MAC0 transmit data 1 MAC0 transmit data 0 MAC0 transmit enable MAC0 transmit clock I/O power supply (3.3 V) I/O power supply (0 V) O I I I I I I MAC0 transmit error MAC0 receive error MAC0 receive clock MAC0 receive data valid MAC0 receive data 0 MAC0 receive data 1 MAC0 receive data 2 Internal power supply (1.5 V) Internal power supply (0 V) I MAC0 receive data 3 Rev. 1.00 Dec. 27, 2005 Page 15 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 Pin No. (BP-256H/HV) Pin Name MDC0 MDIO0 WOL0 LNKSTA0 EXOUT0/TEND0 CAMSEN0/IRQ4 VccQ VssQ VssQ MD4 MD5 VccQ VssQ VccQ VccQ-RTC XTAL2 EXTAL2 VssQ-RTC ASEMD0 TDI TMS TDO TRST TCK ASEBRKAK AUDSYNC AUDCK Vcc Vss I/O O IO O I O/O I/I Description MAC0 management data clock MAC0 management data I/O MAC0 Wake-On-LAN MAC0 link status MAC0 general-purpose external output/DMA transfer end notification 0 MAC0 CAM input/external interrupt request I/O power supply (3.3 V) I/O power supply (0 V) I/O power supply (0 V) F18 D20 E17 F19 D17 C20 D19 B20 C18 E19 E18 D18 C19 A20 B19 B18 B17 A19 B16 C16 A18 C17 A17 D16 B15 C15 A16 D15 B14 I I Specifies area 0 bus width Endian select I/O power supply (3.3 V) I/O power supply (0 V) I/O power supply (3.3 V) RTC oscillator power supply (3.3 V) O I On-chip RTC crystal oscillator pin On-chip RTC crystal oscillator pin RTC oscillator power supply (0 V) I I I O I I O O O ASE mode Test data input Test mode select Test data output Test reset Test clock ASE break acknowledge AUD synchronous AUD clock Internal power supply (1.5 V) Internal power supply (0 V) Rev. 1.00 Dec. 27, 2005 Page 16 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 Pin No. (BP-256H/HV) Pin Name VccQ VssQ AUDATA3 AUDATA2 AUDATA1 AUDATA0 RESETM RESETP NMI IRQ0/IRL0 IRQ1/IRL1 IRQ2/IRL2 IRQ3/IRL3 Vcc Vss STATUS0 STATUS1 CKIO2 DACK0 VccQ VssQ DACK1 DREQ0 DREQ1 PTC0/SCK_SIO1 PTC1/SIOMCLK1 PTC2/RXD_SIO1 Vcc Vss PTC3/TXD_SIO1 PTC4/SIOFSYNC1 I/O Description I/O power supply (3.3 V) I/O power supply (0 V) C14 A15 D14 B13 C13 A14 D13 A13 C12 B12 D12 A12 C11 B11 D11 A11 A10 D10 A9 C10 B10 D9 A8 C9 B9 D8 A7 C8 B8 D7 A6 O O O O I I I I I I I AUD data AUD data AUD data AUD data Manual reset request Power-on reset request Non-maskable interrupt request External interrupt request External interrupt request External interrupt request External interrupt request Internal power supply (1.5 V) Internal power supply (0 V) O O O O Processor status Processor status System clock output DMA acknowledge 0 I/O power supply (3.3 V) I/O power supply (0 V) O I I IO/IO IO/I IO/I DMA acknowledge 1 DMA request 0 DMA request 1 I/O port C/SIOF1 communication clock I/O port C/SIOF1 clock input I/O port C/SIOF1 receive data Internal power supply (1.5 V) Internal power supply (0 V) IO/O IO/IO I/O port C/SIOF1 transmit data I/O port C/SIOF1 frame sync Rev. 1.00 Dec. 27, 2005 Page 17 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Pin No. (FP-256G/GV) 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Pin No. (BP-256H/HV) Pin Name PTC5/CE2A PTC6/CE2B VccQ VssQ PTC7/IOIS16 CS5B/CE1A CS6B/CE1B VssQ MD0 MD1 MD2 MD3 Vcc-PLL1 Vss-PLL1 Vcc-PLL2 Vss-PLL2 XTAL EXTAL I/O IO/O IO/O Description I/O port C/area 5 PCMCIA card enable I/O port C/area 6 PCMCIA card enable I/O power supply (3.3 V) I/O power supply (0 V) C7 A5 D6 B7 C6 A4 D5 B6 D4 A3 B4 A2 C3 B5 C5 C4 B3 A1 IO/I O/O O/O I/O port C/PCMCIA 16-bit I/O select Chip select 5B/area 5 PCMCIA card enable Chip select 6B/area 6 PCMCIA card enable I/O power supply (0 V) I I I I Clock mode select Clock mode select Clock mode select Area 0 bus width PLL1 power supply (1.5 V) PLL1 power supply (0 V) PLL2 power supply (1.5 V) PLL2 power supply (0 V) O I Clock oscillator pin External clock/crystal oscillator pin Notes: 1. VccQ-RTC must be supplied even if the realtime clock (RTC) is not used. 2. RTC in this LSI does not operate even if VccQ-RTC is turned on. The crystal oscillator circuit for RTC operates with VccQ-RTC. The control circuit and the RTC counter operate with Vcc (common to the internal circuit). Therefore, all power supplies other than VccQ-RTC should always be turned on even if only RTC operates. 3. Vcc-PLL1/Vcc-PLL2 must be supplied even if the on-chip CPG is not used. 4. VccQ (3.3 V), Vcc (1.5 V), VssQ, and Vss must be connected to the system power supply (for uninterrupted supply). Rev. 1.00 Dec. 27, 2005 Page 18 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function 1.3.2 Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Symbol Vcc I/O Name Power supply Function Power supply for the internal LSI and ports for the system. Connect all Vcc pins to the system power supply. There will be no operation if any pins are open. Ground pin. Connect all Vss pins to the system power supply (0 V). There will be no operation if any pins are open. Power supply for I/O pins. Connect all VccQ pins to the system power supply. There will be no operation if any pins are open. Ground pin. Connect all VssQ pins to the system power supply (0 V). There will be no operation if any pins are open. Power supply for the on-chip PLL1 oscillator. Ground pin for the on-chip PLL1 oscillator. Power supply for the on-chip PLL2 oscillator. Ground pin for the on-chip PLL2 oscillator. For connection to a crystal resonator. This pin can be also used for external clock input. For examples of crystal resonator connection and external clock input, see section 11, On-Chip Oscillation Circuits. Classification Power supply Vss Ground VccQ Power supply VssQ Ground Clock Vcc-PLL1 Vss-PLL1 Vcc-PLL2 Vss-PLL2 EXTAL I I I I I PLL1 power supply PLL1 ground PLL2 power supply PLL2 ground External clock Rev. 1.00 Dec. 27, 2005 Page 19 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Clock Symbol XTAL I/O O Name Crystal Function For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 11, OnChip Oscillation Circuits. Supplies the system clock to external devices. This pin can be also used for external clock input. Supplies the system clock to external devices. These pins set the operating mode. Do not change values on these pins during operation. MD2 to MD0 set the clock mode, MD4 and MD3 set the bus-width mode of area 0, and MD5 sets the endian. CKIO I/O System clock CKIO2 Operating mode MD5 to MD0 control O I System clock Mode set System control RESETP RESETM STATUS1 STATUS0 BREQ I I O Power-on reset Manual reset Status output When low, the system enters the power-on reset state. When low, the system enters the manual reset state. Indicates that this LSI is in software standby mode, reset, or sleep. Low when an external device requests the release of the bus mastership. Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus mastership. I Bus request BACK O Bus request acknowledge Rev. 1.00 Dec. 27, 2005 Page 20 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Interrupts Symbol NMI IRQ5 to IRQ0 I/O I I Name Non-maskable interrupt Interrupt requests 5 to 0 Function Non-maskable interrupt request pin. Fix to high when not in use. Maskable interrupt request pins. Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. IRL3 to IRL0 IRQOUT Address bus Data bus Bus control A25 to A0 D31 to D0 CS0, CS2 to CS4, CS5A, CS6A, CS5B/CE1A, CS6B/CE1B, CE2A, CE2B RD RD/WR BS WE3(BE3)/ ICIOWR I O O I/O O Interrupt request 15-level interrupt request pins. Interrupt request Indicates that the interrupt request output is occurred. Address bus Data bus Chip select 0, 2 to 4, 5A, 5B, 6A, 6B PCMCIA card select Outputs addresses. 32-bit bidirectional bus. Chip-select signals for external memory or devices. PCMCIA card select signal when PCMCIA is used. O O O O Read Read/write Bus start Byte write Indicates reading of data from external devices. Read/write signal Bus-cycle start signal Indicates that bits 31 to 24 of the data in the external memory or device are being written. I/O write strobe signal when PCMCIA is used. Indicates that bits 23 to 16 of the data in the external memory or device are being written. I/O read strobe signal when PCMCIA is used. Indicates that bits 15 to 8 of the data in the external memory or device are being written. Memory write strobe signal when PCMCIA is used. WE2(BE2)/ ICIORD O Byte write WE1(BE1)/ WE O Byte write Rev. 1.00 Dec. 27, 2005 Page 21 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Bus control Symbol WE0(BE0) I/O O Name Byte write Function Indicates that bits 7 to 0 of the data in the external memory or device are being written. Connects RAS pin during access to the SDRAM. Connects CAS pin during access to the SDRAM. Connects CKE pin during access to the SDRAM. Indicates 16-bit I/O for PCMCIA. Selects D31 to D24 during access to the SDRAM. Selects D23 to D16 during access to the SDRAM. Selects D15 to D8 during access to the SDRAM. Selects D7 to D0 during access to the SDRAM. RAS CAS CKE IOIS16 DQMUU DQMUL DQMLU DQMLL REFOUT WAIT O O O I O O O O O I RAS CAS CK enable 16-bit I/O selection DQM DQM DQM DQM Refresh request Outputs the refresh request in output master mode or bus release. Wait Inserts a wait cycle into the bus cycles during access to the external space. Input pin for external requests for DMA transfer. Output pin for request acceptance, in response to external requests for DMA transfer. Output pin for DMA transfer end signal. Direct memory access controller (DMAC) DREQ0, DREQ1 DACK0, DACK1 TEND0, TEND1 I O DMA-transfer request DMA-transfer request accept DMA-transfer end output O Rev. 1.00 Dec. 27, 2005 Page 22 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Symbol I/O I I I O I O O O Name Test clock Test mode select Test data input Function Test-clock input pin. Inputs the test-mode select signal. Serial input pin for instructions and data. User debugging TCK interface (H-UDI) TMS TDI TDO TRST Advanced user debugger (AUD) AUDATA3 to AUDATA0 AUDCK AUDSYNC Test data output Serial output pin for instructions and data. Test reset AUD data AUD clock AUD synchronous signal Break mode acknowledge Initializing signal input pin. Data output pin in AUD trace mode. Synchronous-clock output pin in AUD trace mode. Data start-position acknowledgesignal output pin in AUD trace mode. Indicates that the E10A emulator has entered its break mode. For the connection with the E10A, see the SH7712 E10A Emulator User's Manual (tentative title). E10A interface ASEBRKAK O ASEMD0 Realtime clock (RTC) VccQ-RTC VssQ-RTC EXTAL2 I I I I ASE mode RTC oscillator power supply RTC oscillator ground RTC external clock Sets the ASE mode. Power supply pin for the on-chip RTC Ground pin for the on-chip RTC Clock input pin for the on-chip RTC clock (32.768 MHz). For a connection example, refer to section 15, Realtime Clock (RTC). Clock output pin for the on-chip RTC clock (32.768 MHz). For a connection example, refer to section 15, Realtime Clock (RTC). XTAL2 O RTC crystal Rev. 1.00 Dec. 27, 2005 Page 23 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Ethernet controller (EtherC1/0) Symbol CRS1, CRS0 I/O I Name MAC1/0 carrier detection Function Carrier detection pin. For a connection example, refer to section 18, Ethernet Controller (EtherC). Collision detection pin. For a connection example, refer to section 18, Ethernet Controller (EtherC). 4-bit transmit data pins. For a connection example, refer to section 18, Ethernet Controller (EtherC). 4-bit transmit data pins. For a connection example, refer to section 18, Ethernet Controller (EtherC). COL1, COL0 I MAC1/0 collision detection MAC1 transmit data ETXD13 to ETXD10 O ETXD03 to ETXD00 O MAC0 transmit data TX-EN1, TX-EN0 O MAC1/0 These pins indicate that transmit transmit enable data is ready on ETXD13 to ETXD10 and ETXD03 to ETXD00. For a connection example, refer to section 18, Ethernet Controller (EtherC). MAC1/0 transmit clock Timing reference pins (clock) for TX-EN1/0, TX-ER1/0, ETXD13 to ETXD10 and ETXD03 to ETXD00. For a connection example, refer to section 18, Ethernet Controller (EtherC). These pins notify an error during transmission to the PHY-LSI. For a connection example, refer to section 18, Ethernet Controller (EtherC). TX-CLK1, TX-CLK0 I TX-ER1, TX-ER0 O MAC1/0 transmit error RX-ER1, RX-ER0 I MAC1/0 receive These pins notify an error during error data reception. For a connection example, refer to section 18, Ethernet Controller (EtherC). Rev. 1.00 Dec. 27, 2005 Page 24 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Ethernet controller (EtherC1/0) Symbol RX-CLK1, RX-CLK0 I/O I Name Function MAC1/0 receive Timing reference pins (clock) for clock RX-DV1/0, RX-ER1/0, ERXD13 to ERXD10 and ERXD03 to ERXD00. For a connection example, refer to section 18, Ethernet Controller (EtherC). MAC1/0 receive These pins indicate that valid data valid receive data is on ERXD13 to ERXD10 and ERXD03 to ERXD00. For a connection example, refer to section 18, Ethernet Controller (EtherC). MAC1 receive data 4-bit receive data pins. For a connection example, refer to section 18, Ethernet Controller (EtherC). 4-bit receive data pins. For a connection example, refer to section 18, Ethernet Controller (EtherC). Reference clock pins for information transfer via MDIO. For a connection example, refer to section 18, Ethernet Controller (EtherC). Bidirectional pins for exchanging management information. For a connection example, refer to section 18, Ethernet Controller (EtherC). RX-DV1, RX-DV0 I ERXD13 to ERXD10 I ERXD03 to ERXD00 I MAC0 receive data MDC1, MDC0 O MAC1/0 management data clock MDIO1, MDIO0 I/O MAC1/0 management data I/O WOL1, WOL0 LNKSTA1, LNKSTA0 EXOUT1, EXOUT0 CAMSEN1, CAMSEN0 O I O MAC1/0 Wake- These pins indicate that a Magic On-LAN Packet has been received. MAC1/0 link status Link state input pins from the PHY-LSI MAC1/0 External output pins general-purpose external output MAC1/0 CAM input CAM interface pins input I Rev. 1.00 Dec. 27, 2005 Page 25 of 932 REJ09B0269-0100 Section 1 Overview and Pin Function Classification Ethernet controller (EtherC1/0) Serial communication interface with FIFO (SCIF1/0) Symbol ARBUSY I/O O Name Bus release request Function This pin outputs a bus release request when the amount of data in the receive FIFO reaches the threshold. Modem control pins CTS1, CTS0 RTS1, RTS0 RXD1, RXD0 TXD1, TXD0 SCIF1CK, SCIF0CK I SCIF1/0 transmission clear O I O I/O I/O SCIF1/0 Modem control pins transmit request SCIF1/0 receive Receive data pins data SCIF1/0 transmit data SCIF1/0 serial clock Transmit data pins Clock I/O pins Serial I/O with FIFO (SIOF1/0) SCK_SIO1, SCK_SIO0 SIOMCLK1, SIOMCLK 0 RXD_SIO1, RXD_SIO0 TXD_SIO1, TXD_SIO0 SIOFSYNC1, SIOFSYNC0 SIOF1/0 Transmit/receive communication communication clock I/O pins clock SIOF1/0 clock input Master-clock input pins I I O I/O SIOF1/0 receive Receive data pins data SIOF1/0 transmit data Transmit data pins SIOF1/0 Frame Transmit/receive framesynchronous synchronous-signal I/O pins signal General 8-bit general-purpose I/O port pins purpose I/O port A General 8-bit general-purpose I/O port pins purpose I/O port B General 8-bit general-purpose I/O port pins purpose I/O port C I/O port PTA7 to PTA0 I/O PTB7 to PTB0 I/O PTC7 to PTC0 I/O Rev. 1.00 Dec. 27, 2005 Page 26 of 932 REJ09B0269-0100 Section 2 CPU Section 2 CPU 2.1 2.1.1 Processing States and Processing Modes Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the CPU processing states. Reset State: In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and manual reset. For details on resets, refer to section 4, Exception Handling. In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In manual reset, the register contents of a part of the LSI on-chip modules, such as the bus state controller (BSC), are retained. For details, refer to section 23, List of Registers. The CPU internal statuses and registers are initialized both in power-on reset and manual reset. After initialization, the program branches to address H'A0000000 to pass control to the reset processing program to be executed. Exception Handling State: In the exception handling state, the CPU processing flow is changed temporarily by a general exception or interrupt exception processing. The program counter (PC) and status register (SR) are saved in the save program counter (SPC) and save status register (SSR), respectively. The program branches to an address obtained by adding a vector offset to the vector base register (VBR) and passes control to the exception processing program defined by the user to be executed. For details on reset, refer to section 4, Exception Handling. Program Execution State: The CPU executes programs sequentially. Low-Power Consumption State: The CPU stops operation to reduce power consumption. The low-power consumption state can be entered by executing the SLEEP instruction. For details on the low-power consumption state, refer to section 10, Power-Down Modes. Figure 2.1 shows a status transition diagram. CPUS3D0S_000020020300 Rev. 1.00 Dec. 27, 2005 Page 27 of 932 REJ09B0269-0100 Section 2 CPU 2.1.2 Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is selected. The CPU enters the privileged mode by a transition to reset state or exception handling state. In the privileged mode, any registers and resources in address spaces can be accessed. Clearing the MD bit of the SR to 0 puts the CPU in the user mode. In the user mode, some of the registers, including SR, and some of the address spaces cannot be accessed by the user program and system control instructions cannot be executed. This function effectively protects the system resources from the user program. To change the processing mode from user to privileged mode, a transition to exception handling state is required*. Note: * To call a service routine used in privileged mode from user mode, the LSI supports an unconditional trap instruction (TRAPA). When a transition from user mode to privileged mode occurs, the contents of the SR and PC are saved. A program execution in user mode can be resumed by restoring the contents of the SR and PC. To return from an exception processing program, the LSI supports an RTE instruction. (From any states) Power-on reset Manual reset Reset state Reset processing routine starts Program execution state Multiple exceptions Exception handling routine starts An exception is accepted SLEEP instruction Exception handling state An exception is accepted Low-power consumption state Figure 2.1 Processing State Transitions Rev. 1.00 Dec. 27, 2005 Page 28 of 932 REJ09B0269-0100 Section 2 CPU 2.2 2.2.1 Memory Map Logical Address Space The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of logical address space. User programs and data are accessed from the logical address space. The logical address space is divided into several areas as shown in table 2.1. P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0 areas are handled as address translatable areas. If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified while the address translation unit is enabled, the P0 or U0 address is translated into a physical address based on translation information defined by the user. If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in user mode, a transition to an address error exception occurs. P1 Area: The P1 area is defined as a cacheable but non-address translatable area. Normally, programs executed at high speed in privileged mode, such as exception processing handlers, which are at the core of the operating system (S), are assigned to the P1 area. P2 Area: The P2 area is defined as a non-cacheable but non-address translatable area. A reset processing program to be called from the reset state is described at the start address (H'A0000000) of the P2 area. Normally, programs such as system initialization routines and OS initiation programs are assigned to the P2 area. To access a part of an on-chip I/O, its corresponding program should be assigned to the P2 area. P3 Area: The P3 area is defined as a cacheable and address translatable area. This area is used if an address translation is required for a privileged program. P4 Area: The P4 area is defined as a control area which is non-cacheable and non-address translatable. This area can be accessed only in privileged mode. A part of the LSI's on-chip I/O is assigned to this area. Rev. 1.00 Dec. 27, 2005 Page 29 of 932 REJ09B0269-0100 Section 2 CPU Table 2.1 Logical Address Space Mode Privileged/user mode Description 2-Gbyte physical space, cacheable, address translatable In user mode, only this address space can be accessed. Address Range Name H'00000000 to H'7FFFFFFF P0/U0 H'80000000 to H'9FFFFFFF H'A0000000 to H'BFFFFFFF H'C0000000 to H'DFFFFFFF H'E0000000 to H'FFFFFFFF P1 P2 P3 P4 Privileged mode Privileged mode Privileged mode Privileged mode 0.5-Gbyte physical space, cacheable 0.5-Gbyte physical space, non-cacheable 0.5-Gbyte physical space, cacheable, address translatable 0.5-Gbyte control space, non-cacheable 2.2.2 External Memory Space The LSI uses 29 bits of the 32-bit logical address to access external memory. In this case, 0.5Gbyte of external memory space can be accessed. The external memory space is managed in area units. Different types of memory can be connected to each area, as shown in figure 2.2. For details, please refer to section 12, Bus State Controller (BSC). In addition, area 1 in the external memory space is used as an on-chip I/O space where most of this LSI's on-chip I/Os are mapped. *1 Normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are used for external memory addresses.*2 For example, address H'00000100 in the P0 area, address H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3 area of the logical address space are mapped into address H'00000100 of area 0 in the external memory space. The P4 area in the logical address space is not mapped into the external memory address. If an address in the P4 area is accessed, an external memory cannot be accessed. Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the address from the P2 area which is not cached in the logical address space. 2. If the address translation unit is enabled, arbitrary mapping in page units can be specified. For details, refer to section 5, Memory Management Unit (MMU). Rev. 1.00 Dec. 27, 2005 Page 30 of 932 REJ09B0269-0100 Section 2 CPU External memory space H'0000 0000 P0 area Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 U0 area H'8000 0000 H'8000 0000 P1 area H'A000 0000 P2 area H'C000 0000 Address error P3 area H'E000 0000 P4 area H'FFFF FFFF H'FFFF FFFF Privileged mode User mode Figure 2.2 Logical Address to External Memory Space Mapping Rev. 1.00 Dec. 27, 2005 Page 31 of 932 REJ09B0269-0100 Section 2 CPU 2.3 Register Descriptions This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. General Registers: This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB) bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers. System Registers: This LSI incorporates the multiply and accumulate registers (MACH/MACL) and procedure register (PR) as system registers. These registers can be accessed regardless of the processing mode. Program Counter: The program counter stores the value obtained by adding 4 to the current instruction address. Control Registers: This LSI incorporates the status register (SR), global base register (GBR), save status register (SSR), save program counter (SPC), and vector base register as control register. Only the GBR can be accessed in user mode. Control registers other than the GBR can be accessed only in privileged mode. Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each process mode. Rev. 1.00 Dec. 27, 2005 Page 32 of 932 REJ09B0269-0100 Section 2 CPU Table 2.2 Register Initial Values Registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Initial Values* Undefined Register Type General registers System registers Program counter Control registers MACH, MACL, PR PC SR Undefined H'A0000000 MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 bits = H'F (1111), reserved bits = all 0, other bits = undefined Undefined H'00000000 GBR, SSR, SPC VBR Note: * Initialized by a power-on or manual reset. Rev. 1.00 Dec. 27, 2005 Page 33 of 932 REJ09B0269-0100 Section 2 CPU 31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 0 31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 0 GBR MACH MACL PR PC (a) User mode register configuration (b) Privileged mode register configuration (RB = 1) (c) Privileged mode register configuration (RB = 0) Notes: *1 The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode. *2 Bank register *3 Bank register Accessed as a general register when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. *4 Bank register Accessed as a general register when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.3 Register Configuration in Each Processing Mode Rev. 1.00 Dec. 27, 2005 Page 34 of 932 REJ09B0269-0100 Section 2 CPU 2.3.1 General Registers There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB) bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to R7_BANK by the control register load instruction (LDC) and control register store instruction (STC). In user mode, bank 0 is selected regardless of he RB bit value. Sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 cannot be accessed. In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1 to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15 are accessed as general registers R0 to R15. A bank is switched automatically when an exception handling state is entered, registers R0 to R7 need not be saved by the exception handling routine. The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK by the LDC and STC instructions. In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as R0_BANK to R7_BANK by the LDC and STC instructions. The general registers R0 to R15 are used as equivalent registers for almost all instructions. In some instructions, the R0 register is automatically used or only the R0 register can be used as source or destination registers. Rev. 1.00 Dec. 27, 2005 Page 35 of 932 REJ09B0269-0100 Section 2 CPU 31 R0*1,*2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 General Registers: Undefined after reset Notes: *1 R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source or destination register. *2 R0-R7 are banked registers. In user mode, BANK0 is used. In privileged mode, either R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1 is selected by the RB bit of the SR register. Figure 2.4 General Registers 2.3.2 System Registers The system registers: multiply and accumulate registers (MACH/MACL) and procedure register (PR) as system registers can be accessed by the LDS and STS instructions. Multiply and Accumulate Registers (MACH/MACL): The multiply and accumulate registers (MACH/MACL) store the results of multiplication and accumulation instructions or multiplication instructions. The MACH/MACL registers also store addition values for the multiplication and accumulations. After reset, these registers are undefined. The MACH and MACL registers store upper 32 bits and lower 32 bits, respectively. Procedure Register (PR): The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF, or JSR instruction. The return address stored in the PR register is restored to the program counter (PC) by the RTS (return from the subroutine) instruction. After reset, this register is undefined. Rev. 1.00 Dec. 27, 2005 Page 36 of 932 REJ09B0269-0100 Section 2 CPU 2.3.3 Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. There is no instruction to read the PC directly. Before an exception handling state is entered, the PC is saved in the save program counter (SPC). Before a subroutine call is executed, the PC is saved in the procedure register (PR). In addition, the PC can be used for PC relative addressing mode. Figure 2.5 shows the system register and program counter configurations. Multiply and accumulate high and low registers (MACH/MACL) 31 MACH MACL Procedure register (PR) 31 0 0 PR Program counter (PC) 31 0 PC Figure 2.5 System Registers and Program Counter Rev. 1.00 Dec. 27, 2005 Page 37 of 932 REJ09B0269-0100 Section 2 CPU 2.3.4 Control Registers The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC instruction in privileged mode. The GBR register can be accessed in the user mode. The control registers are described below. Status Register (SR): The status register (SR) indicates the system status as shown below. The SR register can be accessed only in privileged mode. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 MD 1 R/W Processing Mode Indicates the CPU processing mode. 0: User mode 1: Privileged mode The MD bit is set to 1 in reset or exception handling state. 29 RB 1 R/W Register Bank The general registers R0 to R7 are banked registers. The RB bit selects a bank used in the privileged mode. 0: Selects bank 0 registers. In this case, R0_BANK0 to R7_BANK0 and R8 to R15 are used as general registers. R0_BANK1 to R7_BANK1 can be accessed by the LDC or STR instruction. 1: Selects bank 1 registers. In this case, R0_BANK1 to R7_BANK1 and R8 to R15 are used as general registers. R0_BANK0 to R7_BANK0 can be accessed by the LDC or STR instruction. The RB bit is set to 1 in reset or exception handling state. Rev. 1.00 Dec. 27, 2005 Page 38 of 932 REJ09B0269-0100 Section 2 CPU Bit 28 Bit Name BL Initial Value 1 R/W R/W Description Block Specifies whether an exception, interrupt, or user break is enabled or not. 0: Enables an exception, interrupt, or user break. 1: Disables an exception, interrupt, or user break. The BL bit is set to 1 in reset or exception handling state. 27 to 10 9 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. M Q R/W R/W M Bit Q Bit These bits are used by the DIV0S, DIV0U, and DIV1 instructions. These bits can be changed even in user mode by using the DIV0S, DIV0U, and DIV1 instructions. These bits are undefined at reset. These bits do not change in an exception handling state. 7 to 4 I3 to I0 All 1 R/W Interrupt Mask Indicates the interrupt mask level. These bits do not change even if an interrupt occurs. At reset, these bits are initialized to B'1111. These bits are not affected in an exception handling state. 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 S R/W Saturation Mode Specifies the saturation mode for multiply instructions or multiply and accumulate instructions. This bit can be specified by the SETS and CLRS instructions in user mode. At reset, this bit is undefined. This bit is not affected in an exception handling state. Rev. 1.00 Dec. 27, 2005 Page 39 of 932 REJ09B0269-0100 Section 2 CPU Bit 0 Bit Name T Initial Value R/W R/W Description T Bit Indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow. This bit can be specified by the SETT and CLRT instructions in user mode. At reset, this bit is undefined. This bit is not affected in an exception handling state. Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits can be read or written in privileged mode. Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged mode. Before entering the exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial value is undefined. Save Program Counter (SPC): The save program counter (SPC) can be accessed only in privileged mode. Before entering the exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined. Global Base Register (GBR): The global base register (GBR) is referenced as a base register in GBR indirect addressing mode. At reset, the GBR initial value is undefined. Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged mode. If a transition from reset state to exception handling state occurs, this register is referenced as a base address. For details, refer to section 4, Exception Handling. At reset, the VBR is initialized as H'00000000. Figure 2.6 shows the control register configuration. Rev. 1.00 Dec. 27, 2005 Page 40 of 932 REJ09B0269-0100 Section 2 CPU Save status register (SSR) 31 SSR Save program counter (SPC) 31 SPC 0 0 Global base register (GBR) 31 GBR Vector base register (VBR) 31 VBR 0 0 Status register (SR) 31 0 MD RB BL 0 0 0 M Q I3 I2 I1 I0 0 0 S T Figure 2.6 Control Register Configuration Rev. 1.00 Dec. 27, 2005 Page 41 of 932 REJ09B0269-0100 Section 2 CPU 2.4 2.4.1 Data Formats Register Data Format Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 2.4.2 Memory Data Formats Memory data formats are classified into byte, word, and longword. Memory can be accessed in byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. An address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data accessed cannot be guaranteed. When a word or longword operand is accessed, the byte positions on the memory corresponding to the word or longword data on the register is determined to the specified endian mode (big endian or little endian). Figure 2.7 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in the register corresponds to the lowest address in the memory, and the LSB the in the register corresponds to the highest address. For example, if the contents of the general register R0 is stored at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the R1 and the LSB byte of the R1 register is stored at the address indicated by the (R1 +3). The on-chip device registers assigned to memory are accessed in big endian mode. Note that the available access size (byte, word, or long word) differs in each register. Note: The CPU instruction codes of this LSI must be stored in word units. In big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary of the memory. Rev. 1.00 Dec. 27, 2005 Page 42 of 932 REJ09B0269-0100 Section 2 CPU 31 Byte position in R0 23 15 7 [7:0] 0 [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] Byte position in memory [7:0] @(R1+0) @(R1+1) @(R1+2) @(R1+3) (a) Byte access Example: MOV.B R0, @R1 (R1 = Address 4n) [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] @(R1+0) @(R1+1) @(R1+2) @(R1+3) (b) Word access Example: MOV.W R0, @R1 (R1 = Address 4n) @(R1+0) @(R1+1) @(R1+2) @(R1+3) (c) Longword access Example: MOV.L R0, @R1 (R1 = Address 4n) Figure 2.7 Data Format on Memory (Big Endian Mode) The little endian mode can also be specified as data format. Either big-endian or little-endian mode can be selected according to the external pin (MD5) at a power-on reset. When MD5 is low at reset, the processor operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian mode. The endian mode cannot be modified dynamically. In little endian mode, the MSB byte in the register corresponds to the highest address in the memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For example, if the contents of the general register R0 is stored at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3) and the LSB byte of the R1 register is stored at the address indicated by the R1. If the little endian mode is selected, the on-chip memory are accessed in little endian mode. However, the on-chip device registers assigned to memory are accessed in big endian mode. Note that the available access size (byte, word, or long word) differs in each register. Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode, the instruction code must be stored from lower byte to upper byte in this order from the word boundary of the memory. 31 Byte position in R0 23 15 7 [7:0] 0 [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] Byte position in memory [7:0] @(R1+3) @(R1+2) @(R1+1) @(R1+0) (a) Byte access Example: MOV.B R0, @R1 (R1 = Address 4n) [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] @(R1+3) @(R1+2) @(R1+1) @(R1+0) (b) Word access Example: MOV.W R0, @R1 (R1 = Address 4n) @(R1+3) @(R1+2) @(R1+1) @(R1+0) (c) Longword access Example: MOV.L R0, @R1 (R1 = Address 4n) Figure 2.8 Data Format on Memory (Little Endian Mode) Rev. 1.00 Dec. 27, 2005 Page 43 of 932 REJ09B0269-0100 Section 2 CPU Note: When the external memory is accessed through the E-DMAC module, big endian is supported, but little endian is not supported. Therefore, if the external memory is accessed through the E-DMAC module in little endian mode, data format should be converted from big endian mode to little endian mode through software. 2.5 2.5.1 Features of CPU Core Instructions Instruction Execution Method Instruction Length: All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles in longword (32 bits). Memory can be accessed in byte, word, or longword. In this case, Memory byte or word data is sign-extended and operated on as longword data. Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly on memory. Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. This LSI supports two types of conditional branch instructions: delayed branch instruction or normal branch instruction. Example: BRA ADD TARGET R1, R0 ; ADD is executed before branching to the TARGET T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Example: ADD CMP/EQ BT #1, R0 ; The T bit cannot be modified by the ADD instruction #0, R0 ; The T bit is set to 1 if R0 is 0. Target ; Branch to TARGET if the T bit is set to 1 (R0=0). Rev. 1.00 Dec. 27, 2005 Page 44 of 932 REJ09B0269-0100 Section 2 CPU Literal Constant: Byte literal constant is placed inside the instruction code as immediate data. Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in memory. The table in memory is referenced with a MOV instruction using PC-relative addressing mode with displacement. Example: MOV.W @(disp, PC) Absolute Addresses: When data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand as well as word or longword literal constant. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using register indirect addressing mode. 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. Using the method whereby word or longword immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. 2.5.2 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.3 Addressing Mode Register direct Register indirect Register indirect with post-increment Addressing Modes and Effective Addresses for CPU Instructions Instruction Format Rn @Rn Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula -- Rn @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 + 1/2/4 Rn Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Rev. 1.00 Dec. 27, 2005 Page 45 of 932 REJ09B0269-0100 Section 2 CPU Addressing Mode Register indirect with pre-decrement Instruction Format Effective Address Calculation Method @-Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 Calculation Formula Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) 1/2/4 Rn - 1/2/4 Register indirect with displacement @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 + Rn + disp x 1/2/4 1/2/4 Indexed @(R0, Rn) register indirect Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 disp (Zero-extended) + GBR + disp x 1/2/4 x 1/2/4 Rev. 1.00 Dec. 27, 2005 Page 46 of 932 REJ09B0269-0100 Section 2 CPU Addressing Mode Indexed GBR indirect Instruction Format Effective Address Calculation Method @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR Calculation Formula GBR + R0 + R0 GBR + R0 PC-relative with @(disp:8, displacement PC) Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC & * Word: PC + disp x 2 Longword: PC&H'FFFFFFFC + disp x 4 H'FFFFFFFC + disp (zero-extended) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 x 2/4 *: With longword operand PC-relative disp:8 Effective address is PC with 8-bit displacement disp added after being signextended and multiplied by 2. PC PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 disp:12 Effective address is PC with 12-bit displacement disp added after being signextended and multiplied by 2 PC PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 Rev. 1.00 Dec. 27, 2005 Page 47 of 932 REJ09B0269-0100 Section 2 CPU Addressing Mode PC-relative Instruction Format Effective Address Calculation Method Rn Effective address is sum of PC and Rn. PC Calculation Formula PC + Rn + Rn PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. -- -- -- Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the operand size to clarify the LSI operation. For details on assembler description, refer to the description rules in each assembler. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC relative with displacement disp:8, disp ; PC relative 2.5.3 CPU Instruction Formats Table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Rev. 1.00 Dec. 27, 2005 Page 48 of 932 REJ09B0269-0100 Section 2 CPU Table 2.4 CPU Instruction Formats Source Operand -- Destination Operand -- Sample Instruction NOP Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx -- nnnn: register direct MOVT Rn Control register or nnnn: register system register direct STS MACH,Rn SR,@-Rn Control register or nnnn: preSTC.L system register decrement register indirect m type 15 0 xxxx mmmm xxxx xxxx mmmm: register direct Control register or LDC system register Rm,SR mmmm: postControl register or LDC.L increment register system register indirect mmmm: register indirect PC-relative using Rm nm type 15 0 xxxx nnnn mmmm xxxx @Rm+,SR -- -- nnnn: register direct nnnn: register indirect JMP BRAF ADD @Rm Rm Rm,Rn mmmm: register direct mmmm: register indirect MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: * postincrement register indirect (multiplyand-accumulate operation) Rev. 1.00 Dec. 27, 2005 Page 49 of 932 REJ09B0269-0100 Section 2 CPU Instruction Format nm type Source Operand Destination Operand Sample Instruction MOV.L @Rm+,Rn mmmm: postnnnn: register increment register direct indirect mmmm: register direct mmmm: register direct nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: indexed register indirect MOV.L Rm,@(R0,Rn) md type 15 0 xxxx xxxx mmmm dddd mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 nd4 type 15 0 xxxx xxxx nnnn dddd R0 (register direct) nnnndddd: register indirect with displacement mmmm: register direct mmmmdddd: register indirect with displacement nnnndddd: register indirect with displacement nnnn: register direct MOV.B R0,@(disp,Rn) nmd type 15 0 xxxx nnnn mmmm dddd MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn d type 15 0 xxxx xxxx dddd dddd dddddddd: GBR indirect with displacement R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC-relative with displacement dddddddd: PC-relative d12 type 15 0 xxxx dddd dddd dddd MOV.L R0,@(disp,GBR) R0 (register direct) MOVA @(disp,PC),R0 -- -- BF BRA label label (label=disp+PC) dddddddddddd: PC-relative dddddddd: PCrelative with displacement nd8 type 15 0 xxxx nnnn dddd dddd nnnn: register direct MOV.L @(disp,PC),Rn Rev. 1.00 Dec. 27, 2005 Page 50 of 932 REJ09B0269-0100 Section 2 CPU Instruction Format i type 15 xxxx xxxx 0 iiii iiii Source Operand iiiiiiii: immediate Destination Operand Indexed GBR indirect Sample Instruction AND.B #imm,@(R0,GBR) #imm,R0 iiiiiiii: immediate iiiiiiii: immediate ni type 15 xxxx nnnn i i i i 0 iiii R0 (register direct) AND -- nnnn: register direct TRAPA #imm ADD #imm,Rn iiiiiiii: immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 1.00 Dec. 27, 2005 Page 51 of 932 REJ09B0269-0100 Section 2 CPU 2.6 2.6.1 Instruction Set CPU Instruction Set Based on Functions The CPU instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. Tables 2.6 to 2.11 show the instruction notation, machine code, execution time, and function. Table 2.5 Type Data transfer instructions CPU Instruction Types Kinds of Instruction 5 Op Code MOV Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension 33 Number of Instructions 39 Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU Rev. 1.00 Dec. 27, 2005 Page 52 of 932 REJ09B0269-0100 Section 2 CPU Type Arithmetic operation instructions Kinds of Instruction 21 Op Code MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Function Multiply-and-accumulate, doubleprecision multiply-and-accumulate Double-precision multiplication (32 x 32 bits) Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit setting Logical AND and T bit setting Exclusive logical OR 1-bit left shift 1-bit right shift 1-bit left shift with T bit 1-bit right shift with T bit Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Arithmetic dynamic shift Logical dynamic shift Number of Instructions 33 Logic operation instructions 6 AND NOT OR TAS TST XOR 14 Shift instructions 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD 16 Rev. 1.00 Dec. 27, 2005 Page 53 of 932 REJ09B0269-0100 Section 2 CPU Type Branch instructions Kinds of Instruction 9 Op Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear S bit clear Load into control register Load into system register PTEH/PTEL load into TLB No operation Data prefetch to cache Return from exception handling S bit setting T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling Number of Instructions 11 System control instructions 15 CLRT CLRMAC CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA 75 Total: 68 188 The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Rev. 1.00 Dec. 27, 2005 Page 54 of 932 REJ09B0269-0100 Section 2 CPU Execution States Value when no wait states are inserted*1 Instruction Indicated by mnemonic. Instruction Code Indicated in MSB LSB order. Operation Indicates summary of operation. Privilege Indicates a privileged instruction. T Bit Value of T bit after instruction is executed Explanatio n of Symbols --: No change Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Rn: Source register Destination register Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement*2 Explanation of Symbols , : (xx): Transfer direction Memory operand M/Q/T: Flag bits in SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit imm: Immediate data disp: Displacement < Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is also used by the following instruction 2. Scaled (x1, x2, or x4) according to the instruction operand size, etc. Rev. 1.00 Dec. 27, 2005 Page 55 of 932 REJ09B0269-0100 Section 2 CPU Table 2.6 Instruction MOV Data Transfer Instructions Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Operation Imm Sign extension Rn Privileged Mode Cycles T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #imm,Rn MOV.W @(disp,PC),Rn MOV.L MOV MOV.B @(disp,PC),Rn Rm,Rn Rm,@Rn (disp x 2+PC)Sign extension Rn (disp x 4+PC)Rn RmRn Rm(Rn) Rm(Rn) Rm(Rn) (Rm)Sign extensionRn (Rm)Sign extensionRn (Rm)Rn Rn-1Rn, Rm(Rn) Rn-2Rn, Rm(Rn) Rn-4Rn, Rm(Rn) (Rm)Sign extensionRn, Rm+1Rm (Rm)Sign extensionRn, Rm+2Rm (Rm)Rn, Rm+4Rm R0(disp+Rn) R0(disp x 2+Rn) Rm(disp x 4+Rn) (disp+Rm)Sign extensionR0 (disp x 2+Rm)Sign extensionR0 (disp x 4+Rm)Rn Rm(R0+Rn) Rm(R0+Rn) Rm(R0+Rn) 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 MOV.W Rm,@Rn MOV.L MOV.B Rm,@Rn @Rm,Rn MOV.W @Rm,Rn MOV.L MOV.B @Rm,Rn Rm,@-Rn MOV.W Rm,@-Rn MOV.L MOV.B Rm,@-Rn @Rm+,Rn MOV.W @Rm+,Rn MOV.L MOV.B @Rm+,Rn R0,@(disp,Rn) 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd MOV.W R0,@(disp,Rn) MOV.L MOV.B Rm,@(disp,Rn) 0001nnnnmmmmdddd @(disp,Rm),R0 10000100mmmmdddd MOV.W @(disp,Rm),R0 10000101mmmmdddd MOV.L MOV.B @(disp,Rm),Rn 0101nnnnmmmmdddd Rm,@(R0,Rn) 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) Rev. 1.00 Dec. 27, 2005 Page 56 of 932 REJ09B0269-0100 Section 2 CPU Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT SWAP.B SWAP.W XTRCT @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code Operation extensionRn Privileged Mode Cycles T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000nnnnmmmm1100 (R0+Rm)Sign 0000nnnnmmmm1101 (R0+Rm)Sign extensionRn 0000nnnnmmmm1110 (R0+Rm)Rn R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn Rm,Rn Rm,Rn Rm,Rn 11000111dddddddd 0000nnnn00101001 R0(disp+GBR) R0(disp x 2+GBR) R0(disp x 4+GBR) (disp+GBR)Sign extensionR0 (disp x 2+GBR)Sign extensionR0 (disp x 4+GBR)R0 disp x 4+PCR0 TRn bytesRn 0110nnnnmmmm1000 RmSwap lowest two 0110nnnnmmmm1001 RmSwap two consecutive wordsRn 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn Rn Rev. 1.00 Dec. 27, 2005 Page 57 of 932 REJ09B0269-0100 Section 2 CPU Table 2.7 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Arithmetic Operation Instructions Instruction Code Rm,Rn 0011nnnnmmmm1100 Operation Rn+RmRn Rn+immRn Rn+Rm+TRn, CarryT Rn+RmRn, OverflowT If R0 = imm, 1 T If Rn = Rm, 1 T Privileged Mode Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit - - Carry Overflow Compariso n result #imm,Rn 0111nnnniiiiiiii Rm,Rn Rm,Rn 0011nnnnmmmm1110 0011nnnnmmmm1111 #imm,R0 10001000iiiiiiii Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn 0011nnnnmmmm0000 Compariso n result 0011nnnnmmmm0010 If Rn Rm with unsigned data, 1T If Rn Rm with signed data, 1T Compariso n result Compariso n result Compariso n result Compariso n result 0011nnnnmmmm0011 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1T If Rn > Rm with signed data, 1T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits 0011nnnnmmmm0111 0100nnnn00010101 Compariso n result 0100nnnn00010001 Compariso n result CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn 0010nnnnmmmm1100 Compariso n result Calculation result 0011nnnnmmmm0100 0010nnnnmmmm0111 Calculation result 0000000000011001 0011nnnnmmmm1101 0 2 (to 5)* - DMULU.L Rm,Rn 0011nnnnmmmm0101 2 (to 5)* - Rev. 1.00 Dec. 27, 2005 Page 58 of 932 REJ09B0269-0100 Section 2 CPU Instruction DT EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn @Rm+, @Rn+ Instruction Code 0100nnnn00010000 Operation Privileged Mode Cycles 1 1 1 1 1 T Bit Comparison result Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is sign-extended Rn A word in Rm is sign-extended Rn A byte in Rm is zero-extended Rn A word in Rm is zero-extended Rn Signed operation of (Rn) x (Rm) + MAC MAC,Rn + 4 Rn, Rm + 4 Rm, 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC,Rn + 2 Rn, Rm + 2 Rm, 16 x 16 + 64 64 bits Rn x Rm MACL, 32 x 32 32 bits Signed operation of Rn x Rm MACL, 16 x 16 32 bits Unsigned operation of Rn x Rm MACL, 16 x 16 32 bits 0-RmRn 0-Rm-TRn, BorrowT Rn-RmRn Rn-Rm-TRn, Borrow T Rn-RmRn, UnderflowT 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 2 (to 5)* MAC.W @Rm+, @Rn+ 0100nnnnmmmm1111 2 (to 5)* MUL.L MULS.W Rm,Rn Rm,Rn 0000nnnnmmmm0111 2 (to 5)* 1( to 3)* 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 1(to 3)* NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn * 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 1 1 1 1 1 Borrow Borrow Underflow Note: The number of execution cycles indicated within the parentheses ( ) are required when the operation result is read from the MACH/MACL register immediately after the instruction. Rev. 1.00 Dec. 27, 2005 Page 59 of 932 REJ09B0269-0100 Section 2 CPU Table 2.8 Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Logic Operation Instructions Instruction Code Operation R0 & imm R0 (R0+GBR) & imm (R0+GBR) Privileged Mode Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3 T Bit Test result Rm,Rn #imm,R0 #imm,@(R0, GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0, GBR) @Rn Rm,Rn #imm,R0 #imm,@(R0, GBR) Rm,Rn #imm,R0 #imm,@(R0, GBR) 0010nnnnmmmm1001 Rn & Rm Rn 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 Rm Rn 0010nnnnmmmm1011 RnRm Rn 11001011iiiiiiii 11001111iiiiiiii R0imm R0 (R0+GBR)imm (R0+GBR) 0100nnnn00011011 If (Rn) is 0, 1 T; 1 MSB of (Rn) T 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 Test result 11001000iiiiiiii R0 & imm; if the result is 0, 1 T Test result 11001100iiiiiiii (R0 + GBR) & imm; if the result is 0, 1 T Test result 0010nnnnmmmm1010 Rn ^ Rm Rn 11001010iiiiiiii 11001110iiiiiiii R0 ^ imm R0 (R0+GBR) ^ imm (R0+GBR) Rev. 1.00 Dec. 27, 2005 Page 60 of 932 REJ09B0269-0100 Section 2 CPU Table 2.9 Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Shift Instructions Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Operation TRnMSB LSBRnT TRnT TRnT Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [MSB Rn] TRn0 MSBRnT Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [0 Rn] TRn0 0RnT Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn Privileged Mode Cycles 1 1 1 1 1 T Bit MSB LSB MSB LSB Rm, Rn SHAL SHAR SHLD SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 Rn Rn Rm, Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 1 1 1 1 1 1 1 1 1 1 1 MSB LSB MSB LSB 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 SHLR16 Rn Rev. 1.00 Dec. 27, 2005 Page 61 of 932 REJ09B0269-0100 Section 2 CPU Table 2.10 Branch Instructions Instruction BF BF/S label label Instruction Code 10001011dddddddd Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Privileged Mode Cycles 3/1* 2/1* T Bit 10001111dddddddd BT BT/S label label 10001001dddddddd 3/1* 2/1* 10001101dddddddd BRA BRAF BSR BSRF JMP JSR RTS label Rm label Rm @Rm @Rm 1010dddddddddddd 2 2 2 2 2 2 2 0000mmmm00100011 1011dddddddddddd Delayed branch,Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Note: * One state when the branch is not executed. Rev. 1.00 Dec. 27, 2005 Page 62 of 932 REJ09B0269-0100 Section 2 CPU Table 2.11 System Control Instructions Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 Operation 0MACH,MACL 0S 0T RmSR RmGBR RmVBR RmSSR RmSPC Privileged Mode Cycles 1 1 1 6 4 4 4 4 4 4 4 4 4 4 4 4 8 4 4 4 4 4 4 4 4 T Bit 0 LSB LSB Rm,R0_BANK 0100mmmm10001110 RmR0_BANK Rm,R1_BANK 0100mmmm10011110 RmR1_BANK Rm,R2_BANK 0100mmmm10101110 RmR2_BANK Rm,R3_BANK 0100mmmm10111110 RmR3_BANK Rm,R4_BANK 0100mmmm11001110 RmR4_BANK Rm,R5_BANK 0100mmmm11011110 RmR5_BANK Rm,R6_BANK 0100mmmm11101110 RmR6_BANK Rm,R7_BANK 0100mmmm11111110 RmR7_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SSR @Rm+,SPC @Rm+, R0_BANK @Rm+, R1_BANK @Rm+, R2_BANK @Rm+, R3_BANK 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 (Rm)SR, Rm+4Rm (Rm)GBR, Rm+4Rm (Rm)VBR, Rm+4Rm (Rm)SSR,Rm+4Rm (Rm)SPC,Rm+4Rm (Rm)R0_BANK,Rm+4Rm (Rm)R1_BANK,Rm+4Rm (Rm)R2_BANK,Rm+4Rm 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 (Rm)R3_BANK, Rm+4Rm Rev. 1.00 Dec. 27, 2005 Page 63 of 932 REJ09B0269-0100 Section 2 CPU Instruction LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB NOP PREF RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR, Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn R4_BANK,Rn @Rm @Rm+, R4_BANK @Rm+, R5_BANK @Rm+, R6_BANK @Rm+, R7_BANK Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Instruction Code 0100mmmm11000111 Operation (Rm)R4_BANK, Rm+4Rm (Rm)R5_BANK, Rm+4Rm (Rm)R6_BANK, Rm+4Rm (Rm)R7_BANK, Rm+4Rm RmMACH RmMACL RmPR (Rm)MACH, Rm+4Rm (Rm)MACL, Rm+4Rm (Rm)PR, Rm+4Rm PTEH/PTELTLB No operation (Rm) cache Delayed branch, SSR SR, SPC PC 1S 1T Sleep SRRn GBRRn VBRRn SSRRn SPCRn R0_BANKRn R1_BANKRn R2_BANKRn R3_BANKRn R4_BANKRn Privileged Mode Cycles T Bit - - 4 4 4 4 1 1 1 1 1 1 1 1 1 5 1 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 0100mmmm11010111 0100mmmm11100111 0100mmmm11110111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 0000nnnn11000010 Rev. 1.00 Dec. 27, 2005 Page 64 of 932 REJ09B0269-0100 Section 2 CPU Instruction STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn Instruction Code 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 Operation R5_BANKRn R6_BANKRn R7_BANKRn Rn-4Rn, SR(Rn) Rn-4Rn, GBR(Rn) Rn-4Rn, VBR(Rn) Rn-4Rn, SSR(Rn) Rn-4Rn, SPC(Rn) Rn-4Rn, R0_BANK(Rn) Rn-4Rn, R1_BANK(Rn) Rn-4Rn, R2_BANK(Rn) Rn-4Rn, R3_BANK(Rn) Rn-4Rn, R4_BANK(Rn) Rn-4Rn, R5_BANK(Rn) Rn-4Rn, R6_BANK(Rn) Rn-4Rn, R7_BANK(Rn) MACHRn MACLRn PRRn Rn-4Rn, MACH(Rn) Rn-4Rn, MACL(Rn) Rn-4Rn, PR(Rn) Unconditional trap exception 2 occurs* Privileged Mode Cycles - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 T Bit R0_BANK,@- 0100nnnn10000011 Rn R1_BANK,@- 0100nnnn10010011 Rn R2_BANK,@- 0100nnnn10100011 Rn R3_BANK,@- 0100nnnn10110011 Rn R4_BANK,@- 0100nnnn11000011 Rn R5_BANK,@- 0100nnnn11010011 Rn R6_BANK,@- 0100nnnn11100011 Rn R7_BANK,@- 0100nnnn11110011 Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Notes: 1. Number of states before the chip enters the sleep state. 2. For details, refer to section 4, Exception Handling. Rev. 1.00 Dec. 27, 2005 Page 65 of 932 REJ09B0269-0100 Section 2 CPU 2.6.2 Operation Code Map Table 2.12 shows the operation code map. Table 2.12 Operation Code Map Instruction Code MSB 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rm 0000 Rm 0000 Rn Fx Fx LSB 0000 0001 STC SR, Rn STC SPC, Rn STC R0_BANK, Rn STC R4_BANK, Rn BSRF Rm PREF @Rm MOV.W Rm, @(R0, Rn) SETT SETS DIV0U MOV.L Rm, @(R0, Rn) CLRMAC MUL.L Rm, Rn LDTLB STC R1_BANK, Rn STC R5_BANK, Rn STC R2_BANK, Rn STC R3_BANK, Rn STC R6_BANK, Rn STC R7_BANK, Rn BRAF Rm STC GBR, Rn STC VBR, Rn STC SSR, Rn Fx: 0000 MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 00MD 0010 01MD 0010 10MD 0010 11MD 0010 00MD 0011 10MD 0011 Rm 01MD MOV.B Rm, @(R0, Rn) CLRT CLRS NOP 0000 0000 00MD 1000 0000 0000 01MD 1000 0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0001 Rn 0010 Rn Fx Fx Fx Fx Rm Rm Rm 1001 1010 1011 1000 1001 1010 1011 RTS SLEEP RTE MOVT Rn STS MACH, Rn STS MACL, Rn STS PR, Rn 11MD MOV. B @(R0, Rm), Rn disp MOV.L MOV.W @(R0, Rm), Rn MOV.L @(R0, Rm), Rn MAC.L @Rm+,@Rn+ Rm, @(disp:4, Rn) Rm, MOV.W Rm, @Rn MOV.L Rm, @Rn 00MD MOV.B @Rn Rev. 1.00 Dec. 27, 2005 Page 66 of 932 REJ09B0269-0100 Section 2 CPU Instruction Code MSB 0010 0010 0010 0011 Rn 0011 Rn 0011 Rn 0011 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn Rm Rm Rm Rm Fx Fx Fx 00MD 01MD 10MD 00MD 01MD 10MD 11MD 0000 0001 0010 0011 0011 0011 LSB Fx: 0000 MD: 00 Rn Rn Rn CMP/EQ Rm, Rn DIV1 Rm, Rn SUB Rm, Rn ADD Rm, Rn SHLL Rn SHLR Rn STS.L MACH, @- Rn STC.L SR, @-Rn STC.L SPC, @-Rn STC.L R0_BANK, @-Rn Fx: 0001 MD: 01 Rm Rm Rm Fx: 0010 MD: 10 01MD 10MD 11MD CMP/HS Rm, Rn Fx: 0011 to 1111 MD: 11 MOV.B Rn TST Rm, @- Rm, Rn CMP/STRRm, Rn CMP/GE Rm, Rn CMP/GT Rm, Rn SUBV ADDV Rm, Rn Rm, Rn DMULU.L Rm,Rn CMP/HI Rm, Rn SUBC Rm, Rn DMULS.L Rm,Rn DT Rn ADDC Rm, Rn SHAL Rn SHAR Rn STS.L PR, @-Rn CMP/PZ Rn STS.L MACL, @- Rn STC.L GBR, @-Rn STC.L VBR, @- Rn STC.L Rn SSR, @- STC.L R1_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R6_BANK, @-Rn ROTCL Rn STC.L R3_BANK, @-Rn STC.L R7_BANK, @-Rn 0100 Rn 11MD 0011 STC.L R4_BANK, @-Rn 0100 Rn 0100 Rn Fx Fx 0100 0101 0110 ROTL Rn ROTR Rn LDS.L @Rm+, MACH CMP/PL Rn LDS.L @Rm+, MACL ROTCR Rn LDS.L @Rm+, PR 0100 Rm Fx 0100 Rm 00MD 0100 Rm 01MD 0100 Rm 10MD 0111 0111 0111 LDC.L @Rm+, SR LDC.L @Rm+, GBR LDC.L @Rm+, SPC LDC.L LDC.L LDC.L @Rm+, VBR LDC.L @Rm+, SSR LDC.L LDC.L @Rm+, R0_BANK @Rm+, R1_BANK @Rm+, R2_BANK @Rm+, R3_BANK 0100 Rm 11MD 0111 LDC.L LDC.L LDC.L LDC.L @Rm+, R4_BANK @Rm+, R5_BANK @Rm+, R6_BANK @Rm+, R7_BANK 0100 Rn Fx 1000 SHLL2 Rn SHLL8 Rn SHLL16 Rn Rev. 1.00 Dec. 27, 2005 Page 67 of 932 REJ09B0269-0100 Section 2 CPU Instruction Code MSB 0100 Rn 0100 Rm Fx Fx LSB 1001 1010 1011 1100 1101 1110 1110 1110 1110 1111 disp 00MD 01MD 10MD 11MD Fx: 0000 MD: 00 SHLR2 Rn LDS JSR Rm, MACH @Rm Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 0100 Rm/Rn Fx 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rm 0100 Rn 0101 Rn 0110 Rn 0110 Rn 0110 Rn 0110 Rn 0111 Rn 1000 00MD Rm Rm 00MD 01MD 10MD 11MD Rm Rm Rm Rm Rm Rm imm Rn SHAD Rm, Rn SHLD Rm, Rn LDC LDC Rm, SR Rm, SPC LDC Rm, R1_BANK LDC Rm, R5_BANK LDC Rm, R2_BANK LDC Rm, R6_BANK LDC Rm, R3_BANK LDC Rm, R7_BANK LDC Rm, GBR LDC Rm, VBR LDC Rm, SSR LDC Rm, R0_BANK LDC Rm, R4_BANK MAC.W @Rm+, @Rn+ MOV.L @ (disp:4, Rm), Rn MOV.B @Rm, Rn MOV.B @Rm+, Rn MOV.W @Rm, Rn MOV.W @Rm+, Rn MOV.L @Rm, Rn MOV MOV.L @Rm+, Rn NEGC Rm, Rn EXTS.B Rm, Rn NOT NEG Rm, Rn Rm, Rn Rm, Rn SWAP.B Rm, Rn SWAP.WRm, Rn EXTU.B Rm, Rn ADD EXTU.W Rm, Rn EXTS.W Rm, Rn # imm : 8, Rn MOV. W R0, @(disp: 4, Rn) MOV.W @(disp: 4, Rm), R0 BT disp: 8 BF disp: 8 disp MOV. B R0, @(disp: 4, Rn) 1000 01MD Rm disp MOV.B @(disp:4, Rm), R0 1000 10MD 1000 11MD 1001 Rn 1010 disp 1011 disp imm/disp imm/disp disp CMP/EQ #imm:8, R0 BT/S disp: 8 MOV.W @ (disp : 8, PC), Rn BRA BSR disp: 12 disp: 12 BF/S disp: 8 Rev. 1.00 Dec. 27, 2005 Page 68 of 932 REJ09B0269-0100 Section 2 CPU Instruction Code MSB 1100 00MD LSB imm/disp Fx: 0000 MD: 00 MOV.B R0, @(disp: 8, GBR) Fx: 0001 MD: 01 MOV.W R0, @(disp: 8, GBR) MOV.W @(disp: 8, GBR), R0 Fx: 0010 MD: 10 MOV.L R0, @(disp: 8, GBR) MOV.L @(disp: 8, GBR), R0 Fx: 0011 to 1111 MD: 11 TRAPA #imm: 8 1100 01MD disp MOV.B @(disp: 8, GBR), R0 MOVA @(disp: 8, PC), R0 1100 10MD 1100 11MD imm imm TST #imm: 8, R0 AND #imm: 8, R0 XOR #imm: 8, R0 OR #imm: 8, R0 TST.B #imm: 8, @(R0, GBR) AND.B #imm: 8, @(R0, GBR) XOR.B #imm: 8, @(R0, GBR) OR.B #imm: 8, @(R0, GBR) 1101 Rn 1110 Rn disp imm MOV.L @(disp: 8, PC), Rn MOV #imm:8, Rn 1111 ************ Note: For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual. Rev. 1.00 Dec. 27, 2005 Page 69 of 932 REJ09B0269-0100 Section 2 CPU Rev. 1.00 Dec. 27, 2005 Page 70 of 932 REJ09B0269-0100 Section 3 DSP Operating Unit Section 3 DSP Operating Unit 3.1 DSP Extended Functions This LSI incorporates a DSP unit and X/Y memory directly connected to the DSP unit. This LSI supports the DSP extended function instruction sets needed to control the DSP unit and X/Y memory. The DSP extended function instructions are divided into four groups. Extended System Control Instructions for the CPU: If the DSP extended function is enabled, the following extended system control instructions can be used for the CPU. * Repeat loop control instructions and repeat loop control register access instructions are added. Looped programs can be executed efficiently by using the zero-overhead repeat control unit. For details, refer to section 3.3, CPU Extended Instructions. * Modulo addressing control instructions and control register access instructions are added. Function allows access to data with a circular structure. For details, refer to section 3.4, DSP Data Transfer Instructions. * DSP unit register access instructions are added. Some of the DSP unit registers can be used in the same way as the CPU system registers. For details, refer to section 3.4, DSP Data Transfer Instructions. Data Transfer Instructions for Data Transfers between DSP Unit Registers and On-Chip X/Y memory: Data transfer instructions for data transfers between the DSP unit registers and onchip X/Y memory are called double-data transfer instructions. Instruction codes for these doubletransfer instructions are 16 bit codes as well as CPU instruction codes. These data transfer instructions perform data transfers between the DSP unit and on-chip X/Y memory that is directly connected to the DSP unit. These data transfer instructions can be described in combination with other DSP unit operation instructions. For details, refer to section 3.4, DSP Data Transfer Instructions. Data Transfer Instructions for Data Transfers between DSP Unit Registers and All Logical Address Spaces: Data transfer instructions for data transfers between DSP unit registers and all logical address spaces are called single-data transfer instructions. Instruction codes for the doubletransfer instructions are 16 bit codes as well as CPU instruction codes. These data transfer instructions performs data transfers between the DSP unit registers and all logical address spaces. For details, refer to section 3.4, DSP Data Transfer Instructions. DSP Unit Operation Instructions: DSP unit operation instructions are called DSP data operation instructions. These instructions are provided to execute digital signal processing operations at high speed using the DSP. Instruction codes for these instructions are 32 bits. The DSP data operation Rev. 1.00 Dec. 27, 2005 Page 71 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit instruction fields consist of two fields: field A and field B. In field A, a function for double data transfer instructions can be descried. In field B, ALU operation instructions and multiply instructions can be described. The instructions described in fields A and B can be executed in parallel. A maximum of four instructions (ALU operation, multiply, and two data transfers) can be executed in parallel. For details, refer to section 3.5, DSP Data Operation Instructions. Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes. Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit instruction codes must be stored in memory, upper word and lower word, in this order, in word units. 2. In little endian, the upper and lower words must be stored in memory as data to be accessed in word units. 15 0000 CPU core instruction 12 11 0 * 1110 15 10 9 111100 0 A Field Double-data transfer instruction 15 Single-data transfer instruction 10 9 111101 A Field 0 31 DSP data operation instruction 26 25 111110 A Field 16 15 B Field 0 Figure 3.1 DSP Instruction Format Rev. 1.00 Dec. 27, 2005 Page 72 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.2 3.2.1 DSP Mode Resources Processing Modes The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) of the status register (SR), as shown below. Description Access of Resources Protected in Privileged Mode or Privileged Instruction Execution Prohibited Prohibited Allowed MD 0 0 1 1 DSP 0 1 0 1 Processing Mode User mode User DSP mode Privileged mode DSP Extended Functions Invalid Valid Invalid Valid Privileged DSP mode Allowed As shown above, the extension of the DSP function by the DSP bit can be specified independently of the control by the MD bit. Note, however, that the DSP bit can be modified only in privileged mode. Before the DSP bit is modified, a transition to privileged mode or privileged DSP mode is necessary. 3.2.2 DSP Mode Memory Map In DSP mode, a part of the P2 area in the logical address space can be accessed in user DSP mode. When this area is accessed in user DSP mode, this area is referred to as a Uxy area. X/Y memory is then assigned to this Uxy area. Accordingly, X/Y memory can also be accessed in user DSP mode. Table 3.1 Logical Address Space Name P2/Uxy Protection Privileged or DSP Description 16-Mbyte physical address space, noncacheable, non-address translatable Can be accessed in privileged mode, privileged DSP mode, and user DSP mode Address Range H'A5000000 to H'A5FFFFFF Rev. 1.00 Dec. 27, 2005 Page 73 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.2.3 CPU Register Sets In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three control registers: a repeat start register (SR), repeat end register (RE), and module register are added as control registers. 31 0 31 30 29 28 27 RC[11:0] 16 15 0 14 0 13 12 11 10 9 8 Q 7 I3 6 I2 5 I1 4 I0 3 2 1 0 T MD RB BL 0 DSP DMY DMX M 0 RF1 RF0 S Status Register (SR) RS 31 0 Repeat Start register (RS) RE 31 16 15 0 Repeat End register (RE) ME MS MODulo register (MOD) Figure 3.2 CPU Registers in DSP Mode Extension of Status Register (SR): In DSP mode, the following control bits are added to the status register (SR). These added bits are called DSP extension bits. These DSP extension bits are valid only in DSP mode. Bit Initial Bit Name Value All 0 R/W R/W Description For details, refer to section 2, CPU. Repeat Counter Holds the number of repeat times in order to perform loop control, and can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, this bit is initialized to 0. This bit is not affected in the exception handling state. 0 R/W For details, refer to section 2, CPU. DSP Bit Enables or disables the DSP extended functions. If this bit is set to 1, the DSP extended functions are enabled. This bit can be modified in privileged mode or privileged DSP mode. This bit cannot be modified in user DSP mode. At reset, this bit is initialized to 0. This bit is not affected in the exception handling state. 31 to 28 27 to 16 RC11 to RC0 15 to 13 12 DSP Rev. 1.00 Dec. 27, 2005 Page 74 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Bit 11 10 Initial Bit Name Value DMY DMX 0 0 R/W R/W R/W Description Modulo Control Bits Enable or disable modulo addressing for X/Y memory access. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. For details, refer to section 2, CPU. Repeat Flag Bits Used by repeat control instructions. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. For details, refer to section 2, CPU. 9 to 4 3 2 FR1 FR0 0 0 R/W R/W 1 to 0 Note: When data is written to the SR register, 0 should be written to bits that are specified as 0. Repeat Start Register (RS): The repeat start register (RS) holds the start address of a loop repeat module that is controlled by the repeat function. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. Repeat End Register (RE): The repeat end register (RE) holds the end address of a loop repeat module that is controlled by the repeat function. This register can be accessed in DSP mode. At reset, this register is initialized to 0. This register is not affected in the exception handling state. Modulo Register (MOD): The modulo register stores the modulo end address and modulo start address for modulo addressing in upper and lower 16 bits. The upper and lower 16 bits of the modulo register are referred to as the ME register and MS register, respectively. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. The above registers can be accessed by the control register load instruction (LDC) and store instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however, that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and DMY bits in the SR, as described below. * In user mode, if the LCD and STC instructions are used for the RS, an illegal instruction exception occurs. Rev. 1.00 Dec. 27, 2005 Page 75 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * In privileged and privileged DSP modes, all SR bits can be modified. * In user DSP mode, the SR can be read by the STC instruction. * In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension bits can be modified. Table 3.2 Operation of SR Bits in Each Processing Mode Privileged Mode Field MD RB BL RC [11:0] DSP DMY DMX Q M I[3:0] RF[1:0] S T MD = 1 & DSP = 0 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK Privileged DSP Mode MD = 1 & DSP = 1 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK User DSP Mode MD = 0 & DSP = 1 S: OK, L: NG S: OK, L: NG S: OK, L: NG S: OK, L: OK S: OK, L: NG S: OK, L: OK S: OK, L: OK S: OK, L: NG S: OK, L: NG S: OK, L: NG S: OK, L: OK S: OK, L: NG S: OK, L: NG SETRC instruction SETRC instruction Access to DSP-Related Bit with Dedicated Instruction User Mode MD = 0 & DSP = 0 S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction S, L: Invalid instruction Initial Value after Reset 1 1 1 000000000000 0 0 0 x x 1111 x x x [Legend] S: STC instruction L: LDC instruction OK: STC/LDC operation is enabled. Invalid instruction: Exception occurs when an invalid instruction is executed. NG: Previous value is retained. No change. x: Undefined Rev. 1.00 Dec. 27, 2005 Page 76 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Before entering the exception handling state, all bits including the DSP extension bits of the SR registers are saved in the SSR. Before returning from the exception handling, all bits including the DSP extension bits of the SR must be restored. If the repeat control must be recovered before entering the exception handling state, the RS and RE registers must be recovered to the value that existed before exception handling. In addition, if it is necessary to recover modulo control before entering the exception handling state, the MOD register must be recovered to the value that existed before exception handling. 3.2.4 DSP Registers The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit of the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions. 39 32 31 A0G A1G 0 A0 A1 M0 M1 X0 X1 Y0 Y1 (a) DSP data registers 31 12 11 .................................................... TS[2:0] Initial value DSR : All 0 Others: Undefined 9 8 7 6 Z 5 N 4 V 3 1 0 DC TC GT CS[2:0] (b) DSP status register (DSR) Figure 3.3 DSP Register Configuration Rev. 1.00 Dec. 27, 2005 Page 77 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.3 3.3.1 CPU Extended Instructions Repeat Control Instructions In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this function, loop programs can be executed without overhead caused by the compare and branch instructions. Examples of Repeat Loop Programs: Examples of repeat loop programs are shown below. * Example 1: Repeat loop consisting of 4 or more instructions LDRS RptStart LDRE RptStart +4 SETRC #4 Instr0 ; Sets repeat start instruction address to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from SETRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; ; Three instruction prior to the repeat end instruction is regarded as repeat detection instruction ; ; ; [Repeat end instruction] RptStart: instr1 ... ... ... ... RptDtct: instr(N-3) RptEnd2: RptEnd1: RptEnd: instr(N-2) instr(N-1) instrN In the above program example, instructions from the RptStart address (instr1 instruction) to the RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the program are called repeat loop. The start and end instructions of the repeat loop are called the repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes instructions and starts repeat loop control if the CPU detects the completion of a specific instruction. This specific instruction is called the repeat detection instruction. In a repeat loop consisting of 4 or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. In a repeat loop consisting of 4 or more instructions, the same instruction is regarded as the RptStart instruction and RptDtct instruction. Rev. 1.00 Dec. 27, 2005 Page 78 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit To control the repeat loop, the DSP extended control registers, such as the RE register and RS register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be specified by the LDRE, LDRS, and SETRC instructions. * Repeat end register (RE) The RE register is specified by the LDRE instruction. The RE register specifies (repeat detection instruction address +4). In a repeat loop consisting of 4 or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. A repeat loop consisting of three or less instructions is described later. * Repeat start register (RS) The RS register is specified by the LDRS instruction. In a repeat loop consisting of 4 or more instructions, the RS register specifies the repeat start instruction address. In a repeat loop consisting of three or less instructions, a specific address is specified in the RS. This is described later. * Repeat counter (RC[11:0] bits of the SR) The repeat counter is specifies the number of repetitions by the SETRC instruction. During repeat loop execution, the RC holds the remaining number of repetitions. * Repeat flags (RF[1:0] bits of the SR) The repeat flags are automatically specified according to the RS and RE register values during SETRC instruction execution. The repeat flags store information on the number of instructions included in the repeat loop. Normally, the user cannot modify the repeat flag values. The CPU always executes instructions by comparing the RE register to program counter values. Because the PC stores (the current instruction address +4), if the RE matches the PC during repeat instruction detection execution, a repeat detection instruction can be detected. If a repeat detection instruction is executed without branching and if RC[11:0] > 0, then repeat control is performed. If RC[11:0] 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and then control is passed to the address specified by the RS register. Examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two instructions, and one instruction, respectively. In these examples, an instruction immediately prior to the repeat start instruction is regarded as a repeat detection instruction. The RS register specifies the specific value that indicates the number of repeat instructions. Rev. 1.00 Dec. 27, 2005 Page 79 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Example 2: Repeat loop consisting of three instructions LDRS RptStart +4 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 4) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==0 during SETRC instruction execution, the repeat loop is regarded as three-instruction repeat. RptDtct: instr0 ; An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. ; [Repeat start instruction] ; ; [Repeat end instruction] RptStart: instr1 Instr2 RptEnd: instr3 * Example 3: Repeat loop consisting of two instructions LDRS RptStart +6 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 6) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==-2 during SETRC instruction execution, the repeat loop is regarded as two-instruction repeat. RptDtct: instr0 ; An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. ; [Repeat start instruction] ; [Repeat end instruction] RptStart: instr1 RptEnd: instr2 Rev. 1.00 Dec. 27, 2005 Page 80 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Example 4: Repeat loop consisting of one instruction LDRS RptStart +8 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 8) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==-4 during SETRC instruction execution, the repeat loop is regarded as one-instruction repeat. RptDtct: instr0 ; An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. RptStart: RptEnd: instr1 ; [Repeat start instruction] == [Repeat end instruction] In repeat loops consisting of three instructions, two instructions and one instruction, specific addresses are specified in the RS register. RE - RS is calculated during SETRC instruction execution, and the number of instructions included in the repeat loop is determined according to the result. A value of 0, -2,and -4 in the result correspond to 3 instructions, two instructions, and one instruction, respectively. If repeat instruction execution is completed without branching and if RC[11:0]>0, an instruction following the repeat detection instruction is regarded as a repeat start instruction and instruction execution is repeated for the number of times corresponding to the recognized number of instructions. If RC[11:0] 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and then control is passed to the address specified by the RS register. If RC[11:0] ==1(or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and then the control is passed to the next instruction following the repeat end instruction. Note: If RE - RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat loop. (In a repeat loop consisting of four or more instructions, RE - RS is always a positive value. For details, refer to example 1 above.) If RE - RS is positive, or a value other than 0, -2,and -4, correct operation cannot be guaranteed. Rev. 1.00 Dec. 27, 2005 Page 81 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit The rule is shown in table 3.3. Table 3.3 RS and RE Setting Rule Number of Instructions in Repeat Loop 1 RS RE RptStart0 + 8 RptStart0 + 4 2 RptStart0 + 6 RptStart0 + 4 3 RptStart0 + 4 RptStart0 + 4 4 RptStart RptEnd3 + 4 Note: The terms used above in table 3.3, are defined as follows. RptStart: Address of the repeat start instruction RptStart0: Address of the instruction one instruction prior to the repeat start instruction RptEnd3: Address of the instruction three instructions prior to the repeat end instruction Repeat Control Instructions and Repeat Control Macros: To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS and LDRS instructions and then the number of repetitions must be specified by the SERTC instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions. Table 3.4 Instruction LDRS @(disp,PC) LDRE @(disp,PC) SETRC #imm Repeat Control Instructions Operation Calculates (disp x 2 + PC) and stores the result to the RS register Calculates (disp x 2 + PC) and stores the result to the RE register Sets 8-bit immediate data imm to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 255. Sets the[11:0] bits of the Rm register to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 4095. Number of Execution States 1 1 1 SETRC Rm 1 The RS and RE registers must be specified appropriately according to the rules shown in table 3.3. The SH assembler supports control macros (REPEAT) as shown in table 3.5 to solve problems. Rev. 1.00 Dec. 27, 2005 Page 82 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.5 Repeat Control Macros Number of Execution States 3 Instruction Operation REPEAT RptStart, RptEnd, #imm Specifies RptStart as repeat start instruction, RptEnd as repeat end instruction, and 8-bit immediate data #imm as number of repetitions. This macro is extended to three instructions: LDRS, LDRE, and SETRC which are converted correctly. REPEAT RptStart, RptEnd, Rm Specifies RptStart as repeat start instruction, 3 RptEnd as repeat end instruction, and the [11:0] bits of Rm as number of repetitions. This macro is extended to three instructions: LDRS, LDRE, and SETRC which are converted correctly. Using the repeat macros shown in table 3.5, examples 1 to 4 shown above can be simplified to examples 5 to 8 as shown below. * Example 5: Repeat loop consisting of 4 or more instructions (extended to the instruction stream shown in example 1, above) REPEAT RptStart, RptEnd, #4 Instr0 RptStart: instr1 ... ... ... ... instr(N-3) instr(N-2) RptEnd: instr(N-1) instrN ; ; [Repeat start instruction] ; ; ; ; ; ;[Repeat end instruction] * Example 6: Repeat loop consisting of three instructions (extended to the instruction stream shown in example 2, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 Instr2 RptEnd: instr3 ; ; [Repeat start instruction] ; ; [Repeat end instruction] Rev. 1.00 Dec. 27, 2005 Page 83 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Example 7: Repeat loop consisting of two instructions (extended to the instruction stream shown in example 3, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 RptEnd: instr2 ; ; [Repeat start instruction] ; [Repeat end instruction] * Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction stream shown in example 4, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: RptEnd: instr1 ; [Repeat start instruction] == [Repeat end instruction] ; In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC and STC instructions for the SR register. These instructions should be used if an exception is enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception handling and by restoring the stored values after exception handling. However, note that there are some restrictions on exception acceptance during repeat loop execution. For details refer to Restrictions on Repeat Loop Control in section 3.3.1, Repeat Control Instructions and section 4, Exception Handling. Table 3.6 Instruction STC RS, Rn STC RE, Rn STC.L RS, @-Rn STC.L RE, @-Rn LDC.L @Rn+, RS LDC.L @Rn+, RE LDC Rn,RS LDC Rn, RE DSP Mode Extended System Control Instructions Operation RSRn RERn Rn-4Rn, RS(Rn) Rn-4Rn, RE(Rn) (Rn)RS, Rn+4Rn (Rn)RE, Rn+4Rn Rn RS RnRE Number of Execution States 1 1 1 1 4 4 4 4 Rev. 1.00 Dec. 27, 2005 Page 84 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Restrictions on Repeat Loop Control 1. Repeat control instruction assignment The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In addition, note that at least one instruction is required between the SETRC instruction and a repeat start instruction. 2. Illegal instruction one or more instructions following the repeat detection instruction If one of the following instructions is executed between an instruction following a repeat detection instruction to a repeat end instruction, an illegal instruction exception occurs. Branch instructions BRA, BSR, BT, BF, BT/F, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA Repeat control instructions SETRC, LDRS, LDRE Load instructions for SR, RS, and RE registers LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: This restriction applies to all instructions for a repeat loop consisting of one to three instructions and to three instructions including a repeat end instruction for a repeat loop consisting of four or more instructions. 3. Instructions prohibited during repeat loop (In a repeat loop consisting of four or more instructions) The following instructions must not be placed between the repeat start instruction and repeat detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the correct operation cannot be guaranteed. Repeat control instructions SETRC, LDRS, LDRE Load instructions for SR, RS, and RE registers LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control instructions, and the external loop by other instructions such as DT or BF/S. Rev. 1.00 Dec. 27, 2005 Page 85 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 4. Restriction on branching to an instruction following the repeat detection instruction and an exception acceptance Execution of a repeat detection instruction must be completed without any branch so that the CPU can recognize the repeat loop. Therefore, when the execution branches to an instruction following the repeat detection instruction, the control will not be passed to a repeat start instruction after executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this case, the RC[11:0] bits of the SR register will not be changed. If a conditional branch instruction is used in the repeat loop, an instruction before a repeat detection instruction must be specified as a branch destination. If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call instruction must be placed before a repeat detection instruction. Here, a branch includes a return from an exception processing routine. If an exception whose return address is placed in an instruction following the repeat detection instruction occurs, the repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a transition to an exception occurs but a program cannot be returned to the previous execution state correctly. For details, refer to section 4, Exception Handling. Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction following the repeat detection instruction is regarded as a return address. In this case, a control cannot be returned to the repeat control correctly. In a TRAPA instruction, an address of an instruction following the repeat detection address is regarded as return address. Accordingly, to return to the repeat control correctly, place a return address prior to the repeat detection instruction. 2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to the low-power consumption state or an exception acceptance such as interrupts can be performed correctly. In this case, however, the repeat control cannot be returned correctly. To return to the repeat control correctly, the SLEEP instruction must be placed prior to the repeat detection instruction. 5. Branch from a repeat detection instruction If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a branch instruction, a repeat loop can be acknowledged when a branch does not occur in a branch instruction. If a branch occurs in a branch instruction, a repeat control is not performed and a branch destination instruction is executed. Rev. 1.00 Dec. 27, 2005 Page 86 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 6. Program counter during repeat control If RC[11:0] 2, the program counter (PC) value is not correct for instructions two instructions following a repeat detection instruction. In a repeat loop consisting of one to three instructions, the PC indicates the correct value (instruction address + 4) for an instruction (repeat start instruction) following a repeat detection instruction but the PC continues to indicate the same address (repeat start instruction address) from the subsequent instruction to a repeat end instruction. In a repeat loop consisting of four or more instructions, the PC indicates the correct value (instruction address + 4) for an instruction following a repeat detec-tion instruction, but PC indicates the RS and (RS +2) for instructions two and three instructions following the repeat detection instruction. Here, RS indicates the value stored in the repeat start register (RS). The correct operation cannot be guaranteed for the incorrect PC values. Accordingly, PC relative addressing instructions placed two or more instructions following the repeat detection instruction cannot be executed correctly and the correct results cannot be obtained. PC relative addressing instructions MOVA @(disp, PC), Rn MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn (Including the case when the MOV #imm,Rn is extended to MOV.W @(disp, PC), Rn or MOV.L @(disp, PC), Rn) Table 3.7 PC Value during Repeat Control (When RC[11:0] 2) Number of Instructions in Repeat Loop 1 RptDtct RptDtct + 4 2 RptDtct + 4 RptDtct1 + 4 RptDtct1 + 4 3 RptDtct + 4 RptDtct1 + 4 RptDtct1 + 4 RptDtct1 + 4 4 RptDtct +4 RptDtct1 + 4 RS RS + 2 RptDtct1 RptDtct1 + 4 RptDtct2 RptDtct3 Note: In table 3.7, the following labels are used. RptDtct: An address of the repeat detection instruction RptDtct1: An address of the instruction one instruction following the repeat start instruction (In a repeat loop consisting of one to three instructions, RptStart is a repeat start instruction) RptDtct2: An address of the instruction two instruction following the repeat start instruction RptDtct3: An address of the instruction three instruction following the repeat start instruction Rev. 1.00 Dec. 27, 2005 Page 87 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 7. Repeat counter and repeat control The CPU always executes a program with comparing the repeat end register (RE) and the program counter (PC). If the PC matches the RE while the RC[11:0] bits of the SR register are other than 0, the repeat control function is initiated. If RC 2, a control is passed to a repeat start instruction after a repeat end instruction has been executed. The RC is decremented by 1 at the completion of the repeat end instruction. In this case, restrictions 1 to 6 are also applied. If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instruction. In this case, restrictions 1 to 6 are also applied. If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. The repeat loop is executed once as normal instructions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. 3.3.2 Extended Repeat Control Instructions In the repeat control function described in section 3.3.1, Repeat Control Instructions, there are some restrictions. To reduce these restrictions, this LSI supports the extended repeat instructions to extend the repeat control function. These extended repeat control instructions were not supported in the conventional SH-DSP. To keep compatibility with the conventional SH-DSP, use the conventional repeat control instructions called compatible repeat control instructions. Program Examples Using the Extended Repeat Control Instructions: Examples of repeat loop programs using the extended repeat control instructions are shown below. Rev. 1.00 Dec. 27, 2005 Page 88 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Example 1: Repeat loop consisting of 4 or more instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; ; ; ; ; [Repeat end instruction] RptStart: instr1 ... ... ... ... instr(N-3) instr(N-2) instr(N-1) RptEnd: instrN * Example 2: Repeat loop consisting of three instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; [Repeat end instruction] RptStart: instr1 instr2 RptEnd: instr3 Rev. 1.00 Dec. 27, 2005 Page 89 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Example 3: Repeat loop consisting of two instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; [Repeat end instruction] RptStart: instr1 RptEnd: instr2 * Example 4: Repeat loop consisting of one instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 Rptstart: RptEnd: instr1 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from LDRC instruction to [Repeat start instruction] RptStart: ; [Repeat start instruction]= [Repeat end instruction] In extended repeat control instructions, a repeat start instruction address and a repeat end instruction address are stored in the RS register and RE register, respectively, regardless of the number of repeat instructions. In addition, the extended repeat control can be performed by using the LDRC instruction instead of the SETRC instruction. During the extended repeat control, a repeat loop can be recognized by executing a repeat end instruction. Therefore, there is no restriction on branches or exceptions. Extended Repeat Control Instructions: To describe the extended repeat loop, the repeat start and end addresses must be specified to the RS and RE registers by the LDRS and LDRE instructions, respectively. For the LDRS and LDRE instructions of the extended repeat control instructions, the LDRS and LDRE instructions of the compatible repeat control instructions are used. The number of repetitions are specified by the LDRC instruction. An 8-bit immediate data or the general register values can be used as an operand of the LDRC instruction. If 256 or greater value is specified to the RC, use the LDRC Rm type instructions. Rev. 1.00 Dec. 27, 2005 Page 90 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.8 Instruction Extended Repeat Control Instructions Operation Calculates (disp x 2 + PC) and stores the result to the RS register Calculates (disp x 2 + PC) and stores the result to the RE register Sets 8-bit immediate data imm to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 255. During extended repeat control, bit 0 of the RE register is set to 1. Number of Execution States 1 1 1 LDRS @(disp,PC) LDRE @(disp,PC) LDRC #imm LDRC Rm Sets the[11:0] bits of the Rm register to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 4095. During extended repeat control, bit 0 of the RE register is set to 1. 1 By executing the LDRC instruction, the CPU performs the extended repeat control function. To indicate that the CPU is being in extended repeat control, bit 0 of the RE register is set to 1 by executing the LDRC instruction. To change the RE register value by a process such as an exception handling, bit 0 of the RE register must be saved and restored correctly. By saving and restoring the RC[11:0] bits, DSP bit, and RF[1:0] bits of the SR register, RE register, and RS register correctly, a control is returned to the extended repeat function correctly after processing such as exception handling. Restrictions on Extended Repeat Loop Control 1. Extended repeat control instruction assignment The LDRC instruction must be executed after executing the LDRS and LDRE instructions. In addition, note that at least one instruction is required between the LDRC instruction and a repeat start instruction. 2. Illegal instruction one or more instructions following the repeat detection instruction If one of the following instructions is executed as a repeat end instruction, an illegal instruction exception occurs. Branch instructions Rev. 1.00 Dec. 27, 2005 Page 91 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP Repeat control instructions SETRC, LDRS, LDRE, LDRC Load instructions for SR, RS, and RE registers LCD Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: A branch instruction without delay (BT, BF, TRAPA) can be placed as a repeat end instruction. A delay stop of a delayed branch instruction can also be placed as a repeat end instruction. In this case, the RC[11:0] value is decremented by 1 regardless of branch occurrence. If no branch occurs, a control returns to a repeat start instruction. If a branch occurs, a control is passed to a branch destination. 3. Repeat counter and repeat control The CPU always execute a program with comparing the repeat end register (RE) and the (PC - 4) (current instruction address). If the (PC - 4) [31:1] matches the RE [31:1] while bit 0 of RE register is set to 1 and RC [11:0] of SR register is not 0, the extended repeat control function is initiated. If RC 2, a control is passed to a repeat start instruction after a repeat end instruction has been executed. The RC is decremented by 1 at the completion of the repeat end instruction. If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instruction. If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. The repeat loop is executed once as normal instructions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. Rev. 1.00 Dec. 27, 2005 Page 92 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.4 DSP Data Transfer Instructions In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added instructions are classified into the following three groups. 1. Double data transfer instructions The DSP unit is connected to the X memory and Y memory via the specific buses called X bus and Y bus. By using the data transfer instructions using the X and Y buses, two data items can be transferred between the DSP unit and X/Y memories simultaneously. These instructions are called double data transfer instructions. These double data transfer instructions can be described in combination with the DSP operation instructions to execute data transfer and data operation in parallel, 2. Single data transfer instructions The DSP unit is also connected to the L bus that is used by the CPU. The DSP registers other than the DSR can access any logical addresses generated by the CPU. In this case, the single data transfer instructions are used. The single data transfer instructions cannot be used in combination with the DSP operation instructions and can access only one data item at a time. 3. System control instructions Some of the DSP unit registers are handled as the CPU system registers. To control these system registers, the system control registers are supported. The DSP registers are connected to the CPU general registers via the data transfer bus (C bus). In any DSP data transfer instructions, an address to be accessed is generated and output by the CPU. For DSP data transfer instructions, some of the CPU general registers are used for address generation and specific addressing modes are used. Rev. 1.00 Dec. 27, 2005 Page 93 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit CPU LAB [31:0] XAB [15:0] YAB [15:0] DSP unit XDB [15:0] YDB [15:0] CDB [31:0] DSR A0G A0 A1G A1 M0 M1 X0 X1 Y0 Y1 LDB [31:0] X memory Y memory [Legend] XAB: XDB: YAB: YDB: LAB: LDB: CDB: X bus (address) X bus (data) Y bus (address) Y bus (data) L bus (address) L bus (data) C bus (data) Figure 3.4 DSP Registers and Bus Connections Double Data Transfer Instructions (MOVX.W, MOVY.W, MOVX.L, MOVY.L): With double data transfer group instructions, X memory and Y memory can be accessed in parallel. In this case, the specific buses called X bus and Y bus are used to access X memory and Y memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict occurs among X, Y, and L buses. Load instructions for X memory specify the X0 or X1 register as the destination operand. Load instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers for X or Y memory specify the A0 or A1 register as the source operand. These instructions use only word data (16 bits). When a word data transfer instruction is executed, the upper word of register operand is used. To load word data, data is loaded to the upper word of the destination register and the lower word of the destination register is automatically cleared to 0. Rev. 1.00 Dec. 27, 2005 Page 94 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Double data transfer instructions can be described in parallel to the DSP operation instructions. Even if a conditional operation instruction is specified in parallel to a double data transfer instruction, the specified condition does not affect the data transfer operations. For details, refer to section 3.5, DSP Data Operation Instructions. Double data transfer instructions can access only the X memory or Y memory and cannot access other memory space. The X bus and Y bus are 16 bits and support 64-byte address spaces corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF, respectively. Because these areas are included in the P2/Uxy area, they are not affected by the cache and address translation unit. Single Data Transfer Instructions: The single data transfer instructions access any memory location. All DSP registers other than the DSR* can be specified as source and destination operands. Guard bit registers A0G and A1G can also be specified as two independent registers. Because these instructions use the L bus (LAB and LDB), these instructions can access any logical space handled by the CPU. If these instructions access the cacheable area while the cache is enabled, the area accessed by these instructions are cached. The X memory and Y memory are mapped to the logical address space and can also be accessed by the single data transfer instructions. In this case, bus conflict may occur between data transfer and instruction fetch because the CPU also uses the L bus for instruction fetches. The single data transfer instructions can handle both word and longword data. In word data transfer, only the upper word of the operand register is valid. In word data load, word data is loaded into the upper word of the destination registers and the lower word of the destination is automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage. In longword data load, longword data is loaded into the upper and lower word of the destination register. If the guard bits are supported, the sign bit is extended before storage. When the guard register is stored, the sign bit is extended to the upper 24 bits of the LDB and are loaded onto the LDB bus. Notes: * Because the DSR register is defined as the system register, it can be accessed by the LDS or STS instruction. 1. Any data transfer instruction is executed at the MA stage of the pipeline. 2. Any data transfer instruction does not modify the condition code bits of the DSR register. System Control Instructions: The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system registers. Accordingly, data transfer operations between these DSP system registers and general registers or memory can be executed by the STS and LDS instructions. These DSP system registers can be treated as the CPU system register such as PR, MACL and MACH and can use the same addressing modes. Rev. 1.00 Dec. 27, 2005 Page 95 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.9 Instruction STS STS STS STS STS STS STS.L STS.L STS.L STS.L STS.L STS.L LDS.L LDS.L LDS.L LDS.L LDS.L LDS.L LDS LDS LDS LDS LDS LDS Extended System Control Instructions in DSP Mode Operation DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn Rn - 4 Rn, DSR (Rn) Rn - 4 Rn, A0 (Rn) Rn - 4 Rn, X0 (Rn) Rn - 4 Rn, X1 (Rn) Rn - 4 Rn, Y0 (Rn) Rn - 4 Rn, Y1 (Rn) (Rn) DSR, Rn + 4 Rn (Rn) A0, Rn + 4 Rn (Rn) X0, Rn + 4 Rn (Rn) X1, Rn + 4 Rn (Rn) Y0, Rn + 4 Rn (Rn) Y1, Rn + 4 Rn Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn DSR,@-Rn A0,@-Rn X0,@-Rn X1,@-Rn Y0,@-Rn Y1,@-Rn @Rn+,DSR @Rn+,A0 @Rn+,X0 @Rn+,X1 @Rn+,Y0 @Rn+,Y1 Rn,DSR Rn,A0 Rn,X0 Rn,X1 Rn,Y0 Rn,Y1 Rev. 1.00 Dec. 27, 2005 Page 96 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.4.1 General Registers The DSP instructions 10 general registers in the 16 general registers as address pointers or index registers for double data transfers and single data transfers. In the following descriptions, another register function in the DSP instructions is also indicated within parentheses [ ]. * Double data transfer instructions (X memory and Y memory are accessed simultaneously) In double data transfers, X memory Y memory can be accessed simultaneously. To specify X and Y memory addresses, two address pointers are supported. Address Pointer X memory (MOVX.W) Y memory (MOVY.W) R4, R5[Ax] R6, R7[Ay] Index Register R8 [Ix] R9 [Iy] * Single data transfer instructions In single data transfer, any logical address space can be accessed via the L bus. The following address pointers and index registers are used. Address Pointer Any logical space (MOVS.W/L) R4, R5, R2, R3[As] Index Register R8 [Is] 31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 0 General registers (DSP mode) [As2] [As3] [As0] [As1, Ax1] [Ay0] [Ay1] [Ix, Is] [Iy] X and Y double data transfers: R4, 5 R8 R6, 7 R9 [Ax] : Address register set for the for X data memory [Ix] : Index regiser for X address register set Ax [Ay] : Address register set for the for Y data memory [Iy] : Index regiser for Y address register set Ay Single data transfer s: R4, 5, 2, 3 [As] : Address register set for all data memories [Is] : Index regiser used for single data transfers R8 Figure 3.5 General Registers (DSP Mode) Rev. 1.00 Dec. 27, 2005 Page 97 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit In assembler, R0 to R9 are used as symbols. In the DSP data transfer instructions, the following register names (alias) can also be used. In assembler, described as shown below. Ix: .REG (R8) Ix indicates the alias of register 8. Other aliases are shown below. Ax0: .REG (R4) Ax1: .REG (R5) Ix: .REG (R8) Ay0: .REG (R6) Ay1: .REG (R7) Iy: .REG (R9) As0: .REG (R4); This definition is used for if the alias is required in the single data transfer As1: .REG (R5); This definition is used for if the alias is required in the single data transfer As2: .REG (R2) As3: .REG (R3) Is: .REG (R8); This definition is used for if the alias is required in the single data transfer Rev. 1.00 Dec. 27, 2005 Page 98 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.4.2 DSP Data Addressing Table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. Table 3.10 Overview of Data Transfer Instructions Double Data Transfer Instructions Single Data Transfer Instructions MOVX.W MOVY.W Address register Index register Addressing Addressing Modulo addressing Data bus Data length Bus conflict Memory Source register Destination register Ax: R4, R5, Ay: R6, R7 Ix: R8, Iy: R9 Nop/Inc (+2)/index addition: post-increment -- Possible XDB, YDB 16 bits (word) No X/Y data memory Dx, Dy: A0, A1 Dx: X0/X1 Dy: Y0/Y1 MOVS.W MOVS.L As: R2, R3, R4, R5 Is: R8 Nop/Inc (+2, +4)/index addition: post-increment Dec (-2, -4): pre-decrement Not possible LDB 16/32 bits (word/longword) Yes Entire memory space Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Addressing Mode for Double Data Transfer Instructions: The double data transfer instructions supports the following three addressing modes. * Non-update address register addressing The Ax and Ay registers are address pointers. They are not updated. * Increment address register addressing The Ax and Ay registers are address pointers. After a data transfer, they are each incremented by 2 (post- increment). * Addition index register addressing The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy register is added to each (post-increment). The double data transfer instructions do not supports Rev. 1.00 Dec. 27, 2005 Page 99 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit decrement addressing mode. To perform decrementing, -2 is set in the index register and addition index register addressing is specified. When using X/Y data addressing, bit 0 of the address pointer is invalid. Accordingly, bit 0 of the address pointer and index register must be cleared to 0 in X/Y data addressing. When accessing X and Y memory using the X and Y buses, the upper word of Ax and Ay is ignored. The result of Ay+ or Ay+Iy is stored in the lower word of Ay, while the upper word retains its original value. The Ax and Ax +Ix operations are executed in longword (32 bits) and the upper word may be changed according to the result. Single Data Addressing: The following four kinds of addressing can be used with single data transfer instructions. * Non-update address register addressing The As register is an address pointer. An access to @As is performed but As is not updated. * Increment address register addressing: The As register is an address pointer. After an access to @As, the As register is incremented by 2 or 4 (post-increment). * Addition index register addressing: The As register is an address pointer. After an access to @As, the value of the Is register is added to the As register (post-increment). * Decrement address register addressing: The As register is an address pointer. Before a data transfer, -2 or -4 is added to the As register (i.e. 2 or 4 is subtracted) (pre-decrement). In single data transfer instructions, all bits in 32-bit address are valid. 3.4.3 Modulo Addressing In double data transfer instructions, a modulo addressing can be used. If the address pointer value reaches the preset modulo end address while a modulo addressing mode is specified, the address pointer value becomes the modulo start address. To control modulo addressing, the modulo register (MOD) extended in the DSP mode and the DMX and DMY bits of the SR register are used. The MOD register is provided to set the start and end addresses of the modulo address area. The upper and lower words of the MOD register store modulo start address (MS) and modulo end Rev. 1.00 Dec. 27, 2005 Page 100 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit address (ME), respectively. The LDC and STC instructions are extended for MOD register handling. If the DMX bit of the SR register is set, the modulo addressing is specified for the X address register. If the DMY bit of the SR register is set, the modulo addressing is specified for the Y address register. Modulo addressing is valid for either the X or the Y address register, only; it cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set simultaneously (if they are, the DMY setting will be valid). ( In the future, this specification may be changed.) The DMX and DMY bits of the SR can be specified by the STC or LDC instruction for the SR register. If an exception is accepted during modulo addressing, the DMX and DMY bits of the SR and MOD register must be saved. By restoring these register values, a control is returned to the modulo addressing after an exception handling. Table 3.11 Modulo Addressing Control Instructions Instruction STC MOD, Rn STC.L MOD, @-Rn Operation MOD Rn Rn - 4 Rn, MOD (Rn) (Rn) MOD, Rn + 4 Rn Rn MOD Execution States 1 1 4 4 LDC @Rn+, MOD LDC Rn, MOD Rev. 1.00 Dec. 27, 2005 Page 101 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit An example of the use of modulo addressing is shown below. MOV.L #H'70047000,R10 ;Specify MS=H'7000 ME = H'7004 LDC R10,MOD STC SR,R10 MOV.L #H'FFFFF3FF,R11 MOV.L #H'00000400,R12 AND R11,R10 OR R12,R10 LDC R10,SR MOV.L #H'A5007000,R14 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 ; R4: H'A5007000 H'A5007002 ; R4: H'A5007002 H'A5007004 ; R4: H'A5007004 H'A5007000 (Matches to ME and MS is set) ; R4: H'A5007000 H'A5007002 ; R4: H'A5007000 H'A5007002 ;Specify ME:MS to MOD register ; ; ; ; ; ; Specify SR.DMX=1, SR.DMY=0, and X modulo addressing mode The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. When the X or Y data transfer instruction specified by the DMX or DMY is executed, the address register contents before updating are compared with ME*, and if they match, start address MS is stored in the address register as the value after updating. When the addressing type of the X/Y data transfer instruction is no-update, the X/Y data transfer instruction is not returned to MS even if they match ME. When the addressing type of the X/Y data transfer instruction is addition index register addressing, the address pointed way not match the address pointer ME and exceed it. In this case, the address pointer value does not become the modulo start address. The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory. Note: * Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and ME. Rev. 1.00 Dec. 27, 2005 Page 102 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.4.4 Memory Data Formats Memory data formats that can be used in the DSP instructions are classified into word, and longword. An address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed by MOVS.L, LDS.L, or STS.L instruction. In such cases, the data accessed cannot be guaranteed An address error will not occur if word data starting from an address other than 2n is accessed by the MOVX.W or MOVY.W instruction. When using the MOVX.W or MOVY.W instruction, an address must be specified on the boundary 2n. If an address is specified other than 2n, the data accessed cannot be guaranteed. 3.4.5 Instruction Formats of Double and Single Transfer Instructions The format of double data transfer instructions is shown in tables 3.12, and that of single data transfer instructions in table 3.13. Rev. 1.00 Dec. 27, 2005 Page 103 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.12 Double Data Transfer Instruction Formats Type Mnemonic 15 14 13 12 11 10 9 1 1 1 1 0 0 0 Ax 8 7 0 Dx 6 5 0 0 4 3 0 0 1 1 Da 1 0 1 1 1 1 1 1 0 0 0 Ay 0 Dy 0 0 2 0 1 0 1 1 0 1 0 0 1 1 Da 1 0 1 1 0 1 0 1 1 0 1 1 0 X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Note: Ax: 0 = R4, 1 = R5 Ay: 0 = R6, 1 = R7 Dx: 0 = X0, 1 = X1 Dy: 0 = Y0, 1 = Y1 Da: 0 = A0, 1 = A1 Rev. 1.00 Dec. 27, 2005 Page 104 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.13 Single Data Transfer Instruction Formats Type Single data transfer Mnemonic MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Is Note: * Codes reserved for system use. 15 14 13 12 11 10 9 1 1 1 1 0 1 As 0:R4 1:R5 2:R2 3:R3 8 7 6 5 4 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 Ds 0:(*) 1:(*) 2:(*) 3:(*) 4:(*) 5:A1 6:(*) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:A1G E:M1 F:A0G Rev. 1.00 Dec. 27, 2005 Page 105 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5 3.5.1 DSP Data Operation Instructions DSP Registers This LSI has eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register (DSR) as DSP registers (figure 3.3). Four kinds of operation access the DSP data registers. The first is DSP data processing. When a DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits (bits 39 to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are valid. When a DSP fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it sign-extends the source value to bits 39 to 32. When it uses one of these registers as the destination register, bits 39 to 32 of the result are discarded. The second kind of operation is an X or Y data transfer operation, MOVX.W, MOVY.W. This operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 3.4). The register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16). X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y memory load, but no other register can be the destination register in this operation. When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored. The third kind of operation is a single-data transfer instruction, MOVS.W or MOVS.L. These instructions access any memory location through the LDB (figure 3.4). All DSP registers connect to the LDB and can be the source or destination register of the data transfer. These instructions have word and longword access modes. In word mode, registers to be loaded or stored by this instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G. When data is loaded into a register other than A0G and A1G in word mode, the lower half of the register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39 to 32 and the lower half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an 8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0 or A1, it is sign-extended to bits 39 to 32. The fourth kind of operation is system control instructions such as LDS, STS, LDS.L, or STS.L. The DSR, A0, X0, X1, Y0, and Y1 registers of the DSP register can be treated as system registers. For these registers, data transfer instructions between the CPU general registers and system registers or memory access instructions are supported. Rev. 1.00 Dec. 27, 2005 Page 106 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions cannot use some registers shown in the tables because of instruction code limitations. For example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details of register selectability. Table 3.14 Destination Register in DSP Instructions Guard Bits Registers A0, A1 Instructions DSP operation Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer A0G, A1G Data transfer DSP operation MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL Data transfer MOVX/Y.W, MOVS.W MOVS.L 39 32 31 Register Bits 16 15 0 Sign-extended 40-bit result Sign-extended 24-bit result Cleared 16-bit result Cleared Cleared Cleared Sign-extended 16-bit data Sign-extended 32-bit data Data Data No update No update 32-bit result 16-bit result 16-bit result 32-bit data X0, X1 Y0, Y1 M0, M1 Cleared Cleared Rev. 1.00 Dec. 27, 2005 Page 107 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.15 Source Register in DSP Operations Guard Bits Registers A0, A1 Instructions DSP operation Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer A0G, A1G Data transfer DSP operation MOVX/Y.W, MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer Note: * MOVS.W MOVS.L Data Data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data 39 32 31 Register Bits 16 15 0 40-bit data 24-bit data 16-bit data 16-bit data 32-bit data X0, X1 Y0, Y1 M0, M1 The data is sign-extended and input to the ALU. The DSP unit incorporates one control register and DSP status register (DSR). The DSR register stores the DSP data operation result (zero, negative, others). The DSP register also has the DC bit whose function is similar to the T bit of the CPU register. The DC bit functions as status flag. Conditional DSP data operations are controlled based on the DC bit. These operation control affects only the DSP unit instructions. In other words, these operations control affects only the DSP registers and does not affect address register update and CPU instructions such as load and store instructions. A condition to be reflected on the DC bit should be specified to the DC status selection bits (CS[2:0]). The unconditional DSP type data instructions other than PMULS, MOVX, MOVY, and MOVS change the condition flag and DC bit. However, the CPU instructions including the MAC instruction do not modify the DC bit. In addition, conditional DSP instructions do not modify the DSR. Rev. 1.00 Dec. 27, 2005 Page 108 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.16 DSR Register Bits Bits 31 to 12 Bit Name -- Initial Value All 0 R/W R Function Reserved Bits These bits are always read as 0. The write value should always be 0. T Bit Status Selection Specifies the operation result status to be set in the T bit in the SR register if the TC bit is 1. If the S bit of the SR register is set to 1, an overflow is detected. 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed greater than or equal to mode 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) 8 TC 0 R/W TC Bit 0: The T bit of the SR register is not affected by the DSP instruction. 1: The T bit of the SR register changes according to the TS bit of the DSR register while the DSP instruction is executed. Note, however, the T bit does not change during conditional DSP instruction execution. 7 GT 0 R/W Signed Greater Bit Indicates that the operation result is positive (except 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater than operand 2 6 Z 0 R/W Zero Bit Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or operands are equal 11 to 9 TS2 to TS0 All 0 R/W Rev. 1.00 Dec. 27, 2005 Page 109 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Bits 5 Bit Name N Initial Value 0 R/W R/W Function Negative Bit Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller than operand 2 4 V 0 R/W Overflow Bit Indicates that the operation result has overflowed 1: Operation result has overflowed 3 to 1 CS2 to CS0 All 0 R/W DC Bit Status Selection Designate the mode for selecting the operation result status to be set in the DC bit 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed greater than or equal to mode 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) 0 DC 0 R/W DSP Status Bit Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status has not occurred (false) 1: Designated mode status has occurred Indicates the operation result by carry or borrow regardless of the CS bit status after the PADDC or PSUBC instruction has been executed. Rev. 1.00 Dec. 27, 2005 Page 110 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit The DSR is assigned to the system registers. For the DSR, the following load and store instructions are supported. STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0 3.5.2 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field. Instructions can be specified independently, and are also executed independently. B-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. The formats of the DSP operation instructions are shown in table 3.17. The respective operands are selected independently from the DSP registers. The correspondence between DSP operation instruction operands and registers is shown in table 3.18. Rev. 1.00 Dec. 27, 2005 Page 111 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.17 DSP Operation Instruction Formats Type Double data operation instructions Conditional single data operation instructions Instruction Formats ALUop. Sx, Sy, Du MLTop. Se, Df, Dg DCT DCF DCT DCF DCT DCF Unconditional single data operation instructions ALUop. Sx, Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sx, Dz ALUop. Sy, Dz ALUop. Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sy, Dz MLTop. Se, Sf, Dg Table 3.18 Correspondence between DSP Instruction Operands and Registers ALU/Shift Operations Register A0 A1 M0 M1 X0 X1 Y0 Y1 Yes Yes Yes Yes Sx Yes Yes Yes Yes Sy Dz Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes Yes Yes Se Multiply Operations Sf Dg Yes Yes Yes Yes When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. A sample parallel processing program is shown in figure 3.6. Rev. 1.00 Dec. 27, 2005 Page 112 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit PADD DCF PINC A0, M0, A0 M1, A1 PMULS X0, Y0, M0 MOVX.W @R4+, X0 MOVY.W @R6+, Y0 MOVY.W @R7+, Y1 [NOPY] MOVX.W @R5+R8, X0 MOVX.W @R4, X1 PCMP M1, M0 Figure 3.6 Sample Parallel Instruction Program [ ] mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. For details on the B field in DSP data operation instructions, refer to section 3.6.4, DSP Operation Instructions. The DSR register condition code bit (DC) is always updated on the basis of the result of an unconditional ALU or shift operation instruction. Conditional instructions do not update the DC bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19. Rev. 1.00 Dec. 27, 2005 Page 113 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.19 DC Bit Update Definitions CS [2:0] Condition Mode 0 0 0 Carry or borrow mode Description The DC bit is set if an ALU arithmetic operation generates a carry or borrow, and is cleared otherwise. When a PSHA or PSHL shift instruction is executed, the last bit data shifted out is copied into the DC bit. When an ALU logical operation is executed, the DC bit is always cleared. 0 0 1 Negative value mode When an ALU or shift (PSHA) arithmetic operation is executed, the MSB of the result, including the guard bits, is copied into the DC bit. When an ALU or shift (PSHL) logical operation is executed, the MSB of the result, excluding the guard bits, is copied into the DC bit. 0 0 1 1 0 1 Zero value mode Overflow mode The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise. The DC bit is set if the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. 1 0 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is mode cleared if the result is all-zeros. DC = ~{(negative value ^ over-range) | zero value}; In case of arithmetic operation DC = 0; In case of logical operation 1 0 1 Signed greater-orequal mode If the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, including the guard bits (over-range), the definition is the same as in negative value mode. If the result is not over-range, the definition is the opposite of that in negative value mode. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. DC = ~(negative value ^ over-range); In case of arithmetic operation DC = 0 ; In case of logical operation 1 1 1 1 0 1 Reserved (setting prohibited) Reserved (setting prohibited) Rev. 1.00 Dec. 27, 2005 Page 114 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit * Conditional Operations and Data Transfer Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. Examples are shown in figure 3.7. DCT PADD X0,Y0,A0 When condition is True Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00005000, (R4)=H'1111, (R6)=H'2222 After execution: X0=H'11110000, Y0=H'55555555, R4=H'00008002, R6=H'00005004, (R4)=H'1111, (R6)=H'3456 When condition is False Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00005000, (R4)=H'1111, (R6)=H'2222 After execution: X0=H'11110000, Y0=H'55555555, R4=H'00008002, R6=H'00005004, (R4)=H'1111, (R6)=H'3456 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'0088888888, R9=H'00000004 MOVX.W @R4+,X0 MOVY.W A0,@R6+R9 ; Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions * Assignment of NOPX and NOPY Instruction Codes When there is no data transfer instruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted. Examples of NOPX and NOPY instruction codes are shown in table 3.20. Rev. 1.00 Dec. 27, 2005 Page 115 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.20 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 Code 1111100000001011 1011000100000111 PADD X0,Y0,A0 NOPX MOVY.W @R6+R9,Y0 1111100000000011 1011000100000111 PADD X0,Y0,A0 NOPX NOPY 1111100000000000 1011000100000111 PADD X0,Y0,A0 NOPX 1111100000000000 1011000100000111 PADD X0,Y0,A0 1111100000000000 1011000100000111 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVS.W @R4+,X0 NOPX MOVY.W @R6+R9,Y0 MOVY.W @R6+R9,Y0 NOPX NOP NOPY MOVY.W @R6+R9,Y0 NOPY 1111000000001011 1111000000001000 1111010010001000 1111000000000011 1111000000000011 1111000000000000 0000000000001001 3.5.3 DSP-Type Data Formats This LSI has several different data formats that depend on the instruction. This section explains the data formats for DSP type instructions. Figure 3.8 shows three DSP-type data formats with different binary point positions. A CPU-type data format with the binary point to the right of bit 0 is also shown for reference. The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format does not have a binary point. The valid data lengths of the data formats depend on the instruction and the DSP register. Rev. 1.00 Dec. 27, 2005 Page 116 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit DSP type fixed point 39 With guard bits S 31 30 Without guard bits 39 Multiplier input S 31 30 S 16 15 0 -1 to +1 - 2-15 0 -1 to +1 - 2-31 31 30 0 -28 to +28 - 2-31 DSP type integer 39 With guard bits S 31 Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) S 31 22 S 31 21 16 15 S 0 -16 to +16 16 15 0 -32 to +32 16 15 0 -215 to +215 - 1 32 31 16 15 0 -223 to +223 - 1 39 DSP type logical 31 16 15 0 CPU type integer Longword 31 S 0 -231 to +231 - 1 S: Sign bit : Binary point : Does not affect the operations Figure 3.8 Data Formats The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent values from -64 to +63, but -32 to +32 are valid numbers for the instruction. Also the shift amount for a logical shift operation has a 6-bit field, but -16 to +16 are valid numbers for the instruction. The results when an invalid shift amount is specified cannot be guaranteed. Rev. 1.00 Dec. 27, 2005 Page 117 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5.4 ALU Fixed-Point Operations Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers. 39 Guard 31 Source 1 0 39 Guard 31 Source 2 0 ALU DSR GT Z N V DC Guard Destination 39 31 0 Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. ALU fixed-point operations are executed between registers. Each source and destination operand are selected independently from one of the DSP registers. When a register providing guard bits is specified as an operand, the guard bits are activated for this type of operation. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Rev. 1.00 Dec. 27, 2005 Page 118 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.21 Variation of ALU Fixed-Point Operations Mnemonic PADD PSUB PADDC PSUBC PCMP PCOPY Function Addition Subtraction Addition with carry Subtraction with borrow Comparison Data copy Source 1 Sx Sx Sx Sx Sx Sx All 0 PABS Absolute Sx All 0 PNEG Negation Sx All 0 PCLR Clear All 0 Source 2 Sy Sy Sy Sy Sy All 0 Sy All 0 Sy All 0 Sy All 0 Destination Dz (Du) Dz (Du) Dz Dz -- Dz Dz Dz Dz Dz Dz Dz Table 3.22 Correspondence between Operands and Registers Register A0 A1 M0 M1 X0 X1 Y0 Y1 Yes Yes Yes Yes Sx Yes Yes Yes Yes Sy Dz Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes As shown in figure 3.10, data loaded from the memory at the MA stage, which is programmed at the same line as the ALU operation, is not used as a source operand for this operation, even though the destination operand of the data load operation is identical to the source operand of the ALU operation. In this case, previous operation results are used as the source operands for the ALU operation, and then updated as the destination operand of the data load operation. Rev. 1.00 Dec. 27, 2005 Page 119 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Operation Sequence Example PADD X0, Y0, A0 Slot Stage MOVX.W @(R4, R8), X0 MOVX.W @R4+, X0 1 MOVX 2 MOVX & PADD 3 4 5 6 IF ID EX MA/DSP MOVX MOVX & PADD Addressing Addressing MOVX Previous cycle result is used. MOVX & PADD Figure 3.10 Operation Sequence Example Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. However, in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in DSR. The DC bit result is as follows: Carry or Borrow Mode: CS[2:0] = 000: The DC bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. Some examples are shown in figure 3.11. This mode is the default condition. When the input data is negative in a PABS or PNEG instruction, carry is generated. Rev. 1.00 Dec. 27, 2005 Page 120 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Example 1 Guard bits 0000 0000 1111111111111111 +) 0000 0000 0000 0000 0000 0001 0000 0001 0000 0000 0000 0000 Carry detecting point Carry is detected Example 2 Guard bits 111111110111 0000 0000 0000 +) 0011 11110001 0000 0000 0000 (1) 0011 11101000 0000 0000 0000 Carry detecting point Carry is not detected Example 3 Guard bits 0000 0000 0000 0000 0000 0001 -) 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 Borrow detecting point Borrow is not detected Example 4 Guard bits 0000 0000 0001 0000 0000 0001 -) 0000 0000 0001 0000 0000 0010 111111111111111111111111 Borrow detecting point Borrow is detected Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode Negative Value Mode: CS[2:0] = 001: The DC flag indicates the same value as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is a positive number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the MSB of the operation result regardless of the destination operand. Some examples are shown in figure 3.12. Example 1 Guard bits 1100 0000 0000 0000 0000 0000 +) 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Sign bit Negative value Example 2 Guard bits 0011 0000 0000 0000 0000 0000 +) 0000 0000 1000 0000 0000 0001 0011 0000 1000 0000 0000 0001 Sign bit Positive value Figure 3.12 DC Bit Generation Examples in Negative Value Mode Zero Value Mode: CS[2:0] = 010: The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit shows 1. When it is not 0, the DC bit shows 0. Overflow Mode: CS[2:0] = 011: The DC bit indicates whether or not overflow occurs in the result. When an operation yields a result beyond the range of the destination register, except the Rev. 1.00 Dec. 27, 2005 Page 121 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit guard-bit parts, the DC bit is set. Even though guard bits are provided in the destination register, the DC bit always indicates the result of when no guard bits are provided. So, the DC bit is always set if the guard-bit parts are used for large number representation. Some DC bit generation examples in overflow mode are shown in figure 3.13. Example 1 Guard bits 111111111111111111111111 +) 111111111000 0000 0000 0000 111111110111111111111111 Overflow detecting field Overflow case Example 2 Guard bits 111111111111111111111111 +) 111111111000 0000 0000 0001 111111111000 0000 0000 0000 Overflow detecting field Non overflow case Figure 3.13 DC Bit Generation Examples in Overflow Mode Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. This mode is similar to the Negative Value Mode described before, because the result of a compare operation is a positive value if the source 1 data is greater than the source 2 data. However, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called "Overrange"), even though the source 1 data is greater than the source 2 data. The DC bit is updated concerning this type of special case in this condition mode. The equation below shows the definition of getting this condition: DC = ~ {(Negative ^ Over-range) | Zero} When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of the CMP/GT operation of the CPU instruction. Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare operation PCMP. This mode is similar to the Signed Greater Than Mode described before but the equal case is also included in this mode. The equation below shows the definition of getting this condition: DC = ~ (Negative ^ Over-range) When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of a CMP/GE operation of the SH core instruction. Rev. 1.00 Dec. 27, 2005 Page 122 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. Note: The DC bit is always updated as the carry/borrow flag for `PADDC' and `PSUBC' regardless of the CS[2:0] state. * Overflow Protection The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See section 3.5.11, Overflow Protection, for details. 3.5.5 ALU Integer Operations Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.22. 39 Guard 31 Source 1 0 39 Guard 31 Source 2 0 ALU DSR GT Z N V DC Ignored Guard Destination 39 31 0 Cleared to 0 Figure 3.14 ALU Integer Arithmetic Operation Flow Rev. 1.00 Dec. 27, 2005 Page 123 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.23 Variation of ALU Integer Operations Mnemonic PINC Function Increment by 1 Source 1 Sx +1 PDEC Decrement by 1 Sx -1 Source 2 +1 Sy -1 Sy Destination Dz Dz Dz Dz Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the upper word excluding the guard bits of the operation result are input into the destination register. In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in integer arithmetic operations if they are supported. Others are basically the same operation as ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or -1. When a word data is loaded into one of the DSP unit's registers, it is input as an upper word data. When a register providing guard bits is specified as an operand, the guard bits are also activated. These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. This is the same as fixed-point operations but the lower word of each source and destination operand is not used in order to generate them. See section 3.5.4, ALU Fixed-Point Operations, for details. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. See section 3.5.4, ALU Fixed-Point Operations, for details. * Overflow Protection The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section 3.5.11, Overflow Protection, for details. Rev. 1.00 Dec. 27, 2005 Page 124 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5.6 ALU Logical Operations Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of operation. The correspondence between each operand and registers is the same as the ALU fixedpoint operations as shown in table 3.21. The ALU logical operation is executed between registers. Each source and destination operand is selected independently from one of the DSP registers. As shown in figure 3.15, this type of operation uses only the upper word of each operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared. These operations are also executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. 39 31 Source 1 0 39 31 Source 2 0 ALU DSR GT Z N V DC Ignored Destination 39 31 0 Cleared to 0 Figure 3.15 ALU Logical Operation Flow Table 3.24 Variation of ALU Logical Operations Mnemonic PAND POR PXOR Function Logical AND Logical OR Logical exclusive OR Source 1 Sx Sx Sx Source 2 Sy Sy Sy Destination Dz Dz Dz Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR register are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the Rev. 1.00 Dec. 27, 2005 Page 125 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit result is: Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always cleared. Negative Value Mode: CS[2:0] = 001: Bit 31 of the operation result is loaded into the DC bit. Zero Value Mode: CS[2:0] = 010: The DC bit is set when the operation result is zero; otherwise it is cleared. Overflow Mode: CS[2:0] = 011: The DC bit is always cleared. Signed Greater Than Mode: CS[2:0] = 100: The DC bit is always cleared. Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.5.7 Fixed-Point Multiply Operation Figure 3.16 shows the multiply operation flow. Table 3.25 shows the variation of this type of operation and table 3.26 shows the correspondence between each operand and registers. The multiply operation of the DSP unit is single-word signed single-precision multiplication. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. If a double-precision multiply operation is needed, the CPU standard double-word multiply instructions can be made of use. Rev. 1.00 Dec. 27, 2005 Page 126 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 39 31 S Source 1 0 0 39 31 S Source 2 0 Ignored MAC S Destination 0 39 31 10 Figure 3.16 Fixed-Point Multiply Operation Flow Table 3.25 Variation of Fixed-Point Multiply Operation Mnemonic PMULS Function Signed multiplication Source 1 Se Source 2 Sf Destination Dg Table 3.26 Correspondence between Operands and Registers Register A0 A1 M0 M1 X0 X1 Y0 Y1 Se -- Yes -- -- Yes Yes Yes -- Sf -- Yes -- -- Yes -- Yes Yes Dg Yes Yes Yes Yes -- -- -- -- Note: The multiply operations basically generate 32-bit operation results. So when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result. The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.16. In the SH's standard multiply operations, the lower words of both source operands are input into a MAC unit. The operation result is also different from the SH's case. The SH's multiply operation Rev. 1.00 Dec. 27, 2005 Page 127 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit result is aligned to the LSB of the destination, but the fixed-point multiply operation result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0. Multiply is always unconditional, but does not affect any condition code bits, DC, N, Z, V, and GT , in DSR. * Overflow Protection The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11, Overflow Protection, for details. If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean (+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF. 3.5.8 Shift Operations Shift operations can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation. The correspondence between each operand and registers, except for immediate operands, is the same as the ALU fixed-point operations as shown in table 3.21. Table 3.27 Variation of Shift Operations Mnemonic PSHA Sx, Sy, Dz PSHL Sx, Sy, Dz PSHA #Imm1, Dz PSHL #Imm2, Dz Function Arithmetic shift Logical shift Arithmetic shift with immediate. Logical shift with immediate. Source 1 Sx Sx Dz Dz Source 2 Sy Sy Imm1 Imm2 Destination Dz Dz Dz Dz -32 <= Imm1 <= +32, -16 <= Imm2 <= +16 Rev. 1.00 Dec. 27, 2005 Page 128 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Arithmetic Shift: Figure 3.17 shows the arithmetic shift operation flow. Left shift Right shift 39 32 31 16 15 0 0 39 32 31 16 15 0 (MSB copy) Shift out >=0 39 32 31 <0 +32- -32 23 22 16 15 Shift out Updated 0 GT DSR Z N V DC Shift amount data (source 2) Sy 6 0 Imm1 Ignored Figure 3.17 Arithmetic Shift Operation Flow Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guardbit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. In this arithmetic shift operation, all bits of the source 1 and destination operands are activated. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either a register or immediate operand. The available shift range is from -32 to +32. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -64 to +63 but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. This operation is executed in the DSP stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 Rev. 1.00 Dec. 27, 2005 Page 129 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3. 4. 5. 6. The DC bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. Zero Value Mode: CS[2:0] = 010 The DC bit is set when the operation result is zero; otherwise it is cleared. Overflow Mode: CS[2:0] = 011 The DC bit is set when an overflow occurs. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. * Overflow Protection The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.5.11, Overflow Protection, for details. Rev. 1.00 Dec. 27, 2005 Page 130 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Logical Shift: Figure 3.18 shows the logical shift operation flow. Cleared to 0 Left shift Right shift 39 32 31 16 15 0 39 32 31 16 15 0 Shift out 0 0 Shift out >=0 39 Shift amount data (source 2) 5 32 31 <0 +16- -16 22 21 16 15 Updated GT DSR Z N V DC 0 Sy 0 Ignored Imm2 Figure 3.18 Logical Shift Operation Flow As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand and the destination operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared as in the ALU logical operations. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either the register or immediate operand. The available shift range is from -16 to +16. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -32 to +31, but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 Bit 31 of the operation result is loaded into the DC bit. 3. Zero Value Mode: CS[2:0] = 010 Rev. 1.00 Dec. 27, 2005 Page 131 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is always cleared in this operation. So is the GT bit. 3.5.9 Most Significant Bit Detection Operation The PDMSB, most significant bit detection operation, is used to calculate the shift amount for normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation definition. Table 3.29 shows the possible variations of this type of operation. The correspondence between each operand and registers is the same as for ALU fixed-point operations, as shown in table 3.21. Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts. When a register not providing the guard-bit parts is specified as a destination operand, the upper word of the operation result is input into the destination register. As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the destination operand is treated as an integer operation result because shift amount data for normalization should be integer data as described in section 3.5.8, Shift Operations. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation result. Rev. 1.00 Dec. 27, 2005 Page 132 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 39 Guard 31 Source 1 or 2 0 Priority encoder GT DSR Z N V DC Guard Cleared to 0 39 31 0 Figure 3.19 PDMSB Operation Flow The definition of the DC bit is selected by the CS0-CS2 (condition selection) bits in DSR. The DC bit result is Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always cleared. Negative Value Mode: CS[2:0] = 001: The DC bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. Zero Value Mode: CS[2:0] = 010: The DC bit is set when the operation result is zero; otherwise it is cleared. Overflow Mode: CS[2:0] = 011: The DC bit is always cleared. Signed Greater Than Mode: CS[2:0] = 100: The DC bit is set when the operation result is a positive value; otherwise it is cleared. Signed Greater Than or Equal Mode: CS[2:0] = 101: The DC bit is set when the operation result is zero or a positive value; otherwise it is cleared. Rev. 1.00 Dec. 27, 2005 Page 133 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.28 Operation Definition of PDMSB Source Data Guard Bit 39 38 ... 33 32 31 Result for DST Lower Word ... 3 2 1 0 Upper Word 30 29 28 Guard Bit 39-32 Upper Word 31-22 21 20 19 18 17 16 Decimal 0 0 0 0 0 0 0 0 ... ... ... ... : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... ... : 0 0 0 0 0 0 0 1 0 0 1 * 0 1 * * All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 0 0 0 0 1 1 1 1 1 1 1 1 : 1 1 1 1 1 1 0 0 1 0 1 0 +31 +30 +29 +28 0 0 0 0 0 0 0 0 0 0 ... ... ... ... ... : 0 0 0 0 0 0 0 0 0 1 0 0 0 1 * 0 0 1 * * 0 1 * * * 1 * * * * ... ... ... ... ... : * * * * * * * * * * * * * * * * * * * * All 0 All 0 All 0 All 1 All 1 All 0 All 0 All 0 All 1 All 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 : 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 +2 +1 0 -1 -2 0 1 1 0 ... ... * * * * * * * * * * * * ... ... * * * * * * * * All 1 All 1 All 1 All 1 1 1 1 1 1 1 : 0 0 0 0 0 0 -8 -8 1 1 1 1 1 1 1 1 1 1 ... ... ... ... ... : 1 1 1 1 1 0 1 1 1 1 * 0 1 1 1 * * 0 1 1 * * * 0 1 * * * * 0 ... ... ... ... ... : * * * * * * * * * * * * * * * * * * * * All 1 All 1 All 0 All 0 All 0 All 1 All 1 All 0 All 0 All 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 : 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 -2 -1 0 +1 +2 1 1 1 1 1 1 1 1 ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... ... ... ... 1 1 1 1 0 1 1 1 * 0 1 1 * * 0 1 All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 +28 +29 +30 +31 Note: * means don't care. Rev. 1.00 Dec. 27, 2005 Page 134 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.29 Variation of PDMSB Operation Mnemonic PDMSB Function MSB detection Source Sx -- Source 2 -- Sy Destination Dz Dz The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in Overflow mode by the CS[2:0] bit. See the Overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.5.10 Rounding Operation The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guardbit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.21. As shown in figure 3.21, the rounding operation uses full-size data for both source and destination operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time rounding operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation results. The definition of the DC bit is selected by the CS0-CS2 (condition selection) bits in DSR. The result of these condition code bits is the same as the ALU-fixed point arithmetic operations. Rev. 1.00 Dec. 27, 2005 Page 135 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 39 Guard 31 Source 1 or 2 0 H'00008000 ALU DSR GT Z N V DC Guard Cleared to 0 39 31 0 Figure 3.20 Rounding Operation Flow Rounded result H'00 0002 H'00 0001 0 Analog value H'00 0001 8000 H'00 0002 0000 H'00 0002 8000 True value Figure 3.21 Definition of Rounding Operation Table 3.30 Variation of Rounding Operation Mnemonic PRND Function Rounding Source 1 Sx -- Source 2 -- Sy Destination Dz Dz * Overflow Protection The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.5.11, Overflow Protection, for details. Rev. 1.00 Dec. 27, 2005 Page 136 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5.11 Overflow Protection The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the SH's standard multiply and MAC operations. The S bit in SR is used as the overflow protection enable bit. The arithmetic operation overflows when the operation result exceeds the range of two's complement representation without guard-bit parts. Table 3.31 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the definition of overflow protection for integer arithmetic operations. The lower word of the saturation value of the integer arithmetic operation is don't care. Lower word value cannot be guaranteed. When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits. Table 3.31 Definition of Overflow Protection for Fixed-Point Arithmetic Operations Sign Positive Negative Overflow Condition Result > 1 - 2 Result < -1 -31 Fixed Value 1-2 -1 -31 Hex Representation 00 7FFF FFFF FF 8000 0000 Table 3.32 Definition of Overflow Protection for Integer Arithmetic Operations Sign Positive Negative Note: * Overflow Condition Result > 2 - 1 Result < -2 means don't care. 15 15 Fixed Value 2 -1 -2 15 15 Hex Representation 00 7FFF **** FF 8000 **** Rev. 1.00 Dec. 27, 2005 Page 137 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5.12 Local Data Move Instruction The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support CPU standard multiply/MAC operations. They can be also used as temporary storage registers by local data move instructions between MACH/L and other DSP registers. Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation of this type of instruction. MACH MACL PSTS PLDS X0 Y0 M0 A0 X1 Y1 M1 A1 A0G A1G DSR Cannot be used Figure 3.22 Local Data Move Instruction Flow Table 3.33 Variation of Local Data Move Operations Mnemonic PLDS PSTS Function Data move from DSP register to MACL/MACH Data move from MACL/MACH to DSP register Operand Dz Dz This instruction is very similar to other transfer instructions. If either the A0 or A1 register is specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are not updated regardless of the instruction result. This instruction can operate as a conditional. This instruction can operate with MOVX and MOVY in parallel. Rev. 1.00 Dec. 27, 2005 Page 138 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.5.13 Operand Conflict When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.34 shows the correspondence between each operand and registers. Table 3.34 Correspondence between Operands and Registers X-Memory Load Ax DSP Registers A0 A1 M0 M1 X0 X1 Y0 Y1 * * 2 Y-Memory Load Ay Iy Dy 6-operand ALU Sx * * 1 3-operand Multiply Se Sf Dg * * 1 2 3-operand ALU Sx * * 1 Ix Dx Sy Du * * 2 Sy Dz * * 1 1 2 * 1 * 2 1 1 * * * * * * 2 1 1 * * * 2 1 * * * * 1 1 * * 1 1 1 1 1 * 1 * 1 * * * * 1 2 2 1 * * * 1 1 1 2 * 2 * 1 * 1 * * 2 2 1 * 1 1 2 Notes: 1. Registers available for operands 2. Registers available for operands (when there is operand conflict) There are three cases of operand conflict problems. * When ALU operation and multiply instructions specify the same destination operand (Du and Dg) * When X-memory load and ALU operation specify the same destination operand (Dx and Du, or Dz) * When Y-memory load and ALU operation specify the same destination operand (Dy and Du, or Dz) In these cases above, the result is not guaranteed. Rev. 1.00 Dec. 27, 2005 Page 139 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.6 3.6.1 DSP Extended Function Instruction Set CPU Extended Instructions Table 3.35 DSP Mode Extended System Control Instructions Instruction SETRC #imm SETRC Rn LDRS @(disp,PC) LDRE @(disp,PC) STC MOD,Rn STC RS,Rn STC RE,Rn STS DSR,Rn STS A0,Rn STS X0,Rn STS X1,Rn STS Y0,Rn STS Y1,Rn STS.L DSR,@-Rn STS.L A0,@-Rn STS.L X0,@-Rn STS.L X1,@-Rn STS.L Y0,@-Rn STS.L Y1,@-Rn STC.L MOD,@-Rn STC.L RS,@-Rn STC.L RE,@-Rn Instruction Code 10000010iiiiiiii 0100nnnn00010100 10001100dddddddd 10001110dddddddd 0000nnnn01010010 0000nnnn01100010 0000nnnn01110010 0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010 0100nnnn01100010 0100nnnn01110010 0100nnnn10000010 0100nnnn10010010 0100nnnn10100010 0100nnnn10110010 0100nnnn01010011 0100nnnn01100011 0100nnnn01110011 Operation immRC (of SR) Rn[11:0] RC(of SR) (disp x 2 + PC) RS (disp x 2 + PC) RE MODRn RSRn RERn DSRRn A0Rn X0Rn X1Rn Y0Rn Y1Rn Rn-4Rn, DSR(Rn) Rn-4Rn, A0(Rn) Rn-4Rn, X0(Rn) Rn-4Rn, X1(Rn) Rn-4Rn, Y0(Rn) Rn-4Rn, Y1(Rn) Rn-4Rn, MOD(Rn) Rn-4Rn, RS(Rn) Rn-4Rn, RE(Rn) (Rn) DSR, Rn + 4Rn (Rn) A0, Rn + 4Rn (Rn) X0, Rn + 4Rn (Rn) X1, Rn + 4Rn Execution States T Bit Category 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LDS.L @Rn + ,DSR 0100nnnn01100110 LDS.L @Rn + ,A0 LDS.L @Rn + ,X0 LDS.L @Rn + ,X1 0100nnnn01110110 0100nnnn10000110 0100nnnn10010110 Rev. 1.00 Dec. 27, 2005 Page 140 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction LDS.L @Rn + ,Y0 LDS.L @Rn + ,Y1 Instruction Code Operation 0100nnnn10100110 (Rn) Y0, Rn + 4Rn 0100nnnn10110110 (Rn) Y1, Rn + 4Rn 0100nnnn01100111 (Rn) RS, Rn + 4Rn 0100nnnn01110111 (Rn) RE, Rn + 4Rn 0100nnnn01101010 RnDSR 0100nnnn01111010 RnA0 0100nnnn10001010 RnX0 0100nnnn10011010 RnX1 0100nnnn10101010 RnY0 0100nnnn10111010 RnY1 0100nnnn01011110 RnMOD 0100nnnn01101110 RnRS 0100nnnn01111110 RnRE Execution States T Bit Category 1 1 4 4 4 1 1 1 1 1 1 4 4 4 LDC.L @Rn + ,MOD 0100nnnn01010111 (Rn) MOD, Rn + 4Rn LDC.L @Rn + ,RS LDC.L @Rn + ,RE LDS Rn,DSR LDS Rn,A0 LDS Rn,X0 LDS Rn,X1 LDS Rn,Y0 LDS Rn,Y1 LDC Rn,MOD LDC Rn,RS LDC Rn,RE Rev. 1.00 Dec. 27, 2005 Page 141 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.6.2 Double-Data Transfer Instructions Table 3.36 Double Data Transfer Instruction Instruction X memory NOPX data transfer MOVX.W @Ax + ,Dx 111100A*D*0*10** MOVX.W @Ax,Dx Instruction Code 1111000*0*0*00** 111100A*D*0*01** Operation X memory no access (Ax) MSW of Dx, 0 LSW of Dx (Ax) MSW of Dx, 0 LSW of Dx, Ax + 2 Ax (Ax) MSW of Dx, 0 LSW of Dx, Ax + Ix Ax MSW of Da (Ax) MSW of Da (Ax), Ax + 2 Ax MSW of Da (Ax), Ax + Ix Ax Y memory no access (Ay) MSW of Dy, 0 LSW of Dy (Ay) MSW of Dy, 0 LSW of Dy, Ay + 2 Ay (Ay) MSW of Dy, 0 LSW of Dy, Ay + Iy Ay MSW of Da (Ay) MSW of Da (Ay), Ay + 2 Ay MSW of Da (Ay), Ay + Iy Ay Execution States DC 1 1 1 MOVX.W @Ax + Ix,Dx 111100A*D*0*11** 1 MOVX.W Da,@Ax MOVX.W Da,@Ax + MOVX.W Da,@Ax + Ix 111100A*D*1*01** 111100A*D*1*10** 111100A*D*1*11** 111100*0*0*0**00 111100*A*D*0**01 111100*A*D*0**10 1 1 1 1 1 1 -- Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay + ,Dy MOVY.W @Ay + Iy,Dy 111100*A*D*0**11 1 MOVY.W Da,@Ay MOVY.W Da,@Ay + MOVY.W Da,@Ay + Iy 111100*A*D*1**01 111100*A*D*1**10 111100*A*D*1**11 1 1 1 Rev. 1.00 Dec. 27, 2005 Page 142 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.6.3 Single-Data Transfer Instructions Table 3.37 Single Data Transfer Instructions Execution States DC Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As + ,Ds Instruction Code Operation Category 111101AADDDD0000 As-2 As, (As) MSW of Ds, 1 0 LSW of Ds 111101AADDDD0100 (As) MSW of Ds, 0 LSW of Ds 111101AADDDD1000 (As) MSW of Ds, 0 LSW of Ds, As + 2 As * * * * 1 1 1 1 1 MOVS.W @As + Ix,Ds 111101AADDDD1100 (As) MSW of Ds, 0 LSW of Ds, As + Ix As MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As + 111101AADDDD0001 As-2 As, MSW of Ds (As) 111101AADDDD0101 MSW of Ds (As) 111101AADDDD1001 MSW of Ds (As), As + 2 As 1 MOVS.W Ds,@As + Ix 111101AADDDD1101 MSW of Ds (As), As + Ix As MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As + ,Ds 111101AADDDD0010 As-4 As, (As) Ds 111101AADDDD0110 (As) Ds 111101AADDDD1010 (As) Ds, As + 4 As 111101AADDDD0011 As-4 As, Ds (As) 111101AADDDD0111 Ds (As) 111101AADDDD1011 Ds (As), As + 4 As 1 1 1 1 1 1 1 1 1 MOVS.L @As + Ix,Ds 111101AADDDD1110 (As) Ds, As + Ix As MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As + Note: * MOVS.L Ds,@As + Ix 111101AADDDD1111 Ds (As), As + Ix As If guard bit registers A0G and A1G are specified in source operand Ds, the data is output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8]. The correspondence between DSP data transfer operands and registers is shown in table 3.38. Rev. 1.00 Dec. 27, 2005 Page 143 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Table 3.38 Correspondence between DSP Data Transfer Operands and Registers Register SH register R0 R1 R2 (As2) R3 (As3) R4 (Ax0) R5 (Ax1) R6 (Ay0) R7 (Ay1) R8 (Ix) R9 (Iy) DSP register A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Note: Yes: The register which can be set. Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Ax Ix Dx Ay Iy Dy Da As Ds Rev. 1.00 Dec. 27, 2005 Page 144 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.6.4 DSP Operation Instructions Table 3.39 DSP Operation Instructions Execution States Instruction PMULS Se,Sf,Dg Instruction Code Operation 111110********** 0100eeff0000gg00 Se*Sf ->Dg (Signed) DC 1 1 1 1 1 1 1 1 1 1 * * * * * PADD Sx,Sy,Du PMULS Se,Sf,Dg PSUB Sx,Sy,Du PMULS Se,Sf,Dg PADD Sx,Sy,Dz 111110********** 0111eeffxxyygguu 111110********** 0110eeffxxyygguu 111110********** 10110001xxyyzzzz Sx + Sy ->Du Se*Sf ->Dg (Signed) Sx-Sy ->Du Se*Sf ->Dg (Signed) Sx + Sy ->Dz DCT PADD Sx,Sy,Dz DCF PADD Sx,Sy,Dz PSUB Sx,Sy,Dz 111110********** 10110010xxyyzzzz 111110********** 10110011xxyyzzzz 111110********** 10100001xxyyzzzz If DC=1, Sx + Sy ->Dz If DC=0, nop If DC=0, Sx + Sy ->Dz If DC=1, nop Sx-Sy ->Dz DCT PSUB Sx,Sy,Dz DCF PSUB Sx,Sy,Dz PSHA Sx,Sy,Dz 111110********** 10100010xxyyzzzz 111110********** 10100011xxyyzzzz 111110********** 10010001xxyyzzzz If DC=1, Sx-Sy ->Dz If DC=0, nop If DC=0, Sx-Sy ->Dz If DC=1, nop If Sy>=0, Sx< DCT PSHA Sx,Sy,Dz DCF PSHA Sx,Sy,Dz 111110********** 10010010xxyyzzzz 111110********** 10010011xxyyzzzz If DC=1 & Sy>=0, Sx< Rev. 1.00 Dec. 27, 2005 Page 145 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction PSHL Sx,Sy,Dz Instruction Code Operation 111110********** 10000001xxyyzzzz If Sy>=0, Sx< Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * DCT PSHL Sx,Sy,Dz DCF PSHL Sx,Sy,Dz PCOPY Sx,Dz 111110********** 10000010xxyyzzzz 111110********** 10000011xxyyzzzz 111110********** 11011001xx00zzzz PCOPY Sy,Dz 111110********** 1111100100yyzzzz Sy ->Dz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz DCT PCOPY Sy,Dz DCF PCOPY Sx,Dz DCF PCOPY Sy,Dz PDMSB Sx,Dz 111110********** 1111101000yyzzzz 111110********** 11011011xx00zzzz 111110********** 1111101100yyzzzz 111110********** 10011101xx00zzzz PDMSB Sy,Dz 111110********** 1011110100yyzzzz DCT PDMSB Sx,Dz DCT PDMSB Sy,Dz DCF PDMSB Sx,Dz DCF PDMSB Sy,Dz 111110********** 10011110xx00zzzz 111110********** 1011111000yyzzzz 111110********** 10011111xx00zzzz 111110********** 1011111100yyzzzz If DC=1, Sx ->Dz If DC=0, nop If DC=1, Sy ->Dz If DC=0, nop If DC=0, Sx ->Dz If DC=1, nop If DC=0, Sy ->Dz If DC=1, nop Sx ->Dz normalization count shift value Sy ->Dz normalization count shift value If DC=1, normalization count shift value Sx ->Dz If DC=0, nop If DC=1, normalization count shift value Sy ->Dz If DC=0, nop If DC=0, normalization count shift value Sx ->Dz If DC=1, nop If DC=0, normalization count shift value Sy ->Dz If DC=1, nop Rev. 1.00 Dec. 27, 2005 Page 146 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction PINC Sx,Dz Instruction Code Operation 111110********** 10011001xx00zzzz MSW of Sx + 1 ->Dz Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * PINC Sy,Dz 111110********** 1011100100yyzzzz MSW of Sy + 1 ->Dz DCT PINC Sx,Dz 111110********** 10011010xx00zzzz If DC=1, MSW of Sx + 1 ->Dz If DC=0, nop DCT PINC Sy,Dz 111110********** 1011101000yyzzzz If DC=1, MSW of Sy + 1 ->Dz If DC=0, nop DCF PINC Sx,Dz 111110********** 10011011xx00zzzz If DC=0, MSW of Sx + 1 ->Dz If DC=1, nop DCF PINC Sy,Dz 111110********** 1011101100yyzzzz If DC=0, MSW of Sy+ 1 ->Dz If DC=1, nop PNEG Sx,Dz 111110********** 11001001xx00zzzz 0-Sx ->Dz PNEG Sy,Dz 111110********** 1110100100yyzzzz 0-Sy ->Dz DCT PNEG Sx,Dz 111110********** 11001010xx00zzzz If DC=1, 0-Sx ->Dz If DC=0, nop DCT PNEG Sy,Dz 111110********** 1110101000yyzzzz If DC=1, 0-Sy ->Dz If DC=0, nop DCF PNEG Sx,Dz 111110********** 11001011xx00zzzz If DC=0, 0-Sx ->Dz If DC=1, nop DCF PNEG Sy,Dz 111110********** 1110101100yyzzzz If DC=0, 0-Sy ->Dz If DC=1, nop POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz Sx | Sy ->Dz DCT POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz DCF POR Sx,Sy,Dz 111110********** 10110111xxyyzzzz If DC=1, Sx | Sy ->Dz If DC=0, nop If DC=0, Sx | Sy ->Dz If DC=1, nop Rev. 1.00 Dec. 27, 2005 Page 147 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction PAND Sx,Sy,Dz Instruction Code Operation 111110********** 10010101xxyyzzzz Sx & Sy ->Dz Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * DCT PAND Sx,Sy,Dz DCF PAND Sx,Sy,Dz PXOR Sx,Sy,Dz 111110********** 10010110xxyyzzzz 111110********** 10010111xxyyzzzz 111110********** 10100101xxyyzzzz If DC=1, Sx & Sy ->Dz If DC=0, nop If DC=0, Sx & Sy ->Dz If DC=1, nop Sx ^ Sy ->Dz DCT PXOR Sx,Sy,Dz DCF PXOR Sx,Sy,Dz PDEC Sx,Dz 111110********** 10100110xxyyzzzz 111110********** 10100111xxyyzzzz 111110********** 10001001xx00zzzz If DC=1, Sx ^ Sy ->Dz If DC=0, nop If DC=0, Sx ^ Sy ->Dz If DC=1, nop Sx [39:16]-1 ->Dz DCT PDEC Sx,Dz 111110********** 10001010xx00zzzz If DC=1, Sx [39:16]-1 ->Dz If DC=0, nop DCF PDEC Sx,Dz 111110********** 10001011xx00zzzz If DC=0, Sx [39:16]-1 ->Dz If DC=1, nop PDEC Sy,Dz 111110********** 1010100100yyzzzz Sy [31:16]-1 ->Dz DCT PDEC Sy,Dz 111110********** 1010101000yyzzzz If DC=1, Sy [31:16]-1 ->Dz If DC=0, nop DCF PDEC Sy,Dz 111110********** 1010101100yyzzzz If DC=0, Sy [31:16]-1 ->Dz If DC=1, nop PCLR Dz 111110********** 100011010000zzzz h'00000000 ->Dz DCT PCLR Dz 111110********** 100011100000zzzz If DC=1, h'00000000 ->Dz If DC=0, nop DCF PCLR Dz 111110********** 100011110000zzzz If DC=0, h'00000000 ->Dz If DC=1, nop Rev. 1.00 Dec. 27, 2005 Page 148 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction PSHA #imm,Dz Instruction Code Operation 111110********** 00010iiiiiiizzzz If imm>=0, Dz< Execution States DC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * Carry PSHL #imm,Dz 111110********** 00000iiiiiiizzzz PSTS MACH,Dz 111110********** 110011010000zzzz DCT PSTS MACH,Dz DCF PSTS MACH,Dz PSTS MACL,Dz 111110********** 110011100000zzzz 111110********** 110011110000zzzz 111110********** 110111010000zzzz If DC=1, MACH ->Dz If DC=0, MACH ->Dz MACL ->Dz DCT PSTS MACL,Dz DCF PSTS MACL,Dz PLDS Dz,MACH 111110********** 110111100000zzzz 111110********** 110111110000zzzz 111110********** 111011010000zzzz If DC=1, MACL ->Dz If DC=0, MACL ->Dz Dz ->MACH DCT PLDS Dz,MACH DCF PLDS Dz,MACH PLDS Dz,MACL 111110********** 111011100000zzzz 111110********** 111011110000zzzz 111110********** 111111010000zzzz If DC=1, Dz ->MACH If DC=0, Dz ->MACH Dz ->MACL DCT PLDS Dz,MACL DCF PLDS Dz,MACL PADDC Sx,Sy,Dz 111110********** 111111100000zzzz 111110********** 111111110000zzzz 111110********** 10110000xxyyzzzz If DC=1, Dz ->MACL If DC=0, Dz ->MACL Sx + Sy + DC ->Dz Carry ->DC Rev. 1.00 Dec. 27, 2005 Page 149 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction PSUBC Sx,Sy, Dz Instruction Code Operation 111110********** 10100000xxyyzzzz Sx-Sy-DC ->Dz Borrow ->DC Execution States DC 1 1 1 1 1 1 Borrow * * * * * PCMP Sx,Sy 111110********** 10000100xxyy0000 Sx-Sy ->DC update PABS Sx,Dz 111110********** 10001000xx00zzzz If Sx<0, 0-Sx ->Dz If Sx>=0, Sx->Dz PABS Sy,Dz 111110********** 1010100000yyzzzz If Sy<0, 0-Sy ->Dz If Sy>=0, Sy ->Dz PRND Sx,Dz 111110********** 10011000xx00zzzz Sx + h'00008000 ->Dz h'0000 ->LSW of Dz PRND Sy,Dz 111110********** 1011100000yyzzzz Sy + h'00008000 ->Dz h'0000 ->LSW of Dz Note: * See table 3.19. Rev. 1.00 Dec. 27, 2005 Page 150 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit 3.6.5 Operation Code Map in DSP Mode Table 3.40 shows the operation code map including an instruction codes extended in the DSP mode. Table 3.40 Operation Code Map Instruction Code MSB 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rm 0000 Rm 0000 Rn Fx Fx Fx: 0000 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB MD: 00 0000 0001 STC SR, Rn STC SPC, Rn STC R0_BANK, Rn STC R4_BANK, Rn BSRF Rm PREF @Rm MOV.B Rm, @(R0, Rn) 00MD 0010 01MD 0010 10MD 0010 11MD 0010 00MD 0011 10MD 0011 Rm 01MD STC GBR, Rn STC MOD, Rn STC R1_BANK, Rn STC R5_BANK, Rn STC VBR, Rn STC RS, Rn STC R2_BANK, Rn STC R6_BANK, Rn BRAF Rm STC SSR, Rn STC RE, Rn STC R3_BANK, Rn STC R7_BANK, Rn MOV.W Rm, @(R0, Rn) SETT SETS MOV.L Rm, @(R0, Rn) CLRMAC MUL.L Rm, Rn 0000 0000 00MD 1000 0000 0000 01MD 1000 0000 0000 10MD 1000 0000 0000 11MD 1000 0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn Fx Fx 1001 1010 1011 1000 1001 CLRT CLRS LDTLB NOP DIV0U RTS SLEEP RTE MOVT STS MACH, Rn STS MACL, Rn Rn 00MD 1010 01MD 1010 10MD 1010 Fx 1011 STS PR, Rn STS DSR, Rn STS A0, Rn STS Y1, Rn STS X0, Rn STS X1, Rn STS Y0, Rn Rev. 1.00 Dec. 27, 2005 Page 151 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction Code MSB 0000 Rn Rm Fx: 0000 Fx: 0001 MD: 01 MOV.W @(R0, Rm), Rn Fx: 0010 MD: 10 MOV.L @(R0, Rm), Rn Fx: 0011 to 1111 MD: 11 MAC.L @Rm+,@Rn+ LSB MD: 00 11MD MOV. B @(R0, Rm), Rn 0001 Rn Rm disp MOV.L Rm, @(disp:4, Rn) 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn 0011 Rn 0011 Rn 0011 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn Rm Rm Rm Rm Rm Rm Rm Rm Fx Fx Fx 00MD 01MD 10MD 11MD 00MD 01MD 10MD 11MD 0000 0001 0010 MOV.B Rm, @Rn MOV.B Rm, @-Rn TST Rm, Rn CMP/STR Rm, Rn CMP/EQ Rm, Rn DIV1 Rm, Rn SUB Rm, Rn ADD Rm, Rn SHLL Rn SHLR Rn STS.L MACH, @-Rn STC.L SR, @-Rn STC.L SPC, @-Rn STC.L R0_BANK, @-Rn MOV.W Rm, @Rn MOV.W Rm, @-Rn AND Rm, Rn XTRCT Rm, Rn MOV.L Rm, @Rn MOV.L Rm, @-Rn XOR Rm, Rn MULU.W Rm, Rn CMP/HS Rm, Rn DIV0S Rm, Rn OR Rm, Rn MULSW Rm, Rn CMP/GE Rm, Rn CMP/GT Rm, Rn SUBV Rm, Rn ADDV Rm, Rn DMULU.L Rm,Rn CMP/HI Rm, Rn SUBC Rm, Rn DMULS.L Rm,Rn DT Rn CMP/PZ Rn STS.L MACL, @-Rn STC.L GBR, @-Rn STC.L MOD, @-Rn STC.L R1_BANK, @-Rn STC.L R5_BANK, @-Rn SETRC CMP/PL Rn Rn ADDC Rm, Rn SHAL Rn SHAR Rn STS.L PR, @-Rn STC.L VBR, @-Rn STC.L RS, @-Rn STC.L R2_BANK, @-Rn STC.L R6_BANK, @-Rn ROTCL ROTCR Rn Rn 00MD 0011 01MD 0011 10MD 0011 STC.L SSR, @-Rn STC.L STC.L R3_BANK, @-Rn STC.L R7_BANK, @-Rn RE, @-Rn 0100 Rn 11MD 0011 STC.L R4_BANK, @-Rn 0100 Rn 0100 Rn 0100 Rm Fx Fx 0100 0101 ROTL Rn ROTR Rn LDS.L @Rm+, MACH 00MD 0110 LDS.L @Rm+, MACL LDS.L @Rm+, PR 0100 Rm 0100 Rm 01MD 0110 10MD 0110 LDS.L @Rm+, X0 LDS.L @Rm+, X1 LDS.L @Rm+, DSR LDS.L @Rm+, Y0 LDS.L @Rm+, A0 LDS.L @Rm+, Y1 Rev. 1.00 Dec. 27, 2005 Page 152 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction Code MSB 0100 Rm 0100 Rm 0100 Rm Fx: 0000 Fx: 0001 MD: 01 LDC.L @Rm+, GBR LDC.L @Rm+, MOD LDC.L @Rm+, R1_BANK LDC.L @Rm+, R5_BANK SHLL8 Rn SHLR8 Rn LDS Rm, MACL Fx: 0010 MD: 10 LDC.L @Rm+, VBR LDC.L @Rm+, RS LDC.L @Rm+, R2_BANK LDC.L @Rm+, R6_BANK SHLL16 Rn SHLR16 Rn LDS LDS Rm, PR Rm, DSR Rm, Y0 @Rm Fx: 0011 to 1111 MD: 11 LDC.L @Rm+, SSR LDC.L @Rm+, RE LDC.L @Rm+, R3_BANK LDC.L @Rm+, R7_BANK LSB MD: 00 00MD 0111 01MD 0111 10MD 0111 LDC.L @Rm+, SR LDC.L @Rm+, SPC LDC.L @Rm+, R0_BANK 0100 Rm 11MD 0111 LDC.L @Rm+, R4_BANK 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rm/ Rn 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rm 0100 Rn 0101 Rn 0110 Rn 0110 Rn 0110 Rn 0110 Rn 0111 Rn Fx Fx 1000 1001 SHLL2 Rn SHLR2 Rn LDS Rm, MACH 00MD 1010 01MD 1010 10MD 1010 Fx 1011 LDS Rm, A0 LDS Rm, Y1 LDS Rm, X0 LDS Rm, X1 LDS JMP JSR @Rm TAS.B @Rn Rm Rm 1100 1101 SHAD Rm, Rn SHLD Rm, Rn LDC Rm, SR LDC Rm, SPC LDC Rm, R0_BANK LDC Rm, R4_BANK MAC.W @Rm+, Rn+ MOV.L @(disp:4, Rm), Rn MOV.B @Rm, Rn MOV.B @Rm+, Rn SWAP.B Rm, Rn EXTU.B Rm, Rn ADD #imm : 8, Rn MOV.W R0, @(disp: 4, Rn) SETRC #imm MOV.W @Rm, Rn MOV.W @Rm+, Rn SWAP.W Rm, Rn EXTU.W Rm, Rn MOV.L @Rm, Rn MOV.L @Rm+, Rn NEGC Rm, Rn EXTS.B Rm, Rn MOV Rm, Rn NOT Rm, Rn NEG Rm, Rn EXTS.W Rm, Rn LDC Rm, GBR LDC Rm, MOD LDC Rm, R1_BANK LDC Rm, R5_BANK LDC Rm, VBR LDC Rm, RS LDC Rm, R2_BANK LDC Rm, R6_BANK LDC Rm, SSR LDC Rm, RE LDC Rm, R3_BANK LDC Rm, R7_BANK 00MD 1110 01MD 1110 10MD 1110 11MD 1110 Rm Rm Rm Rm Rm Rm imm disp 1111 disp 00MD 01MD 10MD 11MD 1000 00MD Rn imm MOV.B R0, @(disp: 4, Rn) Rev. 1.00 Dec. 27, 2005 Page 153 of 1044 REJ09B0269-0100 Section 3 DSP Operating Unit Instruction Code MSB 1000 01MD Rm Fx: 0000 MD: 00 MOV.B @(disp:4, Rm), R0 Fx: 0001 MD: 01 MOV.W @(disp: 4, Rm), R0 BT disp: 8 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB disp 1000 10MD 1000 11MD 1001 Rn 1010 disp 1011 disp 1100 00MD imm/disp imm/disp disp CMP/EQ #imm:8, R0 LDRS @(disp:8,PC) MOV.W BRA BSR disp : 12 disp: 12 BF LDRE @(disp:8,PC) disp: 8 BT/S disp: 8 @(disp : 8, PC), Rn BF/S disp: 8 imm/disp MOV.B R0, @(disp: 8, GBR) MOV.W R0, @(disp: 8, GBR) MOV.W @(disp: 8, GBR), R0 AND AND.B #imm: 8, @(R0, GBR) #imm: 8, R0 MOV.L R0, @(disp: 8, GBR) MOV.L @(disp: 8, GBR), R0 XOR XOR.B #imm: 8, @(R0, GBR) #imm: 8, R0 TRAPA #imm: 8 1100 01MD disp MOV.B @(disp: 8, GBR), R0 MOVA @(disp: 8, PC), R0 OR OR.B #imm: 8, @(R0, GBR) #imm: 8, R0 1100 10MD 1100 11MD imm imm TST #imm: 8, R0 TST.B #imm: 8, @(R0, GBR) 1101 Rn 1110 Rn 1111 00** 1111 01** 1111 10** disp imm ******** ******** ******** MOV.L MOV @(disp: 8, PC), Rn #imm:8, Rn MOVX.W, MOVY.W Double data transfer instruction MOVS.W, MOVS.L Single data transfer instruction MOVX.W, MOVY.W Double data transfer instruction, with DSP parallel operation instruction (32-bit instruction ) 1111 11** ******** Notes: 1. For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual. 2. Instructions in the hatched areas are DSP extended instructions. These instructions can be executed only when the DSP bit of the SR register is set to 1. Rev. 1.00 Dec. 27, 2005 Page 154 of 1044 REJ09B0269-0100 Section 4 Exception Handling Section 4 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. In addition, a function to control processing requested by LSI on-chip modules or an LSI external module to the CPU may also be required. Transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. This LSI has two types of exceptions: general exceptions and interrupts. The user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. A reset input can terminate the normal program execution and pass control to the reset vector after register initialization. This reset operation can also be regarded as an exception handling. This section describes an overview of the exception handling operation. Here, general exceptions and interrupts are referred to as exception handling. For interrupts, this section describes only the process executed for interrupt requests. For details on how to generate an interrupt request, refer to section 8, Interrupt Controller (INTC). 4.1 Register Descriptions There are five registers for exception handling. A register with an undefined initial value should be initialized by the software. Refer to section 23, List of Registers, for the addresses and access sizes of these registers. * * * * * TRAPA exception register (TRA) Exception event register (EXPEVT) Interrupt event register (INTEVT) Interrupt event register 2 (INTEVT2) Exception address register (TEA) Rev. 1.00 Dec. 27, 2005 Page 155 of 932 REJ09B0269-0100 Section 4 Exception Handling Figure 4.1 shows the bit configuration of each register. 31 0 31 0 31 0 31 0 31 TEA 12 11 INTEVT2 0 TEA 12 11 INTEVT 0 INTEVT2 12 11 EXPEVT 0 INTEVT 10 9 TRA 21 0 0 0 EXPEVT TRA Figure 4.1 Register Bit Configuration 4.1.1 TRAPA Exception Register (TRA) TRA is assigned to address HFFFFFFD0 and consists of the 8-bit immediate data (imm) of the TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction is executed. Only bits 9 to 2 of the TRA can be re-written using the software. Bit Bit Name Initial Value R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 to 2 1, 0 TRA R/W R 8-bit Immediate Data Reserved These bits are always read as 0. The write value should always be 0. 31 to 10 Rev. 1.00 Dec. 27, 2005 Page 156 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.1.2 Exception Event Register (EXPEVT) EXPEVT is assigned to address HFFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified by the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 Note: * EXPEVT * R/W 12-bit Exception Code Initialized to H000 at power-on reset and H020 at manual reset. 31 to 12 4.1.3 Interrupt Event Register (INTEVT) INTEVT is assigned to address HFFFFFFD8 and consists of the exception code or the interrupt priority code. Whether the occurrence of an interrupt sets the exception code or the interrupt priority code depends on the interrupt sources. (See section 8.3.5, Interrupt Exception Handling and Priority, for details.) These exception codes and interrupt priority codes are automatically specified by the hardware when an exception occurs. Only bits 11 to 0 in INTEVT can be rewritten using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 INTEVT R/W 12-bit Exception Code 31 to 12 Rev. 1.00 Dec. 27, 2005 Page 157 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.1.4 Interrupt Event Register 2 (INTEVT2) INTEVT2 is assigned to address HA4000000 and consists of the exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 INTEVT2 R 12-bit Exception Code 31 to 12 4.1.5 Exception Address Register (TEA) TEA is assigned to address HFFFFFFFC and the logical address for an exception occurrence is stored in this register when an exception related to memory accesses occurs. TEA can be modified using the software. Bit 31 to 0 Bit Name TEA Initial Value 0 R/W R/W Description Logical address for Exception Occurrence Rev. 1.00 Dec. 27, 2005 Page 158 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.2 4.2.1 Exception Handling Function Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. By executing the return from exception handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations. If an exception occurs and the CPU accepts it, operations 1 to 8 are executed. 1. 2. 3. 4. 5. 6. 7. The contents of PC is saved in SPC. The contents of SR is saved in SSR. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. The mode (MD) bit in SR is set to 1 to place the privileged mode. The register bank (RB) bit in SR is set to 1. An exception code identifying the exception event is written to bits 11-0 of the exception event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA instruction is set to TRA. For an exception related to memory accesses, the logic address where the exception occurred is written to TEA. *1 Instruction execution jumps to the designated exception vector address to invoke the handler routine. 8. The above operations from 1 to 8 are executed in sequence. During these operations, no other exceptions may be accepted unless multiple exception acceptance is enabled. In an exception handling routine for a general exception, the appropriate exception handling must be executed based on an exception source determined by the EXPEVP. In an interrupt exception handling routine, the appropriate exception handling must be executed based on an exception source determined by the INTEVT or INTEVT2. After the exception handling routine has been completed, program execution can be resumed by executing an RTE instruction. The RTE instruction causes the following operations to be executed. 1. 2. The contents of the SSR are restored into the SR to return to the processing state in effect before the exception handling took place. A delay slot instruction of the RTE instruction is executed.*2 Rev. 1.00 Dec. 27, 2005 Page 159 of 932 REJ09B0269-0100 Section 4 Exception Handling 3. Control is passed to the address stored in the SPC. The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Notes: 1. The MMU registers are modified if an MMU exception occurs. 2. For details on the CPU processing mode in which RTE delay slot instructions are executed, please refer to section 4.5, Usage Notes. 4.2.2 Exception Vector Addresses A vector address for general exceptions is determined by adding a vector offset to a vector base address. The vector offset for general exceptions other than the TLB error exception is H00000100. The vector offset for interrupts is H00000600. The vector base address is loaded into the vector base register (VBR) using the software. The vector base address should reside in the P1 or P2 fixed physical address space. 4.2.3 Exception Codes The exception codes are written to bits 11 to 0 in EXPEVT (for reset or general exceptions) or INTEVT2 (for interrupt requests) to identify each specific exception event. See section 8, Interrupt Controller (INTC), for details on the exception codes for interrupt requests. Table 4.1 lists exception codes for resets and general exceptions. 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1, acceptance of general exceptions is restricted as described below, making it possible to effectively prevent multiple exceptions from being accepted. If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power consumption mode. A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit is cleared to 0. User break requests generated while the BL bit is set are ignored and are not retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0. Rev. 1.00 Dec. 27, 2005 Page 160 of 932 REJ09B0269-0100 Section 4 Exception Handling If a general exception other than a DMA address error or user break occurs while the BL bit is set to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to the reset vector (HA0000000) (multiple exception). In this case, unlike a normal reset, modules other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and this status is not detected by an external device. To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before restoring the SPC and SSR, the BL bit must be set to 1. 4.2.5 Exception Source Acceptance Timing and Priority Exception Request of Instruction Synchronous Type and Instruction Asynchronous Type: Resets and interrupts are requested asynchronously regardless of the program flow. In general exceptions, a DMA address error and a user break under the specific condition are also requested asynchronously. The user cannot expect on which instruction an exception is requested. For general exceptions other than a DMA address error and a user break under a specific condition, each general exception corresponds to a specific instruction. Re-Execution Type and Processing-Completion Type Exceptions: All exceptions are classified into two types: a re-execution type and a processing-completion type. If a re-execution type exception is accepted, the current instruction executed when the exception is accepted is terminated and the instruction address is saved to the SPC. After returning from the exception processing, program execution resumes from the instruction where the exception was accepted. In a processing-completion type exception, the current instruction executed when the exception is accepted is completed, the next instruction address is saved to the SPC, and then the exception processing is executed. During a delayed branch instruction and delay slot, the following operations are executed. A reexecution type exception detected in a delay slot is accepted before executing the delayed branch instruction. A processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch instruction has been executed. In this case, the acceptance of delayed branch instruction or a delay slot precedes the execution of the branch destination instruction. In the above description, a delay slot indicates an instruction following an unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed branch, the normal processing is executed. Rev. 1.00 Dec. 27, 2005 Page 161 of 932 REJ09B0269-0100 Section 4 Exception Handling Acceptance Priority and Test Priority: Acceptance priorities are determined for all exception requests. The priority of resets, general exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the CPU status. Interrupts are accepted only when resets or general exceptions are not requested. If multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. 2. 3. 4. A processing-completion type exception generated at the previous instruction* A user break before instruction execution (re-execution type) An exception related to an instruction fetch (CPU address error and MMU related exceptions: re-execution type) An exception caused by an instruction decode (General illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type) An exception related to data access (CPU address error and MMU related exceptions: reexecution type) Unconditional trap (processing-completion type) A user break other than one before instruction execution (processing-completion type) DMA address error (processing-completion type) 5. 6. 7. 8. Note: * If a processing-completion type exception is accepted at an instruction, exception processing starts before the next instruction is executed. This exception processing executed before an exception generated at the next instruction is detected. Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all exception requests being processed. Rev. 1.00 Dec. 27, 2005 Page 162 of 932 REJ09B0269-0100 Section 4 Exception Handling Table 4.1 Exception Type Reset (asynchronous) Exception Event Vectors Current Instruction Aborted Exception Event Power-on reset Manual reset H-UDI reset Priority*1 1 1 1 2 Exception Order -- -- 1 0 Process at BL=1 Reset Reset Reset Ignored Vector Code H'000 H'020 H'000 H'1E0 Vector Offset -- -- -- H'00000100 General exception Re-executed events (synchronous) User break(before instruction execution) CPU address error (instruction access) *4 2 1 Reset H'0E0 H'00000100 *5 TLB miss (instruction 2 access) *4 TLB invalid (instruction access)*4 TLB protection violation (instruction access)*4 Illegal general instruction 2 exception Illegal slot instruction exception Completed Unconditional trap (TRAPA instruction) Re-executed CPU address error (data read/write)*4 *5 TLB miss (data read/write)*4 TLB invalid (data read/write)*4 TLB protection violation (data read/write)*4 Initial page write (data write)*4 Completed User breakpoint (After instruction execution, address) 2 2 2 2 2 2 2 2 2 2 1-1 Reset H'040 H'00000400 1-2 Reset H'040 H'00000100 1-3 Reset H'0A0 H'00000100 2 Reset H'180 H'00000100 2 Reset H'1A0 H'00000100 4 Reset H'160 H'00000100 3 Reset H'0E0/ H'100 H'00000100 3-1 Reset H'040/ H'060 H'00000400 3-2 Reset H'040/ H'060 H'00000100 3-3 Reset H'0A0/ H'0C0 H'00000100 3-4 Reset H'080 H'00000100 5 Ignored H'1E0 H'00000100 Rev. 1.00 Dec. 27, 2005 Page 163 of 932 REJ09B0269-0100 Section 4 Exception Handling Current Exception Type Instruction Exception Event User breakpoint (Data break, I-BUS break) DMA address error General interrupt requests (asynchronous) Completed Interrupt requests 2 3 Priority*1 2 Exception Process Order 5 at BL=1 Ignored Vector Code H'1E0 Vector Offset H'00000100 General exception Completed events (asynchronous) 6 --* 2 Retained Retained H'5C0 --* 3 H'00000100 H'00000600 Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest. A reset has the highest priority. An interrupt is accepted only when general exceptions are not requested. 2. For details on priorities in multiple interrupt sources, refer to section 8, Interrupt Controller (INTC). 3. If an interrupt is accepted, the interrupt source register (EXPEVT) is not changed. The interrupt source code is specified in interrupt source register 2 (EXPEVT2). For details, refer to section 8, Interrupt Controller (INTC). 4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code and vector offset are specified. 5. These exception codes are valid when the MMU is used. Rev. 1.00 Dec. 27, 2005 Page 164 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.3 Individual Exception Operations This section describes the conditions for specific exception handling, and the processor operations. Resets and general exceptions are described in particular. For details on interrupt operations, refer to section 8, Interrupt Controller (INTC). 4.3.1 Resets Power-On Reset: * Conditions Power-on reset is request * Operations Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the reset vector HA0000000. For details, refer to the register descriptions in the relevant sections. Be sure to perform power-On Reset at the time of a power supply injection. Manual Reset: * Conditions Manual reset is request * Operations Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the reset vector HA0000000. For details, refer to the register descriptions in the relevant sections. H-UDI Reset: * Conditions An H-UDI reset command is input (see section 22.4.4 H-UDI Reset.) * Operations EXPEVT is set to H'000, vector base register (VBR) and status register (SR) are initialized, and branched to the reset vector (H'A0000000). VBR is cleared to H'00000000 by initialization. In SR, the MD, RB, and BL bits are set to 1, the DSP bit is cleared to 0, and the interrupt mask bits (I3 to I0) are set to B'1111. Then, the CPU and on-chip peripheral modules are initialized. For details, see the Register Description in each section. Rev. 1.00 Dec. 27, 2005 Page 165 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.3.2 General Exceptions CPU address error: * Conditions Instruction is fetched from odd address (4n + 1, 4n + 3) Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user mode * Types Instruction synchronous, re-execution type * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H0E0 An exception occurred during write: H100 * Remarks The logical address (32 bits) that caused the exception is set in TEA. Illegal general instruction exception: * Conditions When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to table 2.12 in section 2.6.2, Operation Code Map. When an undefined code other than HFC00 to HFFFF is decoded, operation cannot be guaranteed. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. Rev. 1.00 Dec. 27, 2005 Page 166 of 932 REJ09B0269-0100 Section 4 Exception Handling * Types Instruction synchronous, re-execution type * Save address An instruction address where an exception occurs * Exception code H180 * Remarks None Illegal slot instruction: * Conditions When undefined code in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR * Types Instruction synchronous, re-execution type * Save address A delayed branch instruction address * Exception code H1A0 * Remarks None Rev. 1.00 Dec. 27, 2005 Page 167 of 932 REJ09B0269-0100 Section 4 Exception Handling Unconditional trap: * Conditions TRAPA instruction executed * Types Instruction synchronous, processing-completion type * Save address An address of an instruction following TRAPA * Exception code H160 * Remarks The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA[9:2]. User break point trap: * Conditions When a break condition set in the user break controller is satisfied * Types Break (L bus) before instruction execution: Instruction synchronous, re-execution type Operand break (L bus): Instruction synchronous, processing-completion type Data break (L bus): Instruction asynchronous, processing-completion type I bus break: Instruction asynchronous, processing-completion type * Save address Re-execution type: An address of the instruction where a break occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) Processing-completion type: An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) * Exception code H1E0 * Remarks For details on the user break controller, refer to section 9, User Break Controller. Rev. 1.00 Dec. 27, 2005 Page 168 of 932 REJ09B0269-0100 Section 4 Exception Handling DMA address error: * Conditions Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) * Types Instruction asynchronous, processing-completion type * Save address An address of the instruction following the instruction where an exception occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) * Exception code H5C0 * Remarks An exception occurs when a DMA transfer is executed while an illegal instruction address described above is specified in the DMAC. Since the DMA transfer is performed asynchronously with the CPU instruction operation, an exception is also requested asynchronously with the instruction execution. For details on the DMAC, refer to section 13, Direct Memory Access Controller (DMAC). 4.3.3 General Exceptions (MMU Exceptions) When the address translation unit of the memory management unit (MMU) is valid, MMU exceptions are checked after a CPU address error has been checked. Four types of MMU exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception, initial page write exception. These exceptions are checked in this order. A vector offset for a TLB miss exception is defined as H00000400 to simplify exception source determination. For details on MMU exception operations, refer to section 5, Memory Management Unit (MMU). TLB miss exception: * Conditions Comparison of TLB addresses shows no address match. * Types Instruction synchronous, re-execution type Rev. 1.00 Dec. 27, 2005 Page 169 of 932 REJ09B0269-0100 Section 4 Exception Handling * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H040 An exception occurred during write: H060 * Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. The vector address of the TLB miss exception becomes VBR + H'0400. To speed up TLB miss processing, the offset differs from other exceptions. TLB invalid exception: * Conditions Comparison of TLB addresses shows address match but V = 0. * Types Instruction synchronous, re-execution type * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H040 An exception occurred during write: H060 * Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. TLB protection exception: * Conditions When a hit access violates the TLB protection information (PR bits). * Types Instruction synchronous, re-execution type Rev. 1.00 Dec. 27, 2005 Page 170 of 932 REJ09B0269-0100 Section 4 Exception Handling * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H0A0 An exception occurred during write: H0C0 * Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. Initial page write exception: * Conditions A hit occurred to the TLB for a data write access, but D = 0. * Types Instruction synchronous, re-execution type * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code H080 * Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. Rev. 1.00 Dec. 27, 2005 Page 171 of 932 REJ09B0269-0100 Section 4 Exception Handling 4.4 Exception Processing while DSP Extension Function is Valid When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception processing acceptance conditions or exception processing may be changed. 4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is executed when the DSP bit of SR is cleared to 0 (in a mode other than the DSP mode), an illegal instruction exception occurs. In the DSP mode, STC and LDC instructions for the SR register can be executed even in user mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP extension bits can be changed.) 4.4.2 CPU Address Error In the DSP mode, a part of the space P2 (Uxy area: HA5000000 to HA5FFFFFF) can be accessed in user mode and no CPU address error will occur even if the area is accessed. 4.4.3 Exception in Repeat Control Period If an exception is requested or an exception is accepted during repeat control, the exception may not be accepted correctly or a program execution may not be returned correctly from exception processing that is different from the normal state. These restrictions may occur from repeat detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section, this period is called the repeat control period. The following shows program examples where the number of instructions in the repeat loop are 4 or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction address are described as RptDtct. The first, second, and third instructions following the repeat detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B], [C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table 4.2 summarizes the instruction positions and restriction types. Rev. 1.00 Dec. 27, 2005 Page 172 of 932 REJ09B0269-0100 Section 4 Exception Handling Table 4.2 Instruction Position [A] [B] [C1] [C2] Instruction Positions and Restriction Types SPC* 1 Illegal Instruction*2 Interrupt, Break*3 CPU Address Error*4 Retained Added Illegal Added Retained Retained Instruction/data Instruction/data Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] 2. 2. There are a greater number of instructions that can be illegal instructions while SR.RC[11:0] 1. 3. An interrupt, break or DMA address error request is retained while SR.RC[11:0] 1. 4. A specific exception code is specified while SR.RC[11:0] 1. * Example 1: Repeat loop consisting of four or greater instructions LDRS RptStart ; [A] ; [A] ; [A] ; [A] ; [A][Repeat start instruction] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction three instructions before a repeat end instruction ; [C1] ; [C2] ; [C2][Repeat end instruction] ; [A] LDRS RptDtct + 4 SETRC #4 instr0 RptStart: instr1 ......... ......... RptDtct: RptDtct RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext Rev. 1.00 Dec. 27, 2005 Page 173 of 932 REJ09B0269-0100 Section 4 Exception Handling * Example 2: Repeat loop consisting of three instructions LDRS LDRS SETRC #4 RptDtct: RptDtct RptDtct + 4 RptDtct + 4 ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext ; [C1][Repeat start instruction] ; [C2] ; [C2][Repeat end instruction] ; [A] * Example 3: Repeat loop consisting of two instructions LDRS LDRS SETRC #4 RptDtct: RptDtct RptDtct + 6 RptDtct + 4 ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction ; [C1][Repeat start instruction] ; [C2][Repeat end instruction] ; [A] RptStart: RptDtct1 RptEnd: RptDtct2 InstrNext Rev. 1.00 Dec. 27, 2005 Page 174 of 932 REJ09B0269-0100 Section 4 Exception Handling * Example 4: Repeat loop consisting of one instruction LDRS LDRS SETRC #4 RptDtct: RptDtct RptDtct + 8 RptDtct + 4 ; [A] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptEnd: RptDtct1 ; [C1][Repeat start instruction]== [Repeat end instruction] InstrNext ; [A] Rev. 1.00 Dec. 27, 2005 Page 175 of 932 REJ09B0269-0100 Section 4 Exception Handling SPC Saved by Exception in Repeat Control Period: If an exception is accepted in the repeat control period while the repeat counter (RC[11:0]) in the SR register is two or greater, the program counter to be saved may not indicate the value to be returned correctly. To execute the repeat control after returning from an exception processing, the return address must indicate an instruction prior to a repeat detection instruction. Accordingly, if an exception is accepted in repeat control period, an exception other than re-execution type exception by a repeat detection instruction cannot return to the repeat control correctly. Table 4.3 SPC Value when Re-Execution Type Exception Occurs in Repeat Control (RC[11:0] 2) Number of Instructions in Repeat Loop 1 RptDtct RptDtct1 2 RptDtct RptDtct1 RptDtct1 3 RptDtct RptDtct1 RptDtct1 RptDtct1 4 or Greater RptDtct RptDtct1 RS-4 RS-2 Instruction where Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3 Note: The following labels are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction RS: Repeat start instruction address If a re-execution type exception is accepted at an instruction in the hatched areas above, a return address to be saved in the SPC is incorrect. If RC[11:0] is 1 or 0, a correct return address is saved in the SPC. Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is executed at the address following RptDtct1, a general illegal instruction exception occurs. For details on an address to be saved in the SPC, refer to the description in section 4.4.3, Exception in Repeat Control Period. * Branch instructions BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA * Repeat control instructions SETRC, LDRS, LDRE * Load instructions for SR, RS, and RE LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,Rs Rev. 1.00 Dec. 27, 2005 Page 176 of 932 REJ09B0269-0100 Section 4 Exception Handling Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some exception will be retained to prevent an exception acceptance at an instruction where returning from the exception cannot be performed correctly. For details, refer to repeat loop program examples 1 to 4. In the examples, exceptions generated at instructions indicated as [B], [C], [C1], or [C2], the following processing is executed. * Interrupt, DMA address error An exception request is not accepted and retained at instructions [B] and [C]. If an instruction indicates as [A] is executed at the next time, an exception request is accepted.* As shown in program examples 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat loop consisting of four instructions or less. Note: * An interrupt request or a DMA address error exception request is retained in the interrupt controller (INTC) and the direct memory access controller (DMAC) until the CPU can accept a request. * User break before instruction execution A user break before instruction execution is accepted at instruction [B], and an address of instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but the exception request is retained until an instruction [A] or [B] is executed at the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. * User break after instruction execution A user break after instruction execution cannot be accepted at instructions [B] and [C] but the exception request is retained until an instruction [A] or [B] is executed at the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. Table 4.4 Exception Acceptance in Repeat Loop Instruction [B] Not accepted Not accepted Accepted Not accepted Instruction [C] Not accepted Not accepted Not accepted Not accepted Exception Type Interrupt DMA address error User break before instruction execution User break after instruction execution Rev. 1.00 Dec. 27, 2005 Page 177 of 932 REJ09B0269-0100 Section 4 Exception Handling CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT. The SPC is saved according to the description in section 4.4.3, Exception in Repeat Control Period. After the CPU address error exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the four instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] 1. Table 4.5 Instruction Where a Specific Exception Occurs when Memory Access Exception Occurs in Repeat Control (SR.RC[11:0] 1) Number of Instructions in Repeat Loop 1 2 3 4 or Greater Instruction where Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3 Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Note: The following labels are used here. RptDtct: Repeat detection instruction RptDtct1: An instruction of one instruction following the repeat detection instruction RptDtct2: An instruction of two instruction following the repeat detection instruction RptDtct3: An instruction of three instruction following the repeat detection instruction Rev. 1.00 Dec. 27, 2005 Page 178 of 932 REJ09B0269-0100 Section 4 Exception Handling MMU Exception in Repeat Control Period: If an MMU exception occurs in the repeat control period, a specific exception code is generated as well as a CPU address error. For a TLB miss exception, TLB invalid exception, and initial page write exception, an exception code (H070) is specified in the EXPEVT. For a TLB protection exception, an exception code (H0D0) is specified in the EXPEVT. In a TLB miss exception, vector offset is specified as H00000100. An instruction where an exception occurs and the SPC value to be saved are the same as those for the CPU address error. After this exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the four instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] 1. 4.5 1. Usage Notes An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore. An acceptance of other exceptions is determined by processing mode of the SR after restore, and BL bit value. A processingcompletion type exception is accepted before an instruction at the RTE branch destination address is executed. However, note that the correct operation cannot be guaranteed if a reexecution type exception occurs. In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be accepted. If the MD and BL bits of the SR register are changed by the LDC instruction, an exception is accepted according to the changed SR value from the next instruction.* A processingcompletion type exception is accepted after the next instruction is executed. An interrupt and DMA address error in re-execution type exceptions are accepted before the next instruction is executed. 2. 3. Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched and an instruction fetch exception is accepted according to the modified SR value. Rev. 1.00 Dec. 27, 2005 Page 179 of 932 REJ09B0269-0100 Section 4 Exception Handling Rev. 1.00 Dec. 27, 2005 Page 180 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Section 5 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that supports a virtual memory system. The on-chip translation look-aside buffer (TLB) caches information for user-created address translation tables located in external memory. It enables high-speed translation of virtual addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbyte or 4 kbytes). The access rights to virtual address space can be set for each of the privileged and user modes to provide memory protection. 5.1 Role of MMU The MMU is a feature designed to make efficient use of physical memory. As shown in figure 5.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. However, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands (figure 5.1 (1)). Having the process itself consider this mapping onto physical memory would impose a large burden on the process. To lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (figure 5.1 (2)). In a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. Thus a process only has to consider operation in virtual memory. Mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. Switching of physical memory is performed via secondary storage, etc. The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously (figure 5.1 (3)). If processes running in a TSS had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (figure 5.1 (4)). In the virtual memory system, virtual memory is allocated to each process. The task of the MMU is to perform efficient mapping of these virtual memory areas onto physical memory. It also has a memory protection feature that prevents one process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may occur that the relevant translation information is not recorded in the MMU, with the result that one process may inadvertently access the virtual memory allocated to another process. In this case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Rev. 1.00 Dec. 27, 2005 Page 181 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. This makes it possible for memory management to be performed flexibly by software. The MMU has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. In the following text, the address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space. Rev. 1.00 Dec. 27, 2005 Page 182 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Virtual Memory Process 1 Physical Memory Process 1 Process 1 Physical Memory MMU Physical Memory (1) (2) Process 1 Physical Memory Process 2 Process 1 Virtual Memory MMU Physical Memory Process 2 Process 3 Process 3 (3) (4) Figure 5.1 MMU Functions 5.1.1 MMU of This LSI Virtual Address Space: This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As shown in figures 5.2 and 5.3, the virtual address space is divided into several areas. In privileged mode, a 4-Gbyte space comprising areas P0 to P4 are accessible. In user mode, a 2-Gbyte space of U0 area is accessible, and a 16-Mbyte space of Uxy area is also accessible if the DSP bit of the SR register is set to 1. Access to any area (excluding the U0 area and Uxy area) in user mode will result in an address error. If the MMU is enabled by setting the AT bit of the MMUCR register to 1, P0, P3, and U0 areas can be used as any physical address area in 1- or 4-kbyte page units. By using an 8-bit address space identifier, P0, P2, and U0 areas can be increased to up to 256 areas. Mapping from virtual address to 29-bit physical address can be achieved by the TLB. Rev. 1.00 Dec. 27, 2005 Page 183 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 1. P0, P3, and U0 Areas The P0, P3, and U0 areas can be address translated by the TLB and can be accessed through the cache. If the MMU is enabled, these areas can be mapped to any physical address space in 1- or 4-kbyte page units via the TLB. If the CE bit in the cache control register (CCR1) is set to 1 and if the corresponding cache enable bit (C bit) of the TLB entry is set to 1, access via the cache is enabled. If the MMU is disabled, replacing the upper three bits of an address in these areas with 0s creates the address in the corresponding physical address space. If the CE bit of the CCR1 register is set to 1, access via the cache is enabled. When the cache is used, either the copy-back or write-through mode is selected for write access via the WT bit in CCR1. If these areas are mapped to the on-chip module control register area or on-chip memory area in area 1 in the physical address space via the TLB, the C bit of the corresponding page must be cleared to 0. 2. P1 Area The P1 area can be accessed via the cache and cannot be address-translated by the TLB. Whether the MMU is enabled or not, replacing the upper three bits of an address in these areas with 0s creates the address in the corresponding physical address space. Use of the cache is determined by the CE bit in the cache control register (CCR1). When the cache is used, either the copy-back or write-through mode is selected for write access by the CB bit in the CCR1 register. 3. P2 Area The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB. Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with 0s creates the address in the corresponding physical address space. 4. P4 Area The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache and cannot be address-translated by the TLB. Figure 5.4 shows the configuration of the P4 area. Rev. 1.00 Dec. 27, 2005 Page 184 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 256 256 H'0000 0000 H'0000 0000 External Address Space Area 0 Area 1 Area 2 Area P0 Cacheable Address Translation Possible Area 3 Area 4 Area 5 Area 6 Area U0 Cacheable Address Translation Possible Area 7 H'8000 0000 Area P1 Cacheable Address Translation Not Possible Address Error H'8000 0000 H'A000 0000 Area P2 Non-Cacheable Address Translation Not Possible Area Uxy* H'A500 0000 H'A5FF FFFF H'C000 0000 Area P3 Cacheable Address Translation Possible Area P4 Non-Cacheable Address Translation Not Possible Address Error H'E000 0000 H'FFFF FFFF Privileged Mode User Mode H'FFFF FFFF *: Only exists when SR.DSP = 1 Figure 5.2 Virtual Address Space (MMUCR.AT = 1) Rev. 1.00 Dec. 27, 2005 Page 185 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) External Address Space H'0000 0000 Area 0 Area 1 Area 2 Area 3 H'0000 0000 Area P0 Cacheable Area 4 Area 5 Area 6 Area U0 Cacheable Area 7 H'8000 0000 Area P1 Cacheable Address Error H'8000 0000 H'A000 0000 Area P2 Non-Cacheable Area Uxy* H'A500 0000 H'A5FF FFFF H'C000 0000 Area P3 Cacheable Address Error H'E000 0000 Area P4 Non-Cacheable H'FFFF FFFF Privileged Mode User Mode H'FFFF FFFF *: Only exists when SR.DSP = 1 Figure 5.3 Virtual Address Space (MMUCR.AT = 0) Rev. 1.00 Dec. 27, 2005 Page 186 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) H'E000 0000 Reserved Area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 Cache Address Array Cache Data Array TLB Address Array TLB Data Array Reserved Area H'FC00 0000 Control Register Area H'FFFF FFFF Figure 5.4 P4 Area The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For more information, see section 6.4, Memory-Mapped Cache. The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more information, see section 6.4, Memory-Mapped Cache. The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For more information, see section 5.6, Memory-Mapped TLB. The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more information, see section 5.6, Memory-Mapped TLB. The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral modules. For more information, see section 23, List of Registers. 5. Uxy Area The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user mode when the DSP bit in the SR register is set to 1. In user mode, accessing this area when the DSP bit is 0 will result in an address error. This area cannot be accessed via the cache and cannot be address-translated by the TLB. For more information on the Uxy area, see section 7, X/Y Memory. Rev. 1.00 Dec. 27, 2005 Page 187 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Physical Address Space: This LSI supports a 29-bit physical address space. As shown in figure 5.5, the physical address space is divided into eight areas. Area 1 is mapped to the on-chip module control register area and on-chip memory area. Area 7 is reserved. For details on physical address space, refer to section 12, Bus State Controller (BSC). H'0000 0000 Area 0 H'0400 0000 Area 1 (On-Chip module control Register and On-Chip Memories) H'0800 0000 Area 2 H'0C00 0000 Area 3 H'1000 0000 Area 4 H'1400 0000 Area 5 H'1800 0000 Area 6 H'1C00 0000 Area 7 (Reserved Area) H'1FFF FFFF Figure 5.5 External Memory Space Address Transition: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the physical address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is searched by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The corresponding physical address and the page control information are read from the TLB and the physical address is determined. If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed. When the MMU is enabled, address translation information that Rev. 1.00 Dec. 27, 2005 Page 188 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) results in a physical address space of H'20000000 to H'FFFFFFFF should not be registered in the TLB. When the MMU is disabled, masking the upper three bits of the virtual address to 0s creates the address in the corresponding physical address space. Since this LSI supports 29-bit address space as physical address space, the upper three bits of the virtual address are ignored as shadow areas. For details, refer to section 12, Bus State Controller (BSC). For example, address H'00001000 in the P0 area, address H'80001000 in the P1 area, address H'A0001000 in the P2 area, and address H'C0001000 in the P3 area are all mapped to the same physical memory. If these addresses are accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the continuity of addresses stored in the address array of the cache. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is selected. In terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the TLB address comparison method (see section 5.3.3, TLB Address Comparison). Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing virtual address space. The ASID is eight bits in length and can be set by software setting of the ASID of the currently running process in page table entry register high (PTEH) within the MMU. When the process is switched using the ASID, the TLB does not have to be purged. In single virtual memory mode, the ASID is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 5.3.3, TLB Address Comparison). 5.2 Register Descriptions There are four registers for MMU processing. These are all peripheral module registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address. Rev. 1.00 Dec. 27, 2005 Page 189 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) The MMU has the following registers. Refer the section 23, List of Registers, for the addresses and access size for these registers. * * * * Page table entry register high (PTEH) Page table entry register low (PTEL) Translation table base register (TTB) MMU control register (MMUCR) Page Table Entry Register High (PTEH) 5.2.1 The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address at which the exception is generated in case of an MMU exception or address error exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the ASID, software sets the number of the currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB instruction. A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas. Bit 31 to 10 9, 8 Bit Name VPN Initial Value All 0 R/W R/W R Description Number of Virtual Page Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 ASID R/W Address space identifier Rev. 1.00 Dec. 27, 2005 Page 190 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.2.2 Page Table Entry Register Low (PTEL) The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified in response to a software command. Bit 31 to 29 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 28 to 10 9 8 7 6, 5 4 3 2 1 0 PPN V PR SZ C D SH 0 0 0 R R/W Number of Physical Page Page management information For more details, see section 5.3, TLB Functions 5.2.3 Translation Table Base Register (TTB) The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the base address of the current page table. The hardware does not set any value in TTB automatically. TTB is available to software for general purposes. The initial value is undefined. 5.2.4 MMU Control Register (MMUCR) The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 5.3. Any program that modifies MMUCR should reside in the P1 or P2 area. Rev. 1.00 Dec. 27, 2005 Page 191 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Bit 31 to 9 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 8 SV 0 R/W Single virtual memory mode 0: Multiple virtual memory mode 1: Single virtual memory mode 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 RC All 0 R/W Random counter A 2-bit random counter that is automatically updated by hardware according to the following rules in the event of an MMU exception. When a TLB miss exception occurs, all of TLB entry way corresponding to the virtual address at which the exception occurred are checked. If all ways are valid, 1 is added to RC; if there is one or more invalid way, they are set by priority from way 0, in the order way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB miss exception, the way which caused the exception is set in RC. 3 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 TF 0 R/W TLB flush Write 1 to flush the TLB (clear all valid bits of the TLB to 0). When they are read, 0 is always returned. 1 IX 0 R/W Index mode 0: VPN bits 16 to 12 are used as the TLB index number. 1: The value obtained by EX-ORing ASID bits 4 to 0 in PTEH and VPN bits 16 to 12 is used as the TLB index number. Rev. 1.00 Dec. 27, 2005 Page 192 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Bit 0 Bit Name AT Initial Value 0 R/W R/W Description Address translation Enables/disables the MMU. 0: MMU disabled 1: MMU enabled 5.3 5.3.1 TLB Functions Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the logical page number and the corresponding physical number, the address space identifier, and the control information for the page, which is the unit of address translation. Figure 5.6 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 5.7 shows the configuration of virtual addresses and TLB entries. Way 0 to 3 Way 0 to 3 Entry 0 Entry 1 VPN(31-17) VPN(11-10) ASID(7-0) V Entry 0 Entry 1 PPN(28-10) PR(1-0) SZ C D SH Entry 31 Address Array Entry 31 Data Array Figure 5.6 Overall Configuration of the TLB Rev. 1.00 Dec. 27, 2005 Page 193 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 31 VPN 10 9 Offset Virtual Address (1-kbyte Page) 0 31 VPN 12 11 Offset Virtual Address (4-kbyte Page) 0 (15) (2) (8) (1) TLB Entry (19) PPN (2) (1) (1) (1) (1) PR SZ C D SH VPN (31-17) VPN (11-0) ASID V Legend VPN: Virtual page number Upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16 to 12 are used as the index number, they are not stored in the TLB entry. Attention must be paid to the synonym problem (see section 5.4.4, Avoiding Synonym Problems). ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is performed. SH: Share status bit 0: Page not shared between processes 1: Page shared between processes Page-size bit 0: 1-kbyte page 1: 4-kbyte page Valid bit Indicates whether entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. SZ: V: PPN: Physical page number Upper 22 bits of physical address. PPN bits 11 to10 are not used in case of a 4-kbyte page. PR: Protection key field 2-bit field encoded to define the access rights to the page. 00: Reading only is possible in privileged mode. 01: Reading/writing is possible in privileged mode. 10: Reading only is possible in privileged/user mode. 11: Reading/writing is possible in privileged/user mode. Cacheable bit Indicates whether the page is cacheable. 0: Non-cacheable 1: Cacheable Dirty bit Indicates whether the page has been written to. 0: Not written to C: D: Figure 5.7 Virtual Address and TLB Structure Rev. 1.00 Dec. 27, 2005 Page 194 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16 to 12 alone are used as the index number 2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index number The first method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space (multiple virtual memory) and a specific entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1), IX bit should be set to 0. Figures 5.8 and 5.9 show the indexing schemes. Virtual Address 31 PTEH Register 31 17 16 12 11 0 10 0 ASID(4-0) 7 ASID 0 VPN Exclusive-OR Index Way 0 to 3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address Array Data Array Figure 5.8 TLB Indexing (IX = 1) Rev. 1.00 Dec. 27, 2005 Page 195 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Virtual Address 31 17 16 12 11 0 Index Way 0 to 3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address Array Data Array Figure 5.9 TLB Indexing (IX = 0) 5.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered. It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. An example of setting which causes TLB hits to occur simultaneously in more than one way is described below. It is necessary to ensure that this kind of setting is not made by software. 1. If there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB hits in both these ways. 2. If several entries which have different ASID with the same VPN are registered in single virtual memory mode, there is the possibility of simultaneous TLB hits in more than one way when accessing the corresponding page in privileged mode. Several entries with the same VPN must not be registered in single virtual memory mode. 3. There is the possibility of simultaneous TLB hits in more than one way. These hits may occur depending on the contents of ASID in PTEH when a page to which SH is set 1 is registered in the TLB in index mode (MMUCR.IX = 1). Therefore a page to which SH is set 1 must not be Rev. 1.00 Dec. 27, 2005 Page 196 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) registered in index mode. When memory is shared by several processings, different pages must be registered in each ASID. The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1). The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 5.10. SH = 1 or (SR.MD = 1 and MMUCR.SV = 1)? No Yes SZ = 0? No (4-kbyte) SZ = 0? No (4-kbyte) Yes (1-kbyte) Yes (1-kbyte) Bits Compared: VPN 31 to 17 VPN 11 to 10 Bits Compared: VPN 31 to 17 Bits Compared: VPN 31 to 17 VPN 11 to 10 ASID 7 to 0 Bits Compared: VPN 31 to 17 ASID 7 to 0 Figure 5.10 Objects of Address Comparison Rev. 1.00 Dec. 27, 2005 Page 197 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. To record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. When the control registers and on-chip memory in area 1 are mapped, set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at non-permitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 5.1. Rev. 1.00 Dec. 27, 2005 Page 198 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Table 5.1 Access States Designated by D, C, and PR Bits Privileged Mode Reading Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception Permitted Reading Permitted Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception Permitted User Mode Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception TLB protection violation exception Permitted D bit 0 1 Permitted Permitted Permitted (no caching) Permitted (with caching) Permitted C bit 0 1 PR bit 00 01 Permitted 10 Permitted TLB protection violation exception Permitted 11 Permitted Permitted Rev. 1.00 Dec. 27, 2005 Page 199 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.4 5.4.1 MMU Functions MMU Hardware Management There are two kinds of MMU hardware management as follows. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit). For details of the determination method and the hardware processing, see section 5.5, MMU Exceptions. 5.4.2 MMU Software Management There are three kinds of MMU software management, as follows. 1. MMU register setting MMUCR setting, in particular, should be performed in areas P1 and P2 for which address translation is not performed. Also, since SV and IX bit changes constitute address translation system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided with software that does not use the MMU. 2. TLB entry recording, deletion, and reading TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory allocation TLB can be accessed. See section 5.4.3, MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 5.6, Memory-Mapped TLB, for details of the memorymapped TLB. 3. MMU exception processing When an MMU exception is generated, it is handled on the basis of information set from the hardware side. See section 5.5, MMU Exceptions, for details. When single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to specify recording of all TLB entries. This strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. Rev. 1.00 Dec. 27, 2005 Page 200 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Recording a 1- or 4- kbyte page TLB entry may result in a synonym problem. See section 5.4.4, Avoiding Synonym Problems. 5.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in PTEH and ASID bits 4 to 0 in PTEH are used as the index number. Figure 5.11 shows the case where the IX bit in MMUCR is 0. When an MMU exception occurs, the virtual page number of the virtual address that caused the exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception according to the rules (see section 5.2.4, MMU Control Register (MMUCR)). Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine, TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR. As the LDTLB instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure, therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two instructions after the LDTLB instruction. Rev. 1.00 Dec. 27, 2005 Page 201 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) MMUCR 31 9 0 0 Index PTEH Register 31 17 SV 0 0 RC 0 TF IX AT Way Selection PTEL Register 31 29 28 10 12 10 8 0 0 VPN VPN 0 ASID 00 0 PPN 0 V 0 PR SZ C D SH 0 Write Way 0 to 3 Write 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(28-10) PR(1-0) SZ C D SH 31 Address Array Data Array Figure 5.11 Operation of LDTLB Instruction 5.4.4 Avoiding Synonym Problems When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason that this problem occurs is explained below with reference to figure 5.12. The relationship between bit n of the virtual address and cache size is shown in the following table. Cache Size 16 kbytes 32 kbytes Bit n of Virtual Address 11 12 To achieve high-speed operation of this LSI's cache, an index number is created using virtual address [n:4]. When a 1-kbyte page is used, virtual address [n:10] is subject to address translation and when a 4-kbyte page is used, a virtual address [n:12] is subject to address translation. Therefore, the physical address [n:10] may not be the same as the virtual address [n:10]. For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Rev. 1.00 Dec. 27, 2005 Page 202 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Virtual address 1 H'00000000 physical address H'00000C00 Virtual address 2 H'00000C00 physical address H'00000C00 Virtual address 1 is recorded in cache entry H'000, and virtual address 2 in cache entry H'0C0. Since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. Consequently, the following restrictions apply to the recording of address translation information in TLB entries. 1. When address translation information whereby a number of 1-kbyte page TLB entries are translated into the same physical address is recorded in the TLB, ensure that the VPN [n:10] are the same. 2. When address translation information whereby a number of 4-kbyte page TLB entries are translated into the same physical address is recorded in the TLB, ensure that the VPN [n:12] is the same. 3. Do not use the same physical addresses for address translation information of different page sizes. The above restrictions apply only when performing accesses using the cache. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to 10 are the same. Rev. 1.00 Dec. 27, 2005 Page 203 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) * When Using a 4-kbyte Page Virtual Address 31 VPN 13 12 11 10 0 Offset Physical Address 28 PPN 13 12 11 10 Virtual Address 12 to 4 0 Offset Cache Physical Address 28 to 10 * When Using a 1-kbyte Page Virtual Address 31 VPN 13 12 11 10 0 Offset Physical Address 28 PPN 13 12 11 10 Virtual Address 12 to 4 0 Offset Cache Physical Address 28 to 10 Figure 5.12 Synonym Problem (32-kbyte Cache) Rev. 1.00 Dec. 27, 2005 Page 204 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.5 MMU Exceptions When the address translation unit of the MMU is enabled, occurrence of the MMU exception is checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write, and these MMU exceptions are checked in this order. 5.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception processing includes both hardware and software operations. Hardware Operations: In a TLB miss, this hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter (SPC). If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The MD bit in SR is set to 1 to place the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries indexed are valid. When some entries indexed are invalid, the smallest way number of them is set in RC. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000400 to invoke the user-written TLB miss exception handler. Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: Rev. 1.00 Dec. 27, 2005 Page 205 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 1. Write the value of the physical page number (PPN) field and the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the address translation table in the external memory into the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. 5.5.2 TLB Protection Violation Exception A TLB protection violation exception results when the virtual address and the address array of the selected TLB entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the PR field. TLB protection violation exception processing includes both hardware and software operations. Hardware Operations: In a TLB protection violation exception, this hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written into SPC (if the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written into SPC). 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The way that generated the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the TLB protection violation exception handler. Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Issue the RTE instruction after issuing two instructions from the LDTLB instruction. Rev. 1.00 Dec. 27, 2005 Page 206 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.5.3 TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception processing includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, this hardware executes a set of prescribed operations, as follows: 1. The VPN number of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written into SSR. 6. The mode (MD) bit in SR is set to 1 to place the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The way number causing the exception is written to RC in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100, and the TLB protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: The software searches the page tables in external memory and assigns the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the values of the physical page number (PPN) field and the values of the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the external memory to the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Rev. 1.00 Dec. 27, 2005 Page 207 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception processing includes both hardware and software operations. Hardware Operations: In an initial page write exception, this hardware executes a set of prescribed operations, as follows: 1. 2. 3. 4. The VPN field of the virtual address causing the exception is written to the PTEH register. The virtual address causing the exception is written to the TEA register. Exception code H'080 is written to the EXPEVT register. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The way that caused the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: The software must execute the following operations: 1. Retrieve the required page table entry from external memory. 2. Set the D bit of the page table entry in the external memory to 1. 3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in the external memory to the PTEL register. 4. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction must be issued after two LDTLB instructions. Rev. 1.00 Dec. 27, 2005 Page 208 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.5.5 MMU Exception in Repeat Loop If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to H'070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU address error and to H'0D0 for a TLB protection violation exception. In addition, a vector offset for TLB miss exception is H'100. For details, refer to section 4.4.3,Exception in Repeat Control Period. Rev. 1.00 Dec. 27, 2005 Page 209 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Start Yes Address error? CPU address error No No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? Yes No VPNs Match? No Yes VPNs and ASIDs Match? Yes V=1? No TLB Invalid Exception TLB Miss Exception User Mode Yes User or Privileged? Privileged Mode PR? 00/01 W 10 R/W? R 11 R/W? R No D=1? W W 01/11 R/W? R PR? 00/10 R/W? R W Yes TLB Protection Violation Exception TLB Protection Violation Exception Initial page Write Exception No (Non-Cacheable) Memory Access C=1? Yes (Cacheable) Cache Access Figure 5.13 MMU Exception Generation Flowchart Rev. 1.00 Dec. 27, 2005 Page 210 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.6 Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only longword access is possible for both the address array and the data array. However, the instruction data cannot be fetched from both arrays. 5.6.1 Address Array The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the 32bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the VPN, V bit and ASID to be written to the address array (figure 5.14 (1)). In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for selecting the way (bits 9 to 8) and H'F2 to indicate address array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. The following two operations can be used on the address array: 1. Address array read VPN, V, and ASID are read from the TLB entry corresponding to the entry address and way set in the address field. 2. TLB address array write The data specified in the data field are written to the TLB entry corresponding to the entry address and way set in the address field. 5.6.2 Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. The address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 5.14 (2)). In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for selecting the way (bits 9 to 8), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. Rev. 1.00 Dec. 27, 2005 Page 211 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Both reading and writing use the longword of the data array specified by the entry address and way number. The access size of the data array is fixed at longword. (1) TLB Address Array Access * Read Access 31 24 23 17 16 12 1110 9 8 7 6 210 *............* VPN * * W 0 * . . . . . . . . . * 00 17 16 VPN 12 1110 9 8 7 ASID 0 Address Field 11110010 31 Data Field 0 . . . . . . . 0 VPN 0 V * Write Access 31 Address Field 11110010 31 24 23 17 16 12 11 10 9 8 7 6 210 *............* VPN * * W 0 * . . . . . . . . . * 00 17 16 12 11 10 9 8 7 * . . . . . . . * VPN * V 0 ASID Data Field VPN: V: W: ASID: *: (2) TLB Data Array Access * Read/Write Access 31 Address Field VPN Virtual Page Number Valid Bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) Address Space Identifier Don't Care Bit 11110011 31 29 28 24 23 17 16 12 1110 9 8 7 210 *............* VPN * * W * . . . . . . . . . . . * 00 10 9 8 7 6 5 4 3 2 1 0 PPN X V X PR SZ C D SH X Data Field 000 PPN: PR: C: SH: VPN: X: W: V: SZ: D: *: Physical Page Number Protection Key Field Cacheable Bit Share Status Bit Virtual Page Number 0 for Read, Don't Care Bit for Write Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) Valid Bit Page-Size Bit Dirty bit Don't Care Bit Figure 5.14 Specifying Address and Data for Memory-Mapped TLB Access Rev. 1.00 Dec. 27, 2005 Page 212 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) 5.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C ; MMUCR.IX=0 ; the V bit of way 0 of the entry selected by the VPN(16-12)=B'1 0011 ; index is cleared to0,achieving invalidation. MOV.L R0,@R1 R1=H'F201 3000 Reading the Data of a Specific Entry: This example reads the data section of a specific TLB entry. The bit order indicated in the data field in figure 5.14 (2) is read. R0 specifies the address and the data section of a selected entry is read to R1. ; R0=H'F300 4300 ; MOV.L @R0,R1 VPN(16-12)=B'00100 Way 3 5.7 Usage Note The following operations should be performed in the P1 or P2 areas. In addition, when the P0, P3, or U0 areas are accessed consecutively (this access includes instruction fetching), the instruction code should be placed at least two instructions after the instruction that executes the following operations. 1. 2. 3. 4. 5. Modification of SR.MD or SR.BL Execution of the LDTLB instruction Write to the memory-mapped TLB Modification of MMUCR Modification of PTEH.ASID Rev. 1.00 Dec. 27, 2005 Page 213 of 932 REJ09B0269-0100 Section 5 Memory Management Unit (MMU) Rev. 1.00 Dec. 27, 2005 Page 214 of 932 REJ09B0269-0100 Section 6 Cache Section 6 Cache 6.1 * * * * * * * Features Capacity: 16 or 32 kbytes Structure: Instructions/data mixed, 4-way set associative Locking: Way 2 and way 3 are lockable Line size: 16 bytes Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0 Replacement method: Least-recently used (LRU) algorithm Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way). 6.1.1 Cache Structure The cache mixes instructions and data and uses a 4-way set associative system. It is composed of four ways (banks), and each of which is divided into an address section and a data section. Each of the address and data sections is divided into 512 entries. The entry data is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 8 kbytes (16 bytes x 512 entries) in the cache as a whole (4 ways). The cache capacity is 32 kbytes as a whole. Figure 6.1 shows the cache structure. Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 V U Tag address Entry 1 . . . . . . 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 511 511 511 24 (1 + 1 + 22) bits 128 (32 x 4) bits LW0 to LW3: Longword data 0 to 3 6 bits Figure 6.1 Cache Structure Rev. 1.00 Dec. 27, 2005 Page 215 of 932 REJ09B0269-0100 Section 6 Cache Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31-10) used for comparison during cache searches. In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 12, Bus State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way. Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 6.1 shows the relationship between the LRU bits and the way to be replaced when the cache locking mechanism is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section 6.2.2, Cache Control Register 2 (CCR2).) If a bit pattern other than those listed in table 6.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 6.1. The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 6.1 LRU and Way Replacement (when Cache Locking Mechanism is Disabled) Way to be Replaced 3 2 1 0 LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00 Dec. 27, 2005 Page 216 of 932 REJ09B0269-0100 Section 6 Cache 6.2 Register Descriptions The cache has the following registers. For details on register addresses and register states during each process, refer to section 23, List of Registers. * Cache control register 1 (CCR1) * Cache control register 2 (CCR2) * Cache control register 3 (CCR3) 6.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which invalidates all cache entries), and WT and CB bits (which select either write-through mode or write-back mode). Programs that change the contents of the CCR1 register should be placed in address space that is not cached. Bit 31 to 4 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 CF 0 R/W Cache Flush Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). This bit is always read as 0. Write-back to external memory is not performed when the cache is flushed. 2 CB 0 R/W Write-Back Indicates the cache's operating mode for space P1. 0: Write-through mode 1: Write-back mode 1 WT 0 R/W Write-Through Indicates the cache's operating mode for spaces P0, U0, and P3. 0: Write-back mode 1: Write-through mode Rev. 1.00 Dec. 27, 2005 Page 217 of 932 REJ09B0269-0100 Section 6 Cache Bit 0 Bit Name CE Initial Value 0 R/W R/W Description Cache Enable Indicates whether the cache function is used. 0: The cache function is not used. 1: The cache function is used. 6.2.2 Cache Control Register 2 (CCR2) The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU enters the cache lock mode when the DSP bit (bit 12) in the status register (SR) is set to 1 or the lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1. The cache locking mechanism is disabled in non-cache lock mode (DSP bit = 0). When a prefetch instruction (PREF@Rn) is issued in cache lock mode and a cache miss occurs, the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9 and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2). Table 6.2 shows the relationship between the settings of bits and the way that is to be replaced when the cache is missed by a prefetch instruction. On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the cache and the valid entry is held. For example, a prefetch instruction is issued while bits W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0, the cache is hit and new data is not loaded into way 3. In cache lock mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when instructions other than the prefetch instruction are issued. Table 6.3 shows the relationship between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed by instructions other than the prefetch instruction. Programs that change the contents of the CCR2 register should be placed in address space that is not cached. Rev. 1.00 Dec. 27, 2005 Page 218 of 932 REJ09B0269-0100 Section 6 Cache Bit 31 to 17 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock enable (LE) Controls cache lock mode. 0: Enters cache lock mode when the DSP bit of the SR register is set to 1. 1: Enters cache lock mode regardless of the DSP bit value. 15 to 10 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 W3LOAD W3LOCK 0 0 R/W R/W Way 3 Load (W3LOAD) Way 3 Lock (W3LOCK) When the cache is missed by a prefetch instruction while in cache lock mode and when bits W3LOAD and W3LOCK in CCR2 are set to 1, the data is always loaded into way 3. Under any other condition, the prefetched data is loaded into the way to which LRU points. 7 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 W2LOAD W2LOCK 0 0 R/W R/W Way 2 Load (W2LOAD) Way 2 Lock (W2LOCK) When the cache is missed by a prefetch instruction while in cache lock mode and when bits W2LOAD and W2LOCK in CCR2 are set to 1, the data is always loaded into way 2. Under any other condition, the prefetched data is loaded into the way to which LRU points. Note: W2LOAD and W3LOAD should not be set to 1 at the same time. Rev. 1.00 Dec. 27, 2005 Page 219 of 932 REJ09B0269-0100 Section 6 Cache Table 6.2 DSP Bit 0 1 1 1 1 1 1 Note: Way Replacement when a PREF Instruction Misses the Cache W3LOAD * * * 0 0 0 1 W3LOCK * 0 0 1 1 * 1 W2LOAD * * 0 * 0 1 0 W2LOCK * 0 1 0 1 1 * Way to be Replaced Determined by LRU (table 6.1) Determined by LRU (table 6.1) Determined by LRU (table 6.4) Determined by LRU (table 6.5) Determined by LRU (table 6.6) Way 2 Way 3 * Don't care W3LOAD and W2LOAD should not be set to 1 at the same time. Table 6.3 DSP Bit 0 1 1 1 1 Note: Way Replacement when Instructions other than the PREF Instruction Miss the Cache W3LOAD * * * * * W3LOCK * 0 0 1 1 W2LOAD * * * * * W2LOCK * 0 1 0 1 Way to be Replaced Determined by LRU (table 6.1) Determined by LRU (table 6.1) Determined by LRU (table 6.4) Determined by LRU (table 6.5) Determined by LRU (table 6.6) * Don't care W3LOAD and W2LOAD should not be set to 1 at the same time. Table 6.4 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0) Way to be Replaced 3 1 0 LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00 Dec. 27, 2005 Page 220 of 932 REJ09B0269-0100 Section 6 Cache Table 6.5 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1) Way to be Replaced 2 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 6.6 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1) Way to be Replaced 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 6.2.3 Cache Control Register 3 (CCR3) The CCR3 register controls the cache size to be used. The cache size must be specified according to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the CCR3 register should be placed in un-cached address space. In addition, note that all cache entries must be invalidated by setting the CF bit of the CCR1 to 1 before accessing the cache after the CCR3 is modified. Bit 31 to 24 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 CSIZE7 to H'01 CSIZE0 R/W Cache Size Specify the cache size as shown below. 0000 0001: 16-kbyte cache 0000 0010: 32-kbyte cache Settings other than above are prohibited. 15 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 221 of 932 REJ09B0269-0100 Section 6 Cache 6.3 6.3.1 Operation Searching the Cache If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1, P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 6.2 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 12 to 4 of the address (virtual) of the access to memory and the tag address of that entry is read. The virtual address (bits 31 to 10) of the access to memory and the physical address (tag address) read from the address array are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 6.2 shows a hit on way 1. Rev. 1.00 Dec. 27, 2005 Page 222 of 932 REJ09B0269-0100 Section 6 Cache Virtual address 31 13 12 4 3 210 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 MMU 0 1 V U Tag address LW0 LW1 LW2 LW3 511 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 6.2 Cache Search Scheme 6.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU is updated to indicate that the hit way is the most recently hit way. Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 6.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cacheupdate cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. Rev. 1.00 Dec. 27, 2005 Page 223 of 932 REJ09B0269-0100 Section 6 Cache 6.3.3 Prefetch Operation Prefetch Hit: The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of the cache are not changed. Instructions and data are not transferred from the cache to the CPU. Prefetch Miss: Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced is shown in table 6.2. The other operations are the same as those for a read miss. 6.3.4 Write Access Write Hit: In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the entry that has been written to is not updated, and the LRU is updated to indicate that the hit way is the most recently hit way. Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is shown in table 6.3. When the U bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The LRU is updated to indicate that the replaced way is the most recently updated way. After the cache has completed its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 6.3.5 Write-Back Buffer When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the fetching of new entries to the cache completes, the write-back buffer writes the entry back to the external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 6.3 shows the configuration of the write-back buffer. Rev. 1.00 Dec. 27, 2005 Page 224 of 932 REJ09B0269-0100 Section 6 Cache PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4): Physical address written to external memory Longword 0 to 3: One line of cache data to be written to external memory Figure 6.3 Write-Back Buffer Configuration 6.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. Memory that is shared by this LSI's CPU and DMAC should also be handled in this way. Rev. 1.00 Dec. 27, 2005 Page 225 of 932 REJ09B0269-0100 Section 6 Cache 6.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 6.4.1 Address Array The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array. In the address field, specify the entry address for selecting the entry, W for selecting the way, A for enabling or disabling the associative operation, and H'F0 for indicating address array access. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3). In the data field, specify the tag address, LRU bits, U bit, and V bit. Figures 6.4 and 6.5 show the address and data formats. The following three operations are available in the address array. Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address and way specified by the address field of the read instruction. In reading, the associative operation is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0. Address-Array Write (non-Associative Operation): Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is written to the V bit, 0 must also be written to the U bit for that entry. Address-Array Write (Associative Operation): When writing with the associative bit (A bit) of the address = 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag address that is specified by the data field of the write instruction. If the MMU is enabled in this case, a logical address specified by data is translated into a physical address via the TLB before comparison. Write the U bit and the V bit specified by the data field of the write instruction to the entry of the way that has a hit. However, the tag Rev. 1.00 Dec. 27, 2005 Page 226 of 932 REJ09B0269-0100 Section 6 Cache address and LRU bits remain unchanged. When there is no way that receives a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has received a hit is 1 at this point, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 6.4.2 Data Array The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. In the address field, specify the entry address for selecting the entry, L for indicating the longword position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2, and 11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be set to 00. Figures 6.4 and 6.5 show the address and data formats. The following two operations on the data array are available. The information in the address array is not affected by these operations. Data-Array Read: Read the data specified by L of the address filed, from the entry that corresponds to the entry address and the way that is specified by the address filed. Data-Array Write: Write the longword data specified by the data filed, to the position specified by L of the address field, in the entry that corresponds to the entry address and the way specified by the address field. Rev. 1.00 Dec. 27, 2005 Page 227 of 932 REJ09B0269-0100 Section 6 Cache (1) Address array access (a) Address specification Read access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 Write access 31 24 23 *--------* W Entry address 0 * 0 0 14 13 12 11 4 3 2 0 1111 0000 *--------* W Entry address A * 0 0 (b) Data specification (both read and write accesses) 31 10 9 4 3 2 1 0 Tag address (31 to 10) LRU X X U V (2) Data array access (both read and write accesses) (a) Address specification 31 24 23 14 13 12 11 4 3 2 1 0 1111 0001 (b) Data specification 31 *--------* W Entry address L 0 0 0 Longword *: Don't care bit X: 0 for read, don't care for write Figure 6.4 Specifying Address and Data for Memory-Mapped Cache Access (16 kbytes mode) Rev. 1.00 Dec. 27, 2005 Page 228 of 932 REJ09B0269-0100 Section 6 Cache (1) Address array access (a) Address specification Read access 31 24 23 15 14 13 12 4 3 2 0 1111 0000 Write access 31 24 23 *--------* W Entry address 0 * 0 0 15 14 13 12 4 3 2 0 1111 0000 *--------* W Entry address A * 0 0 (b) Data specification (both read and write accesses) 31 30 29 28 10 9 4 3 2 1 0 0 0 0 Tag address (28 to 10) LRU X X U V (2) Data array access (both read and write accesses) (a) Address specification 31 24 23 15 14 13 12 4 3 2 1 0 1111 0001 (b) Data specification 31 *--------* W Entry address L 0 0 0 Longword *: Don't care bit X: 0 for read, don't care for write Figure 6.5 Specifying Address and Data for Memory-Mapped Cache Access (32 kbytes mode) Rev. 1.00 Dec. 27, 2005 Page 229 of 932 REJ09B0269-0100 Section 6 Cache 6.4.3 Usage Examples Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and a match is found, the entry is written back if the entry's U bit is 1 and the V bit and U bit specified by the write data are written. If no match is found, there is no operation. In the example shown below, R0 specifies the write data and R1 specifies the address. ; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F0000088; address array access, entry=B'00001000, A=1 ; MOV.L R0,@R1 Reading the Data of a Specific Entry: To read the data field of a specific entry is enabled by the memory-mapped cache access. The longword indicated in the data field of the data array in figure 6.4 or 6.5 is read into the register. In the example shown below, R0 specifies the address and R1 shows what is read. ; R0=H'F100 004C; data array access, entry=B'00000100 ; Way = 0, longword address = 3 ; MOV.L @R0,R1 ; Longword 3 is read. Rev. 1.00 Dec. 27, 2005 Page 230 of 932 REJ09B0269-0100 Section 7 X/Y Memory Section 7 X/Y Memory This LSI has on-chip X-memory and Y-memory which can be used to store instructions or data. 7.1 Features * Page There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y memory is divided into two pages (pages 0 and 1). * Memory map The X/Y memory is located in the logical address space, physical address space, and X-bus and Y-bus address spaces. In the logical address space, this memory is located in the addresses shown in table 7.1. These addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP = 1) according to the CPU operating mode. Table 7.1 X/Y Memory Logical Addresses Memory Size (Total Four Pages) Page Page 0 of X memory Page 1 of X memory Page 0 of Y memory Page 1 of Y memory 16 kbytes HA5007000 to HA5007FFF HA5008000 to HA5008FFF HA5017000 to HA5017FFF HA5018000 to HA5018FFF On the other hand, this memory is located in a part of area 1 in the physical address space. When this memory is accessed from the physical address space, addresses in which the upper three bits are 0 in addresses shown in table 7.1 are used. In the X-bus and Y-bus address spaces, addresses in which the upper 16 bits are ignored in addresses of X memory and Y memory shown in table 7.1 are used. * Ports Each page has three independent read/write ports and is connected to each bus. The X memory is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus, and L bus. The L bus is used when this memory is accessed from the logical address space. The I bus is used when this memory is accessed from the physical address space. The X bus and Y bus are used when this memory is accessed from the X-bus and Y-bus address spaces. Rev. 1.00 Dec. 27, 2005 Page 231 of 932 REJ09B0269-0100 Section 7 X/Y Memory * Priority order In the event of simultaneous accesses to the same page from different buses, the accesses are processed according to the priority order. The priority order is: I bus > X bus > L bus in the X memory and I bus > Y bus > L bus in the Y memory. 7.2 7.2.1 Operation Access from CPU Methods for accessing by the CPU are directly via the L bus from the logical addresses, and via the I bus after the logical addresses are converted to be the physical addresses using the MMU. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Privileged mode and privileged DSP mode (SR. MD = 1): The X/Y memory can be accessed by the CPU directly from space P2. The MMU can be used to map the logical addresses in spaces P0 and P3 to this memory. User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the CPU directly from space Uxy. The MMU can be used to map the logical addresses in space U0 to this memory. User mode (SR.MD = 0 and SR.DSP = 0): The MMU can be used to map the logical addresses in space U0 to this memory. 7.2.2 Access from DSP Methods for accessing from the DSP differ according to instructions. With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory access via the Y bus can be performed simultaneously. In the case of a single data transfer instruction, methods for accessing from the DSP are directly via the L bus from the logical addresses, and via the I bus after the logical addresses are converted to be the physical addresses using the MMU. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Rev. 1.00 Dec. 27, 2005 Page 232 of 932 REJ09B0269-0100 Section 7 X/Y Memory Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The X/Y memory can be accessed by the DSP directly from space P2. The MMU can be used to map the logical addresses in spaces P0 and P3 to this memory. User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the DSP directly from space Uxy. The MMU can be used to map the logical addresses in space U0 to this memory. 7.2.3 Access from DMAC and E-DMAC The X/Y memory is always accessed by the DMAC and E-DMAC via the I bus, which is a physical address bus. Addresses in which the upper three bits are 0 in addresses shown in table 7.1 must be used. 7.3 7.3.1 Usage Notes Page Conflict In the event of simultaneous accesses to the same page from different buses, the conflict on the pages occurs. Although each access is completed correctly, this kind of conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, conflict will not arise if different memory or different pages are accessed by each bus. 7.3.2 Bus Conflict The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be prevented. 7.3.3 MMU and Cache Settings When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled (CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory Rev. 1.00 Dec. 27, 2005 Page 233 of 932 REJ09B0269-0100 Section 7 X/Y Memory via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus, several cycles are necessary (the number of necessary cycles varies according to the ratio between the internal clock (I) and bus clock (B) or the operation state of the DMAC and E-DMAC). In a program that requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The relationship described above is summarized in table 7.2. Table 7.2 MMU and Cache Settings Setting CCR1.CE 0 0 1 1 [Legend] A: B: C: X: MMUCR.AT 0 1 0 1 Logical Address Space and Access Enabled or Disabled P0, U0 B B X C P1 B B X X P2, Uxy A A A A P3 B B X C Accessible (recommended) Accessible Accessible (Note that MMU page attribute must be specified as cache disabled by clearing the C bit to 0.) Not Accessible 7.3.4 Sleep Mode In sleep mode, I bus master modules such as the DMAC and E-DMAC cannot access the X/Y memory. 7.3.5 Address Error If writing that may causes an address error is performed on the X/Y memory, the contents of the X/Y memory are not guaranteed. Rev. 1.00 Dec. 27, 2005 Page 234 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Section 8 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 8.1 Features The INTC has the following features: * 16 levels of interrupt priority can be set By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ interrupts can be selected from 16 levels for individual request sources. * NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. * IRQ interrupts can be set Detection of low level, rising edge, falling edge, or high level * Interrupt request signal can be externally output (IRQOUT pin) The bus mastership can be requested by notifying the external bus master that the external interrupt and on-chip peripheral module interrupt requests have been generated. 8.1.1 Block Diagram Figure 8.1 shows a block diagram of the INTC. Rev. 1.00 Dec. 27, 2005 Page 235 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) IRQOUT NMI IRL3 to IRL0 IRQ5 to IRQ0 4 Input/output control Interrupt request SR I3 I2 I1 I0 8 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) DMAC SCIF0/1 E-DMAC SIOF0/1 TMU RTC WDT REF H-UDI Comparator Priority identifier CPU ICRn IPRn IRRn Internal bus Bus interface Interrupt controller [Legend] DMAC: SCIF0/1: E-DMAC: SIOF0/1: TMU: RTC: WDT: REF: H-UDI: ICRn: IPRn: IRRn: SR: Direct memory access controller Serial communication interface with FIFO Direct memory access controller for ethernet controller Serial I/O with FIFO Timer unit Realtime clock unit Watchdog timer Refresh request in bus state controller User-debugging interface Interrupt control registers 0, 1 Interrupt priority registers A to I Interrupt request registers 0 to 5, 7 and 8 Status register Figure 8.1 Block Diagram of INTC Rev. 1.00 Dec. 27, 2005 Page 236 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.2 Input/Output Pins Table 8.1 shows the INTC pin configuration. Table 8.1 Name Nonmaskable interrupt input pin Pin Configuration Abbreviation NMI I/O Input Description Input of interrupt request signal, not maskable by the interrupt mask bits in SR Input of interrupt request signals Interrupt input pins Bus mastership request output 2 pin* IRQ5 to IRQ0 IRL3 to IRL0* IRQOUT 1 Input Output Notifies that an interrupt request has generated Notes: 1. The IRL3 to IRL0 pins and the IRQ3 to IRQ0 cannot be used simultaneously because these pins are multiplexed with the IRQ3 to IRQ0 pins. 2. When the NMI or H-UDI interrupt requests are generated and the response time of the CPU is short, this pin may not be asserted. 8.3 Interrupt Sources There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 8.3.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt control register 1 (ICR1) is set to 1 or the BL bit in the status register (SR) is 0 and the MAI bit in ICR1 is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either rising or falling edge detection. When using edge-input detection for NMI interrupts, a pulse width of at least two P cycles (peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR). When the BL bit is 1 and the BLMSK bit in ICR1 is set to 1, only the NMI interrupt is accepted. It is possible to wake the chip up from sleep mode or standby mode with the NMI interrupt. Rev. 1.00 Dec. 27, 2005 Page 237 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.3.2 IRQ Interrupts IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5. The priority level can be set by interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. When ICR1 is rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0). Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock basis. When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt handling. IRQ interrupts can be used for recovering from standby when the corresponding interrupt level is higher than that of bits I3 to I0 in SR. (However, only when the RTC is used, recovering from standby by using the clock for the RTC is enabled.) 8.3.3 IRL Interrupts IRL interrupts are input by the IRL3 to IRL0 pins as level. The priority level is the higher level that is indicated by the IRL3 to IRL0 pins. When the values of the IRL3 to IRL0 pins are 0 (B0000), the highest level interrupt request (interrupt priority level 15) is indicated. When the values of the pins are 15 (B1111), no interrupt is requested (interrupt priority level 0). Figure 8.2 shows an example of connection for an IRL interrupt. Table 8.3 lists the IRL pins and interrupt level. IRL interrupts are included with a noise canceler function and detected when the sampled levels of each peripheral module clock keep the same value for 2 cycles. This prevents sampling error level in IRL pin changing. In standby mode, a noise canceler is handled by the RTC clock (32 kHz) because the peripheral module clocks are halted. Therefore, when the RTC is not used, recovering from standby by IRL interrupts cannot be executed in standby mode. The priority level of IRL interrupts should be kept until an interrupt is accepted and its handling is started. However, changing to higher level is enabled. Rev. 1.00 Dec. 27, 2005 Page 238 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by the IRL interrupt handling. SH7712 Interrupt request Priority encoder 4 IRL3 to IRL0 IRL3 to IRL0 Figure 8.2 Example of IRL Interrupt Connection 8.3.4 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following 14 modules: * Direct memory access controller (DMAC) * Serial communication interface with FIFO (SCIF0 and SCIF1) * Direct memory access controller for ethernet controller (E-DMAC) (includes an EtherC interrupt) * Serial I/O with FIFO (SIOF0 and SIOF1) * Timer unit (TMU0 to TMU2) * Realtime clock (RTC) * Watchdog timer (WDT) * Bus state controller (BSC) * User-debugging interface (H-UDI) Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value of INTEVT or INTEVT2 as a branch offset. A priority level (from 0 to 15) can be set for each module except the H-UDI by writing to the interrupt priority registers A, B, and E to I (IPRA, IPRB, and IPRE to IPRI). The priority level of the H-UDI interrupt is 15 (fixed). Rev. 1.00 Dec. 27, 2005 Page 239 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral module interrupt handling. 8.3.5 Interrupt Exception Handling and Priority There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. Tables 8.2 and 8.3 list the codes for the interrupt event registers (INTEVT and INTEVT2) and the order of interrupt priority. Each interrupt source is assigned a unique code by INTEVT or INTEVT2. The start address of the interrupt service routine is common for each interrupt source. This is why, for instance, the value of INTEVT or INTEVT2 is used as an offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt priority registers A to I (IPRA to IPRI). A reset assigns priority level 0 to IRQ and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in tables 8.2 and 8.3. Table 8.2 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 16 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRC (3 to 0) IPRC (7 to 4) IPRC (11 to 8) Low High Interrupt Source NMI H-UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Interrupt Code*1 H1C0*2 H5E0* H600* H620* H640* H660* 2 3 3 3 3 IPRC (15 to 12) IPRD (3 to 0) IPRD (7 to 4) H680*3 H6A0* 3 Rev. 1.00 Dec. 27, 2005 Page 240 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Interrupt Source DMAC (1) DEI0 DEI1 DEI2 DEI3 SCIF0 ERI0 RXI0 BRI0 TXI0 SCIF1 ERI1 RXI1 BRI1 TXI1 DMAC (2) DEI4 DEI5 Interrupt Code H800* H820* 3 3 Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRE (11 to 8) Low High IPRE (15 to12) High High H840*3 H860* H880* 3 3 H8A0* 3 H8C0*3 H8E0* H900* H920* 3 Low 0 to 15 (0) IPRE (7 to 4) High 3 3 H940*3 H960* 3 Low 0 to 15 (0) IPRF (11 to 8) High Low 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRG (15 to 12) IPRG (11 to 8) IPRG (7 to 4) IPRH (3 to 0) High HB80* 3 HBA0* HC00* HC20* HC40* HE00* 3 E-DMAC EINT0 EINT1 EINT2 SIOF0 ERI0 TXI0 RXI0 CCI0 SIOF1 ERI1 TXI1 RXI1 CCI1 TMU0 TMU1 TMU2 TUNI0 TUNI1 TUNI2 3 3 3 3 HE20*3 HE40*3 HE60* HE80* 3 Low 0 to 15 (0) IPRI (7 to 4) High 3 HEA0* 3 HEC0*3 HEE0* H400* 3 Low 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRA (15 to 12) IPRA (11 to 8) IPRA (7 to 4) Low 2 H420*2 H440* 2 Rev. 1.00 Dec. 27, 2005 Page 241 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Interrupt Source RTC ATI PRI CUI WDT REF ITI RCMI Interrupt Code H480* 2 2 Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 0 to 15 (0) IPRA (3 to 0) High Low 0 to 15 (0) 0 to 15 (0) IPRB (15 to 12) IPRB (11 to 8) Low High H4A0* H4C0*2 H560* H580* 2 2 Notes: 1. INTEVT2 code 2. The code set in INTEVT is as same as INTEVT2. 3. The code that indicates the interrupt level (H200 to H3C0) is set in INTEVT. For details on correspondence between the interrupt level and INTEVT, see table 8.4. Rev. 1.00 Dec. 27, 2005 Page 242 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Table 8.3 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt 1 Code* H1C0* H5E0* 2 2 Interrupt Source NMI H-UDI Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 16 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to 15 (0) 0 to 15 (0) IPRD (3 to 0) IPRD (7 to 4) Low High IRL IRL[3:0] = B0000 H200* IRL[3:0] = B0001 H220* 3 3 IRL[3:0] = B0010 H240*3 IRL[3:0] = B0011 H260* IRL[3:0] = B0100 H280* 3 3 IRL[3:0] = B0101 H2A0* 3 IRL[3:0] = B0110 H2C0* IRL[3:0] = B0111 H2E0* IRL[3:0] = B1000 H300* IRL[3:0] = B1001 H320* 3 3 3 3 IRL[3:0] = B1010 H340*3 IRL[3:0] = B1011 H360* IRL[3:0] = B1100 H380* 3 3 IRL[3:0] = B1101 H3A0* 3 IRL[3:0] = B1110 H3C0* IRQ IRQ4 IRQ5 H680* 3 3 H6A0* 3 Rev. 1.00 Dec. 27, 2005 Page 243 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Interrupt Source DMAC (1) DEI0 DEI1 DEI2 DEI3 SCIF0 ERI0 RXI0 BRI0 TXI0 SCIF1 ERI1 RXI1 BRI1 TXI1 DMAC (2) DEI4 DEI5 Interrupt Code H800* H820* 3 3 Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRE (11 to 8) Low High IPRE (15 to12) High High H840*3 H860* H880* 3 3 H8A0* 3 H8C0*3 H8E0* H900* H920* 3 Low 0 to 15 (0) IPRE (7 to 4) High 3 3 H940*3 H960* 3 Low 0 to 15 (0) IPRF (11 to 8) High Low 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRG (15 to 12) IPRG (11 to 8) IPRG (7 to 4) IPRH (3 to 0) High HB80* 3 HBA0* HC00* HC20* HC40* HE00* 3 E-DMAC EINT0 EINT1 EINT2 SIOF0 ERI0 TXI0 RXI0 CCI0 SIOF1 ERI1 TXI1 RXI1 CCI1 TMU0 TMU1 TMU2 TUNI0 TUNI1 TUNI2 3 3 3 3 HE20*3 HE40*3 HE60* HE80* 3 Low 0 to 15 (0) IPRI (7 to 4) High 3 HEA0* 3 HEC0*3 HEE0* H400* 3 Low 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRA (15 to 12) IPRA (11 to 8) IPRA (7 to 4) Low 2 H420*2 H440* 2 Rev. 1.00 Dec. 27, 2005 Page 244 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Interrupt Source RTC ATI PRI CUI WDT REF ITI RCMI Interrupt Code H480* 2 2 Interrupt Priority Priority IPR within IPR Default (Initial Value) (Bit Numbers) Setting Unit Priority 0 to 15 (0) IPRA (3 to 0) High High H4A0* H4C0*2 H560* H580* 2 Low 0 to 15 (0) 0 to 15 (0) IPRB (15 to 12) IPRB (11 to 8) Low 2 Notes: 1. INTEVT2 code 2. The code set in INTEVT is as same as INTEVT2. 3. The code that indicates the interrupt level (H200 to H3C0) is set in INTEVT. For details on correspondence between the interrupt level and INTEVT, see table 8.4. Table 8.4 Interrupt Level and INTEVT Code INTEVT Code H200 H220 H240 H260 H280 H2A0 H2C0 H2E0 H300 H320 H340 H360 H380 H3A0 H3C0 Interrupt Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rev. 1.00 Dec. 27, 2005 Page 245 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.4 Register Descriptions The INTC has the following registers. For details on register addresses and register access size, refer to section 23, List of Registers. * * * * * * * * * * * * * * * * * * * Interrupt control register 0 (ICR0) Interrupt control register 1 (ICR1) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt request register 0 (IRR0) Interrupt request register 1 (IRR1) Interrupt request register 2 (IRR2) Interrupt request register 3 (IRR3) Interrupt request register 4 (IRR4) Interrupt request register 5 (IRR5) Interrupt request register 7 (IRR7) Interrupt request register 8 (IRR8) Interrupt Priority Registers A to I (IPRA to IPRI) 8.4.1 IPRA to IPRI are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and IRQ interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode. Rev. 1.00 Dec. 27, 2005 Page 246 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 8.5, Interrupt Sources and IPRA to IPRI. Table 8.5 Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI Note: * Interrupt Sources and IPRA to IPRI Bits 15 to 12 TMU0 WDT IRQ3 Reserved* DMAC (1) Reserved* E-DMAC (1) Reserved* Reserved* Bits 11 to 8 TMU1 REF IRQ2 Reserved* SCIF0 DMAC (2) E-DMAC (2) Reserved* Reserved* Bits 7 to 4 TMU2 Reserved* IRQ1 IRQ5 SCIF1 Reserved* E-DMAC (3) Reserved* SIOF1 Bits 3 to 0 RTC Reserved* IRQ0 IRQ4 Reserved* Reserved* Reserved* SIOF0 Reserved* Always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 247 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) As shown in table 8.5, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F means priority level 15 (the highest level). 8.4.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 15 Bit Name NMIL Initial Value 0/1* R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. This bit can be read from to determine the NMI pin level. This bit cannot be modified. 0 : NMI input level is low 1 : NMI input level is high 14 13 12 11 10 9 8 NMIE 0 0 0 0 0 0 0 R R R R R R R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal at the NMI pin is detected. 0 : Interrupt request is detected on falling edge of NMI pin input 1 : Interrupt request is detected on rising edge of NMI pin input Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 248 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 7 6 5 4 3 2 1 0 Note: * Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Reserved These bits are always read as 0. The write value should always be 0. when NMI input is high, 0 when NMI input is low. 8.4.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, high level, or low level. This register is initialized to H4000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 15 Bit Name MAI Initial Value 0 R/W R/W Description All Interrupt Mask When this bit is set to 1, all interrupt requests are masked while low level is input to the NMI pin. In standby mode, an NMI interrupt is masked. 0: When the NMI pin is low, all interrupt requests are not masked 1: When the NMI pin is low, all interrupt requests are masked 14 IRQLVL 1 R/W Interrupt Request Level Detection Enables or disables the use of pins IRQ3 to IRQ0 as four independent interrupt pins. The IRQ4 and IRQ5 pins are not affected. 0 : Use of pins IRQ3 to IRQ0 as four independent interrupt pins enabled 1 : Use of pins IRL3 to IRL0 as encoded 15 level interrupt pins Rev. 1.00 Dec. 27, 2005 Page 249 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 13 Bit Name BLMSK Initial Value 0 R/W R/W Description BL Bit Mask When the BL bit in SR is set to 1, this bit specifies whether an NMI interrupt is masked or not. 0: When the BL bit is set to 1, an NMI interrupt is masked 1: An NMI interrupt is accepted regardless of the BL bit setting 12 0 R Reserved This bit is always read as 0. The write value should always be 0. 11 10 9 8 7 6 5 4 3 2 1 0 IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IRQn Sense Select These bits select whether interrupt request signals corresponding to pins IRQ5 to IRQ0 are detected by a rising edge, falling edge, high level, or low level. Bit 2n+1 Bit 2n IRQn1S IRQn0S 0 0 Interrupt request is detected on falling edge of IRQn input Interrupt request is detected on rising edge of IRQn input Interrupt request is detected on low level of IRQn input Interrupt request is detected on high level of IRQn input 0 1 1 0 1 1 Legend n=0 to 5 Rev. 1.00 Dec. 27, 2005 Page 250 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.4.4 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ5 to IRQ0. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 6 5 4 3 2 1 0 Bit Name IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R Initial Value 0 0 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W R/W Description Reserved These bit are always read as 0. The write value should always be 0. IRQn Interrupt Request Indicates whether there is interrupt request input to the IRQn pin. When edge-detection mode is set for IRQn, an interrupt request is cleared by writing 0 to the IRQnR bit after reading IRQnR = 1. When level-detection mode is set for IRQn, an interrupt request is set/cleared by only 1/0 input to the IRQn pin. IRQnR 0: No interrupt request input to IRQn pin 1: Interrupt request input to IRQn pin Legend: n = 0 to 5 8.4.5 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC and the SCIF0 are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 Bit Name TXI0R Initial Value 0 R/W R Description TXI0 Interrupt Request Indicates whether the TXI0 (SCIF0) interrupt request is generated. 0: TXI0 interrupt request is not generated 1: TXI0 interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 251 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 6 Bit Name BRI0R Initial Value 0 R/W R Description BRI0 Interrupt Request Indicates whether the BRI0 (SCIF0) interrupt request is generated. 0: BRI0 interrupt request is not generated 1: BRI0 interrupt request is generated 5 RXI0R 0 R RXI0 Interrupt Request Indicates whether the RXI0 (SCIF0) interrupt request is generated. 0: RXI0 interrupt request is not generated 1: RXI0 interrupt request is generated 4 ERI0R 0 R ERI0 Interrupt Request Indicates whether the ERI0 (SCIF0) interrupt request is generated. 0: ERI0 interrupt request is not generated 1: ERI0 interrupt request is generated 3 DEI3R 0 R DEI3 Interrupt Request Indicates whether the DEI3 (DMAC) interrupt request is generated. 0: DEI3 interrupt request is not generated 1: DEI3 interrupt request is generated 2 DEI2R 0 R DEI2 Interrupt Request Indicates whether the DEI2 (DMAC) interrupt request is generated. 0: DEI2 interrupt request is not generated 1: DEI2 interrupt request is generated 1 DEI1R 0 R DEI1 Interrupt Request Indicates whether the DEI1 (DMAC) interrupt request is generated. 0: DEI1 interrupt request is not generated 1: DEI1 interrupt request is generated 0 DEI0R 0 R DEI0 Interrupt Request Indicates whether the DEI0 (DMAC) interrupt request is generated. 0: DEI0 interrupt request is not generated 1: DEI0 interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 252 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.4.6 Interrupt Request Register 2 (IRR2) IRR2 is an 8-bit register that indicates whether interrupt requests from the SCIF1 are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 TXI1R 0 R TXI1 Interrupt Request Indicates whether the TXI1 (SCIF1) interrupt request is generated. 0: TXI1 interrupt request is not generated 1: TXI1 interrupt request is generated 2 BRI1R 0 R BRI1 Interrupt Request Indicates whether the BRI1 (SCIF1) interrupt request is generated. 0: BRI1 interrupt request is not generated 1: BRI1 interrupt request is generated 1 RXI1R 0 R RXI1 Interrupt Request Indicates whether the RXI1 (SCIF1) interrupt request is generated. 0: RXI1 interrupt request is not generated 1: RXI1 interrupt request is generated 0 ERI1R 0 R ERI1 Interrupt Request Indicates whether the ERI1 (SCIF1) interrupt request is generated. 0: ERI1 interrupt request is not generated 1: ERI1 interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 253 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.4.7 Interrupt Request Register 3 (IRR3) IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CUIR 0 R CUI Interrupt Request Indicates whether the CUI (RTC) interrupt request is generated. 0: CUI interrupt request is not generated 1: CUI interrupt request is generated 1 PRIR 0 R PRI Interrupt Request Indicates whether the PRI (RTC) interrupt request is generated. 0: PRI interrupt request is not generated 1: PRI interrupt request is generated 0 ATIR 0 R ATI Interrupt Request Indicates whether the ATI (RTC) interrupt request is generated. 0: ATI interrupt request is not generated 1: ATI interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 254 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.4.8 Interrupt Request Register 4 (IRR4) IRR4 is an 8-bit register that indicates whether interrupt requests from the TMU2, TMU1, TMU0, WDT, and REF are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit always read as 0. The write value should always be 0. 6 TUNI2R 0 R TUNI2 Interrupt Request Indicates whether the TUNI2 (TMU2) interrupt request is generated. 0: TUNI2 interrupt request is not generated 1: TUNI2 interrupt request is generated 5 TUNI1R 0 R TUNI1Interrupt Request Indicates whether the TUNI1 (TMU1) interrupt request is generated. 0: TUNI1 interrupt request is not generated 1: TUNI1 interrupt request is generated 4 TUNI0R 0 R TUNI0 Interrupt Request Indicates whether the TUNI0 (TMU0) interrupt request is generated. 0: TUNI0 interrupt request is not generated 1: TUNI0 interrupt request is generated 3 ITIR 0 R ITI Interrupt Request Indicates whether the ITI (WDT) interrupt request is generated. 0: ITI interrupt request is not generated 1: ITI interrupt request is generated 2 1 0 0 R R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 255 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 0 Bit Name RCMIR Initial Value 0 R/W R Description RCMI Interrupt Request Indicates whether the RCMI (REF) interrupt request is generated. 0: RCMI interrupt request is not generated 1: RCMI interrupt request is generated 8.4.9 Interrupt Request Register 5 (IRR5) IRR5 is an 8-bit register that indicates whether interrupt requests from the DMAC and E-DMAC are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 6 5 Bit Name DEI5R Initial Value 0 0 0 R/W R R R Description Reserved These bits are always read as 0. The write value should always be 0. DEI5 Interrupt Request Indicates whether the DEI5 (DMAC) interrupt request is generated. 0: DEI5 interrupt request is not generated 1: DEI5 interrupt request is generated 4 DEI4R 0 R DEI4 Interrupt Request Indicates whether the DEI4 (DMAC) interrupt request is generated. 0: DEI4 interrupt request is not generated 1: DEI4 interrupt request is generated 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 256 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 2 Bit Name EINT2R Initial Value 0 R/W R Description EINT2 Interrupt Request Indicates whether the EINT2 (E-DMAC) interrupt request is generated. 0: EINT2 interrupt request is not generated 1: EINT2 interrupt request is generated 1 EINT1R 0 R EINT1 Interrupt Request Indicates whether the EINT1 (E-DMAC) interrupt request is generated. 0: EINT1 interrupt request is not generated 1: EINT1 interrupt request is generated 0 EINT0R 0 R EINT0 Interrupt Request Indicates whether the EINT0 (E-DMAC) interrupt request is generated. 0: EINT0 interrupt request is not generated 1: EINT0 interrupt request is generated 8.4.10 Interrupt Request Register 7 (IRR7) IRR7 is an 8-bit register that indicates whether an interrupt request from the SIOF0 is generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 Bit Name CCI0R Initial Value 0 R/W R Description CCI0 Interrupt Request Indicates whether the CCI0 (SIOF0) interrupt request is generated. 0: CCI0 interrupt request is not generated 1: CCI0 interrupt request is generated 6 RXI0R 0 R RXI0 Interrupt Request Indicates whether the RXI0 (SIOF0) interrupt request is generated. 0: RXI0 interrupt request is not generated 1: RXI0 interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 257 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 5 Bit Name TXI0R Initial Value 0 R/W R Description TXI0 Interrupt Request Indicates whether the TXI0 (SIOF0) interrupt request is generated. 0: TXI0 interrupt request is not generated 1: TXI0 interrupt request is generated 4 ERI0R 0 R ERI0 Interrupt Request Indicates whether the ERI0 (SIOF0) interrupt request is generated. 0: ERI0 interrupt request is not generated 1: ERI0 interrupt request is generated 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8.4.11 Interrupt Request Register 8 (IRR8) IRR8 is an 8-bit register that indicates whether interrupt requests from the SIOF1 are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 Bit Name CCI1R Initial Value 0 R/W R Description CCI1 Interrupt Request Indicates whether the CCI1 (SIOF1) interrupt request is generated. 0: CCI1 interrupt request is not generated 1: CCI1 interrupt request is generated 6 RXI1R 0 R RXI1 Interrupt Request Indicates whether the RXI1 (SIOF1) interrupt request is generated. 0: RXI1 interrupt request is not generated 1: RXI1 interrupt request is generated Rev. 1.00 Dec. 27, 2005 Page 258 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Bit 5 Bit Name TXI1R Initial Value 0 R/W R Description TXI1 Interrupt Request Indicates whether the TXI1 (SIOF1) interrupt request is generated. 0: TXI1 interrupt request is not generated 1: TXI1 interrupt request is generated 4 ERI1R 0 R ERI1 Interrupt Request Indicates whether the ERI1 (SIOF1) interrupt request is generated. 0: ERI1 interrupt request is not generated 1: ERI1 interrupt request is generated 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 259 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.5 8.5.1 Operation Interrupt Sequence The sequence of interrupt operations is described below. Figure 8.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in the interrupt priority registers A to I (IPRA to IPRI). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to tables 8.2 and 8.3, Interrupt Exception Handling Sources and Priority. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in synchronization with the peripheral clock (P). The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with INTEVT or INTEVT2 value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then clear the BL bit or execute an RTE instruction. Rev. 1.00 Dec. 27, 2005 Page 260 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) Program execution state Interrupt generated? Yes No No SR.BL=0 or sleep mode? Yes Yes NMI? No Level 15 interrupt? No Yes Yes I3 to I0 level 14 or lower? Level 14 interrupt? No Set interrupt source in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bit in SR to 1 Branch to exception handler Yes I3 to I0 level 13 or lower? Level 1 interrupt? No No Yes Yes I3 to I0 level 0? No Yes No I3 to I0: Interrupt mask bits in status register (SR) Figure 8.3 Interrupt Operation Flowchart Rev. 1.00 Dec. 27, 2005 Page 261 of 932 REJ09B0269-0100 Section 8 Interrupt Controller (INTC) 8.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT or INTEVT2. The code in INTEVT or INTEVT2 can be used as an offset for branching to the specific handler. 2. Clear the interrupt source in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing the BL bit in step 4. See figure 8.3 on a sample interrupt operation flowchart. Rev. 1.00 Dec. 27, 2005 Page 262 of 932 REJ09B0269-0100 Section 9 User Break Controller Section 9 User Break Controller The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 9.1 Features The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). * Address Compares 40 bits configured of the ASID and addresses 32 bits: the ASID can be selected either all-bit comparison or all-bit mask. Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc. One of the four address buses (logic address bus (LAB), internal address bus (IAB), X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected. * Data Only on channel B, 32-bit maskable. One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB) and Y-memory data bus (YDB)) can be selected. * Bus cycle Instruction fetch or data access * Read/write * Operand size Byte, word, and longword 2. A user-designed user-break condition exception processing routine can be run. UBCS300B_000020020900 Rev. 1.00 Dec. 27, 2005 Page 263 of 932 REJ09B0269-0100 Section 9 User Break Controller 3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. * Maximum repeat times for the break condition (only for channel B): 212 - 1 times. * Eight pairs of branch source/destination buffers. Rev. 1.00 Dec. 27, 2005 Page 264 of 932 REJ09B0269-0100 Section 9 User Break Controller Figure 9.1 shows a block diagram of the UBC. XAB/YAB IAB ASID Access Control LAB Access comparator MDB BBRA BARA Address comparator ASID comparator Channel A BAMRA BASRA Access comparator BBRB Address comparator ASID comparator Data comparator Channel B BARB BAMRB BASRB BDRB BDMRB BETR BRSR PC trace BRDR CONTROL BRCR LDB/IDB/ XDB/YDB CPU state signals User break request UBC Location CCN Location Break ASID register B Break data register B Break data mask register B Execution times break register Branch source register Branch destination register Break control register [Legend] BBRA: BARA: BAMRA: BASRA: BBRB: BARB: BAMRB: Break bus cycle register A Break address register A Break address mask register A Break ASID register A Break bus cycle register B Break address register B Break address mask register B BASRB: BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Figure 9.1 Block Diagram of User Break Controller Rev. 1.00 Dec. 27, 2005 Page 265 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2 Register Descriptions The user break controller has the following registers. For details on register addresses and access sizes, refer to section 23, List of Registers. * * * * * * * * * * * * * * Break address register A (BARA) Break address mask register A (BAMRA) Break bus cycle register A (BBRA) Break address register B (BARB) Break address mask register B (BAMRB) Break bus cycle register B (BBRB) Break data register B (BDRB) Break data mask register B (BDMRB) Break control register (BRCR) Execution times break register (BETR) Branch source register (BRSR) Branch destination register (BRDR) Break ASID register A (BASRA) Break ASID register B (BASRB) Break Address Register A (BARA) 9.2.1 BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit 31 to 0 Bit Name BAA31 to BAA 0 Initial Value All 0 R/W R/W Description Break Address A Store the address on the LAB or IAB specifying break conditions of channel A. Rev. 1.00 Dec. 27, 2005 Page 266 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit 31 to 0 Bit Name BAMA31 to BAMA 0 Initial Value All 0 R/W R/W Description Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31-BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 9.2.3 Break Bus Cycle Register A (BBRA) BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 CDA1 CDA0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle Rev. 1.00 Dec. 27, 2005 Page 267 of 932 REJ09B0269-0100 Section 9 User Break Controller Bit 5 4 Bit Name IDA1 IDA0 Initial Value 0 0 R/W R/W R/W Description Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R/W R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R/W R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Rev. 1.00 Dec. 27, 2005 Page 268 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.4 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condition B. Bit 31 to 0 Bit Name BAB31 to BAB 0 Initial Value All 0 R/W R/W Description Break Address B Stores an address which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0. If the X memory is selected in BBRB, the values in bits 15 to 1 in XAB are set in BAB31 to BAB17. In this case, the values in BAB16 to BAB0 are arbitrary. If the Y memory is selected in BBRB, the values in bits 15 to 1 in YAB are set in BAB15 to BAB1. In this case, the values in BAB31 to BAB16, and BABO are arbitrary. Table 9.1 Specifying Break Address Register BAB16 BAB15 to BAB1 BAB0 Bus Selection in BBRB BAB31 to BAB17 L bus I bus X bus Y bus XAB15 to XAB1 Don't care LAB31 to LAB0 IAB31 to IAB0 Don't care Don't care Don't care YAB15 to YAB1 Don't care Don't care Rev. 1.00 Dec. 27, 2005 Page 269 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit 31 to 0 Bit Name BAMB31 to BAMB 0 Initial Value All 0 R/W R/W Description Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 9.2.6 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four data buses for break condition B. Bit 31 to 0 Bit Name BDB31 to BDB0 Initial Value All 0 R/W R/W Description Break Data Bit B Stores data which specifies a break condition in channel B. If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. If the X memory is selected in BBRB, the break data in bits 15 to 0 in XDB is set in BDB31 to BDB16. In this case, the values in BDB15 to BDB0 are arbitrary. If the Y memory is selected in BBRB, the break data in bits 15 to 0 in YDB are set in BDB15 to BDB0. In this case, the values in BDB31 to BDB16 are arbitrary. Rev. 1.00 Dec. 27, 2005 Page 270 of 932 REJ09B0269-0100 Section 9 User Break Controller Table 9.2 Specifying Break Data Register BDB31 to BDB16 BDB15 to BDB0 LDB31 to LDB0 IDB31 to IDB0 XDB15 to XDB0 Don't care Don't care YDB15 to YDB0 Bus Selection in BBRB L bus I bus X bus Y bus Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. 3. Set the data in bits 31 to 16 when including the value of the data bus as an L-bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction. 9.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit 31 to 0 Bit Name BDMB31 to BDMB 0 Initial Value All 0 R/W R/W Description Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB. 3. Set the mask data in bits 31 to 16 when including the value of the data bus as an Lbus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction. Rev. 1.00 Dec. 27, 2005 Page 271 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.8 Break Bus Cycle Register B (BBRB) BBRB is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit 15 to 10 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 XYE 0 R/W Selects the X memory bus or Y memory bus as the channel B break condition. Note that this bit setting is enabled only when the L bus is selected with the CDB1 and CDB0 bits. Selection between the X memory bus and Y memory bus is done by the XYS bit. 0: Selects L bus for the channel B break condition 1: Selects X/Y memory bus for the channel B break condition 8 XYS 0 R/W Selects the X bus or the Y bus as the bus of the channel B break condition. 0: Selects the X bus for the channel B break condition 1: Selects the Y bus for the channel B break condition 7 6 CDB1 CDB0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle Rev. 1.00 Dec. 27, 2005 Page 272 of 932 REJ09B0269-0100 Section 9 User Break Controller Bit 5 4 Bit Name IDB1 IDB0 Initial Value 0 0 R/W R/W R/W Description Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R/W R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZB1 SZB0 0 0 R/W R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Rev. 1.00 Dec. 27, 2005 Page 273 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. 6. Enable ASID check. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 BASMA 0 R/W Break ASID Mask A Specifies whether bits in channel A break ASID7 to ASID0 (BASA7 to BASA0) which are set in BASRA are masked or not. 0: All BASRA bits are included in the break conditions and the ASID is checked 1: All BASRA bits are not included in the break conditions and the ASID is not checked 20 BASMB 0 R/W Break ASID Mask B Specifies whether bits in channel B break ASID7 to ASID0 (BASB7 to BASB0) which are set in BASRB are masked or not. 0: All BASRB bits are included in the break conditions and the ASID is checked 1: All BASRB bits are not included in the break conditions and the ASID is not checked Rev. 1.00 Dec. 27, 2005 Page 274 of 932 REJ09B0269-0100 Section 9 User Break Controller Bit 19 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches 12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches Rev. 1.00 Dec. 27, 2005 Page 275 of 932 REJ09B0269-0100 Section 9 User Break Controller Bit 11 Bit Name PCTE Initial Value 0 R/W R/W Description PC Trace Enable 0: Disables PC trace 1: Enables PC trace 10 PCBA 0 R/W PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9 8 7 DBEB 0 0 0 R R R/W Reserved These bits are always read as 0. The write value should always be 0. Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5 4 0 0 R R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 276 of 932 REJ09B0269-0100 Section 9 User Break Controller Bit 3 Bit Name SEQ Initial Value 0 R/W R/W Description Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2 1 0 ETBE 0 0 0 R R R/W Reserved These bits are always read as 0. The write value should always be 0. Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B Rev. 1.00 Dec. 27, 2005 Page 277 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 - 1 times. When a break condition is satisfied, it decreases BETR. A break is issued when the break condition is satisfied after BETR becomes H'0001. Bit 15 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET11 to BET0 All 0 R/W Number of Execution Times Note: When the instruction fetch cycle is specified as the break condition of the channel B, and its break condition is triggerd by the following instructions, the BETR is decrimented by the following value (not by one). Instruction RTE DMULS.L Rm,Rn DMULU.L Rm,Rn MAC.L @Rm+,@Rn MAC.W @Rm+,@Rn MUL.L Rm,Rn AND.B #imm,@(R0,GBR) OR.B #imm,@(R0,GBR) TAS.B @Rn TST.B #imm,@(R0,GBR) XOR.B #imm,@(R0,GBR) LDC Rm,SR LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR LDC Rm,SPC LDC Rm,R0_BANK LDC Rm,R1_BANK LDC Rm,R2_BANK LDC Rm,R3_BANK LDC Rm,R4_BANK LDC Rm,R5_BANK LDC Rm,R6_BANK LDC Rm,R7_BANK Decrement value 4 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 Instruction LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+,R0_BANK LDC.L @Rm+,R1_BANK LDC.L @Rm+,R2_BANK LDC.L @Rm+,R3_BANK LDC.L @Rm+,R4_BANK LDC.L @Rm+,R5_BANK LDC.L @Rm+,R6_BANK LDC.L @Rm+,R7_BANK LDC.L @Rn+,MOD LDC.L @Rn+,RS LDC.L @Rn+,RE LDC Rn,MOD LDC Rn,RS LDC Rn,RE BSR label BSRF Rm JSR @Rm Decrement value 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 Rev. 1.00 Dec. 27, 2005 Page 278 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name SVF Initial Value 0 R/W R Description BRSR Valid Flag Indicates whether the branch source address is stored. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 by reading from BRSR. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 R Branch Source Address Store bits 27 to 0 of the branch source address. Rev. 1.00 Dec. 27, 2005 Page 279 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name DVF Initial Value 0 R/W R Description BRDR Valid Flag Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 by reading BRDR. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 R Branch Destination Address Store bits 27 to 0 of the branch destination address. 9.2.13 Break ASID Register A (BASRA) BASRA is an 8-bit readable/writable register that specifies ASID which becomes the break condition for channel A. BASRA is in CCN. Bit 7 to 0 Bit Name BASA7 to BASA0 Initial Value R/W R/W Description Break ASID A Store ASID (bits 7 to 0) which is the break condition for channel A. Rev. 1.00 Dec. 27, 2005 Page 280 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.2.14 Break ASID Register B (BASRB) BASRB is an 8-bit readable/writable register that specifies ASID which becomes the break condition for channel B. BASRB is in CCN. Bit 7 to 0 Bit Name BASB7 to BASB0 Initial Value R/W R/W Description Break ASID B Store ASID (bits 7 to 0) which is the break condition for channel B. 9.3 9.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and corresponding ASID are set in the break address registers (BARA or BARB) and break ASID registers (BASRA or BASRB in CCN). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is specified for channel B, SCMFCB is used for the condition match flag. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the break set in channel A and the break set in channel B occur around the same time. In this case, there will be only one break request to the CPU, but these two break channel match flags could be both set. 5. When selecting the I bus as the break condition, note the following: Rev. 1.00 Dec. 27, 2005 Page 281 of 932 REJ09B0269-0100 Section 9 User Break Controller Several bus masters, including the CPU, DMAC and E-DMAC, are connected to the I bus. The UBC monitors bus cycles generated by all bus masters, and determines the condition match. Physical addresses are used for the I bus. Set a physical address in break address registers (BARA and BARB). The bus cycles for logical addresses issued on the L bus by the CPU are converted to physical addresses before being output to the I bus. (If the address translation function is enabled, address translation by the MMU is carried out.) For data access cycles issued on the L bus by the CPU, if their logical addresses are not to be cached, they are issued with the data size specified on the L bus and their addresses are not rounded. For instruction fetch cycles issued on the L bus by the CPU, even though their logical addresses are not to be cached, they are issued in longwords and their addresses are rounded to match longword boundaries. If a logical address issued on the L bus by the CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwords and its address is rounded to match longword boundaries. However note that cache fill is not performed for a write miss in write through mode. In this case, the bus cycle is issued with the data size specified on the L bus and its address is not rounded. In write back mode, a write back cycle may be issued in addition to a read fill cycle. It is a longword bus cycle whose address is rounded to match longword boundaries. I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. The DMAC and E-DMAC only issues data access cycles for I bus cycles. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the break is to be accepted cannot be clearly defined. 6. While the block bit (BL) in the CPU status register (SR) is set to 1, no breaks can be accepted. However, condition determination will be carried out, and if the condition matches, the corresponding condition match flag is set to 1. Rev. 1.00 Dec. 27, 2005 Page 282 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 9.3.1, Flow of the User Break Operation. 9.3.3 Break on Data Access Cycle 1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 9.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 9.3. Rev. 1.00 Dec. 27, 2005 Page 283 of 932 REJ09B0269-0100 Section 9 User Break Controller Table 9.3 Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 Access Size Longword Word Byte This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on channel B: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register B (BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored). 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the break will occur cannot be determined. When this kind of break occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. Rev. 1.00 Dec. 27, 2005 Page 284 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.3.4 Break on X/Y-Memory Bus Cycle 1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The break condition cannot include both X-memory and Y-memory at the same time. The break condition is applied to an X/Y-memory bus cycle by specifying L bus/data access/read or write/word or no specified operand size in bits 7 to 0 in the break bus cycle register B (BBRB). 2. When an X-memory address is selected as the break condition, specify an X-memory address in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for BDRB and BDMRB. 3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a data access break of the L bus. For details, see 5 in section 9.3.3, Break on Data Access Cycle. 9.3.5 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0. 2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. Rev. 1.00 Dec. 27, 2005 Page 285 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.3.6 Value of Saved Program Counter When a break occurs, the address of the instruction from where execution is to be resumed is saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the SPC. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the SPC. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the SPC. 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the SPC. 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the SPC. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the SPC. If the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the SPC. Rev. 1.00 Dec. 27, 2005 Page 286 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.3.7 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR. If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. When a repeat loop of the DSP extended function is used, control being transferred from the repeat end instruction to the repeat start instruction is not recognized as a branch, and the values are not stored in BRSR and BRDR. 3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. 9.3.8 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: * Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode Rev. 1.00 Dec. 27, 2005 Page 287 of 932 REJ09B0269-0100 Section 9 User Break Controller Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) The ASID check is not included. A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequential mode Rev. 1.00 Dec. 27, 2005 Page 288 of 932 REJ09B0269-0100 Section 9 User Break Controller On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequential mode Rev. 1.00 Dec. 27, 2005 Page 289 of 932 REJ09B0269-0100 Section 9 User Break Controller * Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode Rev. 1.00 Dec. 27, 2005 Page 290 of 932 REJ09B0269-0100 Section 9 User Break Controller * Register specifications BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000, BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000, BRCR = H'00300080 Specified conditions: Channel A/channel B independent mode Rev. 1.00 Dec. 27, 2005 Page 291 of 932 REJ09B0269-0100 Section 9 User Break Controller 9.4 Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 4.1 in section 4, Exception Handling. If an exception with higher priority occurs, the user break is not generated. Pre-execution break has the highest priority. When a post-execution break or data access break occurs simultaneously with a reexecution-type exception (including pre-execution break) that has higher priority, the reexecution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a break does not occur, the condition match flag is set. 5. Note the following exception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error (or TLB related exception) by data access, the CPU address error (or TLB related exception) is given priority to the break. Note that the UBC condition match flag is set in this case. Rev. 1.00 Dec. 27, 2005 Page 292 of 932 REJ09B0269-0100 Section 9 User Break Controller 6. Note the following when a break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 8. When the repeat loop of the DSP extended function is used, even though a break condition is satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the break may be held. For details, see section 4, Exception Handling. Rev. 1.00 Dec. 27, 2005 Page 293 of 932 REJ09B0269-0100 Section 9 User Break Controller Rev. 1.00 Dec. 27, 2005 Page 294 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Section 10 Power-Down Modes With the power-down modes, the operation of the CPU and same of on-chip peripheral modules are halted to reduce power consumption. The power-down modes are canceled by interrupts or a reset. 10.1 10.1.1 Overview Power-Down Modes This LSI has the following power-down modes and function: 1. Sleep mode 2. Software standby mode 3. Module standby function Table 10.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Rev. 1.00 Dec. 27, 2005 Page 295 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Table 10.1 States of Power-Down Modes State CPG EtherC EDMAC CPU Halt CPU OnOn-Chip Reg- Chip External Periphera ister Memory l Modules Pins Memory Held Held Run Mode Sleep mode Transition Conditions Canceling Procedure Execute SLEEP Run instruction with STBY bit cleared to 0 in STBCR Held Refreshe 1. Interrupt d 2. Reset Software Execute SLEEP Halt Standby instruction with mode STBY bit set to 1 in STBCR Module standby function Set MSTP bit to 1 Run in STBCR, STBCR2, and STBCR3 Halt Held Held Halt* 1 Held Self1. Interrupt refreshed 2. Reset Run Held Held Specified * module halts 2 Refreshe 1. Clear d MSTP bit to 0 2. Poweron reset Notes: 1. The RTC runs when the START bit in RCR2 is set to 1. For details, see section 15, Realtime Clock (RTC). 2. Depends on the on-chip peripheral modules. For details, see section 1, Overview and Pin Function. 10.1.2 Reset A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed is terminated and any events not executed are canceled to execute reset processing immediately. In manual reset, processing required to maintain external memory contents is continued. The following shows the conditions in which power-on reset or manual reset occurs. * Power-on reset 1. A low level signal is input to the RESETP pin. 2. The WDT counter overflows if the WDT starts counting while the WT/IT and RSTS bits in WTCSR are set to 1 and cleared to 0, respectively. 3. An H-UDI reset occurs. (For details on the H-UDI reset, refer to section 22, User Debugging Interface (H-UDI).) Rev. 1.00 Dec. 27, 2005 Page 296 of 932 REJ09B0269-0100 Section 10 Power-Down Modes * Manual reset 1. A low signal is input to the RESETM pin. 2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1. Note: Immediately after a power-on reset or manual reset, be sure to execute the following routine: MOV.L MOV.L MOV.L NOP NOP TESTCR2_SET NOP MOV.B MOV.B MOV.L NOP NOP NOP MOV.L BF NOP NOP @R2, R3 TESTCR2_SET CMP/EQ R3, R0 R0, @R1 R0, @R1 R0, @R2 #H'FFFFFF40, R1 #H'80000005, R0 #H'A4FC0008, R2 Rev. 1.00 Dec. 27, 2005 Page 297 of 932 REJ09B0269-0100 Section 10 Power-Down Modes 10.1.3 Input/Output Pins Table 10.2 lists the pins used for the power-down modes. Table 10.2 Pin Configuration Pin Name Processing state 1 Processing state 0 Symbol STATUS1 STATUS0 I/O O Description Indicates the operating state of the processor. HH: Reset HL: Sleep mode LH: Standby mode LL: Normal operation Power-on reset Manual reset RESETP RESETM I I Inputting low level signal to this pin cause a transition to power-on reset processing. Inputting low level signal to this pin cause a transition to manual reset processing. Note: H and L indicate high and low levels, respectively. The STATUS1 and STATUS0 pins indicate the pin status in this order. 10.2 Register Descriptions The following registers are used for the power-down modes. Refer to section 23, List of Registers, for the addresses and access size for these registers. * Standby control register (STBCR) * Standby control register 2 (STBCR2) * Standby control register 3 (STBCR3) 10.2.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized to H00 at power-on reset but retains the previous value after manual reset. Rev. 1.00 Dec. 27, 2005 Page 298 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Bit 7 Bit Name STBY Initial Value R/W 0 R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode 1: Executing SLEEP instruction puts chip into software standby mode 6 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 MSTP2 0 R/W Module Stop Bit 2 When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted. 0: TMU runs 1: Clock supply to TMU halted 1 MSTP1 0 R/W Module Stop Bit 1 When the MSTP1 bit is set to 1, the supply of the clock to the RTC is halted. 0: RTC runs 1: Clock supply to RTC halted 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 299 of 932 REJ09B0269-0100 Section 10 Power-Down Modes 10.2.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in the powerdown mode. This register is initialized to H00 at power-on reset but retains the previous value after manual reset. Bit 7 Bit Name MSTP10 Initial Value R/W 0 R/W Description Module Stop Bit 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs 1: Clock supply to H-UDI halted 6 MSTP9 0 R/W Module Stop Bit 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs 1: Clock supply to UBC halted 5 MSTP8 0 R/W Module Stop Bit 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs 1: Clock supply to DMAC halted 4 MSTP7 0 R/W Module Stop Bit 7 When the MSTP7 bit is set to 1, the supply of the clock to the DSP is halted. 0: DSP runs 1: Clock supply to DSP halted 3 MSTP6 0 R/W Module Stop Bit 6 When the MSTP6 bit is set to 1, the supply of the clock to the TLB is halted. 0: TLB runs 1: Clock supply to TLB halted Rev. 1.00 Dec. 27, 2005 Page 300 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Bit 2 Bit Name MSTP5 Initial Value R/W 0 R/W Description Module Stop Bit 5 When the MSTP5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: The cache memory runs 1: Clock supply to the cache memory halted 1 0 R Reserved This bit is always read as 0. The write value should always be 0. 0 MSTP3 0 R/W Module Stop Bit 3 When the MSTP3 bit is set to 1, the supply of the clock to the X/Y memory is halted. 0: The X/Y memory runs 1: Clock supply to the X/Y memory halted 10.2.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of the peripheral modules in the power-down mode. This register is initialized to H00 at power-on reset but retains the previous value after manual reset. Bit 7 to 4 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 MSTP33 0 R/W Module Stop Bit 33 When the MSTP33 bit is set to 1, the supply of the clock to the SIOF1 is halted. 0: SIOF1 runs 1: Clock supply to SIOF1 halted 2 MSTP32 0 R/W Module Stop Bit 32 When the MSTP32 bit is set to 1, the supply of the clock to the SIOF0 is halted. 0: SIOF0 runs 1: Clock supply to SIOF0 halted Rev. 1.00 Dec. 27, 2005 Page 301 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Bit 1 Bit Name MSTP31 Initial Value R/W 0 R/W Description Module Stop Bit 31 When the MSTP31 bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: The SCIF1 runs 1: Clock supply to the SCIF1 halted 0 MSTP30 0 R/W Module Stop Bit 30 When the MSTP30 bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: The SCIF0 runs 1: Clock supply to the SCIF0 halted 10.3 10.3.1 Operation Sleep Mode Transition to Sleep Mode: Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO pin. In sleep mode, a high signal and low signal are output from the STATUS1 and STATUS0 pins, respectively. Canceling Sleep Mode: Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, or on-chip peripheral module) or reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. * Canceling with an Interrupt When an NMI, IRQ, IRL, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in INTEVT and INTEVT2. * Canceling with a Reset Sleep mode is canceled by a power-on reset or a manual reset. Rev. 1.00 Dec. 27, 2005 Page 302 of 932 REJ09B0269-0100 Section 10 Power-Down Modes 10.3.2 Software Standby Mode Transition to Software Standby Mode: The LSI switches from a program execution state to a software standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR. In a software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also halts. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral modules registers in software standby mode. Table 10.3 Register States in Software Standby Mode Module Interrupt Controller (INTC) On-Chip Oscillation Circuits User Break Controller (UBC) Bus State Controller (BSC) Timer Unit (TMU) I/O ports H-UDI SCIF0/1 SIOF0/1 EtherC, E-DMAC DMAC Registers Initialized -- -- -- -- TSTR -- -- -- -- -- -- Registers Retaining Data All registers All registers All registers All registers Registers other than TSTR All registers All registers All registers All registers All registers All registers Rev. 1.00 Dec. 27, 2005 Page 303 of 932 REJ09B0269-0100 Section 10 Power-Down Modes The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. 2. Set the WDT's timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After the STBY bit in STBCR is set to 1, a SLEEP instruction is executed. 4. Software standby mode is entered and the clocks within the chip are halted. The STATUS1 and STATUS0 pins output low and high, respectively. Canceling Software Standby Mode: Software standby mode is canceled by an interrupt (NMI, IRQ, IRL, or RTC) or a reset. * Canceling with an Interrupt The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRQ*1, IRL*1, or RTC*1 interrupt, the clock will be supplied to the entire chip and software standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins go low. Interrupt exception handling then begins and a code indicating the interrupt source is set in INTEVT and INTEVT2. After the branch to the interrupt handling routine, clear the STBY bit in STBCR. The WDT stops automatically. If the STBY bit is not cleared, the WDT continues operation and a transition is made to software standby mode*2 when WTCNT reaches H'80. A manual reset is not accepted until the STBY bit is cleared to 0. Interrupts are accepted in software standby mode even when the BL bit in SR is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an interrupt is detected, the phase of the CKIO pin clock output may be unstable, until the software standby mode is canceled. Notes: 1. Only when the RTC is used, software standby mode can be canceled by an IRQ, IRL, or RTC. 2. This standby mode can be canceled only by a power-on reset. Rev. 1.00 Dec. 27, 2005 Page 304 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Interrupt request Crystal resonator settling time and PLL synchronization time WTCNT value WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR. STBY is cleared, WTCNT halts automatically. H'FF H'80 Time Figure 10.1 Canceling Standby Mode with STBCR.STBY * Canceling with a Reset Software standby mode is canceled by a reset (power-on or manual). Keep the RESETP or RESETM pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin. 10.3.3 Module Standby Function Transition to Module Standby Function: Setting each MSTP bit in the standby control registers to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal or sleep mode. Before a transition is made, the module should be disabled. In the module standby state, the functions of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module. For details, see section 1, Overview and Pin Function. All of the register states are the same as those in standby mode. For details, see table 10.3. Canceling Module Standby Function: The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on reset. To cancel the module standby function by clearing the corresponding MSTP bit to 0, read the MSTP bit to check the MSTP bit was cleared correctly. Rev. 1.00 Dec. 27, 2005 Page 305 of 932 REJ09B0269-0100 Section 10 Power-Down Modes 10.3.4 STATUS Pin Change Timings The STATUS1 and STATUS0 pin change timings are shown below. Reset: * Power-on reset CKIO CKIO2 RESETP PLL setting time STATUS normal * 2 reset * 1 normal * 2 0 to 5 Bcyc *3 Notes: *1 reset : HH (STATUS1 = High, STATUS0 = High) *2 normal : LL (STATUS1 = Low, STATUS0 = Low) *3 Bcyc : Bus clock cycle 0 to 30 Bcyc*3 Figure 10.2 STATUS Output at Power-On Reset Rev. 1.00 Dec. 27, 2005 Page 306 of 932 REJ09B0269-0100 Section 10 Power-Down Modes * Manual reset CKIO CKIO2 RESETM STATUS normal * 3 reset * 2 normal * 3 0Bcyc~ *1,*4 0 to 30 Bcyc *4 Notes *1 : In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. *2 : reset: HH (STATUS1 = High, STATUS0 = High) *3 : normal: LL (STATUS1 = Low, STATUS0 = Low) *4 : Bcyc: Bus clock cycle Figure 10.3 STATUS Output at Manual Reset Software Standby Mode: * Software standby mode is canceled by an interrupt Oscillation stops Interrupt request WDT overflow CKIO CKIO2 WDT count STATUS normal *2 standby *1 normal * 2 Notes: *1 standby : LH (STATUS1 = Low, STATUS0 = High) *2 normal : LL (STATUS1 = Low, STATUS0 = Low) Figure 10.4 STATUS Output when Software Standby Mode is Canceled by Interrupt Rev. 1.00 Dec. 27, 2005 Page 307 of 932 REJ09B0269-0100 Section 10 Power-Down Modes * Software standby mode is canceled by a power-on reset Oscillation stops Reset CKIO CKIO2 RESETP *1 STATUS normal * 4 standby * 3 Undefined reset * 2 normal * 4 0 to 10 Bcyc *5 Notes: *1 If a standby mode is canceled by a power on reset, the WDT stops counting. RESETP must be kept low for the PLL oscillation stabilization time. *2 reset : HH (STATUS1 = High, STATUS0 = High) *3 standby : LH (STATUS1 = Low, STATUS0 = High) *4 normal : LL (STATUS1 = Low, STATUS0 = Low) *5 Bcyc : Bus clock cycle 0 to 30 Bcyc *5 Figure 10.5 STATUS Output when Software Standby Mode is Canceled by Power-on Reset * Software standby mode is canceled by a manual reset Oscillation stops Reset CKIO CKIO2 RESETM *1 STATUS normal * 4 standby * 3 reset * 2 normal * 4 0 to 20 Bcyc *5 Notes: *1 *2 *3 *4 *5 If a standby mode is canceled by a power on reset, the WDT stops counting. RESETM must be kept low for the PLL oscillation stabilization time. reset : HH (STATUS1 = High, STATUS0 = High) standby : LH (STATUS1 = Low, STATUS0 = High) normal : LL (STATUS1 = Low, STATUS0 = Low) Bcyc : Bus clock cycle Figure 10.6 STATUS Output when Software Standby Mode is Canceled by Manual Reset Rev. 1.00 Dec. 27, 2005 Page 308 of 932 REJ09B0269-0100 Section 10 Power-Down Modes Sleep Mode: * Sleep mode is canceled by an interrupt Interrupt request CKIO CKIO2 normal * 2 STATUS sleep * 1 normal * 2 Notes: *1 sleep : HL (STATUS1 = High, STATUS0 = Low) *2 normal : LL (STATUS1 = Low, STATUS0 = Low) Figure 10.7 STATUS Output when Sleep Mode is Canceled by Interrupt * Sleep mode is canceled by a power-on reset Reset CKIO CKIO2 RESETP *1 STATUS normal * 4 sleep * 3 Undefined reset * 2 normal * 4 0 to 10 Bcyc *5 Notes: *1 If PLL1 multiplication rate changed by a power-on reset, RESETP must be kept low for the oscillation stabilization time. *2 reset : HH (STATUS1 = High, STATUS0 = High) *3 sleep : HL (STATUS1= High, STATUS0= Low) *4 normal : LL (STATUS1 = Low, STATUS0 = Low) *5 Bcyc : Bus clock cycle 0 to 30 Bcyc *5 Figure 10.8 STATUS Output when Sleep Mode is Canceled by Power-on Reset Rev. 1.00 Dec. 27, 2005 Page 309 of 932 REJ09B0269-0100 Section 10 Power-Down Modes * Sleep mode is canceled by a manual reset Reset CKIO CKIO2 RESETM * 1 STATUS normal * 4 sleep * 3 reset * 2 normal * 4 0 to 80 Bcyc *5 Notes: *1 RESETM must be kept low until STATUS = reset. *2 reset:HH (STATUS1 = High, STATUS0 = High) *3 sleep:HL(STATUS1= High, STATUS0= Low) *4 normal:LL (STATUS1 = Low, STATUS0 = Low) *5 Bcyc:Bus clock cycle 0 to 30 Bcyc *5 Figure 10.9 STATUS Output when Sleep Mode is Canceled by Manual Reset Rev. 1.00 Dec. 27, 2005 Page 310 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Section 11 On-Chip Oscillation Circuits 11.1 Overview The oscillator consists of a clock pulse generator (CPG) block and a watchdog timer (WDT) block. The CPG generates clocks supplied to this LSI and controls the power-down modes. The WDT is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. 11.1.1 Features The CPG has the following features: * Seven clock modes: Selection of seven clock modes according to the frequency range to be used and direct connection of crystal resonator or external clock input. * Three clocks generated independently: An internal clock (I) for the CPU and cache; a peripheral clock (P) for the peripheral modules; and a bus clock (B = CKIO) for the external bus interface. * Frequency change function: Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control: The clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. The WDT has the following features: * Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Selection of power-on reset or manual reset. Rev. 1.00 Dec. 27, 2005 Page 311 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits * Generates interrupts in interval timer mode: An interval timer interrupt is generated after counter overflow. * Selection of eight counter input clocks Eight clocks in which peripheral clocks are divided (x 1 to x 1/4096) can be selected. Rev. 1.00 Dec. 27, 2005 Page 312 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.2 11.2.1 Overview of CPG CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 11.1. Clock pulse generator PLL circuit 1 ( 1, 2, 3) CKIO CKIO2 Divider 1 1 1/2 1/3 1/4 1/6 Internal clock (I ) XTAL EXTAL Crystal oscillator Bus clock (B =CKIO) PLL circuit 2 ( 1, 2, 4) Peripheral clock (P ) CPG control unit Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 STBCR3 Bus interface Internal bus [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3: Standby control register 3 Figure 11.1 Block Diagram of CPG Rev. 1.00 Dec. 27, 2005 Page 313 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, or leaves unchanged the input clock frequency from the CKIO terminal. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will synchronize with the phase of the rising edge of the CKIO pin. 2. PLL Circuit 2: PLL circuit 2 doubles, quadruples, or leaves unchanged the input clock frequency from the crystal oscillator or EXTAL pin. The multiplication ratio is fixed by the clock operating modes. The clock operating modes is set by pins MD0, MD1, and MD2. See table 11.2 for more information on clock operating modes. 3. Crystal Oscillator: This oscillator is used when a crystal resonator is connected to the XTAL and EXTAL pins. This crystal oscillator operates according to the clock operating mode setting. 4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal or peripheral clock. The operating frequency of the internal clock (I) can be 1, 1/2, or 1/3 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The operating frequency of the peripheral clock (P) can be 1/2, 1/3, 1/4, or 1/6 times the output frequency of PLL circuit 1 within 8.34 MHz P 33.34 MHz. The division ratio is set in the frequency control register. 5. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD pins and the frequency control register. 6. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator and other modules during clock switching or in sleep or standby mode. 7. Frequency Control Register: The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. 8. Standby Control Register: The standby control register has bits for controlling the power-down modes. See section 10, Power-Down Modes, for more information. Rev. 1.00 Dec. 27, 2005 Page 314 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.2.2 Input/Output Pins Table 11.1 lists the CPG pins and their functions. Table 11.1 Pin Configuration Pin Name Abbreviation I/O I I I O I IO O Description Set the clock operating mode. Set the clock operating mode. Set the clock operating mode. Connects a crystal oscillator. Connects a crystal oscillator. Also used to input an external clock. Inputs or outputs an external clock. Outputs an external clock. Mode control pins MD0 MD1 MD2 Crystal oscillator pins (clock input pins) Clock I/O pin Clock output pin XTAL EXTAL CKIO CKIO2 Note: To prevent device malfunction, the value of the mode control pin is sampled only by a power-on reset. 11.3 Clock Operating Modes Table 11.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and the clock modes. Table 11.3 shows the available combinations of the values of the clock modes and frequency control register (FRQCR). Table 11.2 Clock Operating Modes Pin Values Mode MD2 0 1 2 4 0 0 0 1 MD1 0 0 1 0 MD0 0 1 0 0 Clock I/O Source EXTAL EXTAL Output CKIO CKIO2 CKIO CKIO2 CKIO Crystal resonator CKIO2 CKIO Crystal resonator CKIO2 PLL2 On/Off ON (x 1) ON (x 4) ON (x 4) ON (x 1) PLL1 On/Off ON (x 1, 2, 3) ON (x 1, 2, 3) ON (x 1, 2, 3) ON (x 1, 2, 3) (Crystal) (Crystal) x 4 (EXTAL) x 4 CKIO Frequency (EXTAL) Rev. 1.00 Dec. 27, 2005 Page 315 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Pin Values Mode MD2 5 6 7 1 1 1 MD1 0 1 1 MD0 1 0 1 Clock I/O Source EXTAL Output CKIO CKIO2 CKIO Crystal resonator CKIO2 CKIO PLL2 On/Off ON (x 2) ON (x 2) OFF PLL1 On/Off ON (x 1, 2, 3) ON (x 1, 2, 3) ON (x 1, 2, 3) CKIO Frequency (EXTAL) x 2 (Crystal) x 2 (CKIO) Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside this LSI. An input clock frequency of 33.3 MHz to 66.67 MHz can be used, and the CKIO frequency range is 33.3 MHz to 66.67 MHz. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be used. An input clock frequency of 10.00 MHz to 16.67 MHz can be used, and the CKIO frequency range is 40.00 MHz to 66.67 MHz. Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be used. A crystal oscillation frequency of 10.00 MHz to 16.67 MHz can be used, and the CKIO frequency range is 40.00 MHz to 66.67 MHz. Mode 4: The on-chip crystal oscillator operates and undergoes waveform shaping by PLL circuit 2 before being supplied inside this LSI. A crystal oscillation frequency of 33.34 MHz to 48.00 MHz can be used, and the CKIO frequency range is 33.34 MHz to 48.00 MHz. Mode 5: An external clock is input from the EXTAL pin and its frequency is multiplied by 2 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be used. An input clock frequency of 16.67 MHz to 33.34 MHz can be used, and the CKIO frequency range is 33.34 MHz to 66.67 MHz. Mode 6: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 2 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency clock to be used. A crystal oscillation frequency of 10.00 MHz to 16.67 MHz can be used, and the CKIO frequency range is 40.00 MHz to 66.67 MHz Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to this LSI. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Rev. 1.00 Dec. 27, 2005 Page 316 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Table 11.3 Possible Combination of Clock Mode and FRQCR Values FRQCR Value 1001 1002 1003 1103 1104 1204 1, 2 1001 1002 1003 1103 1104 1204 4 1001 1002 1003 1103 PLL Circuit 1 On (x1) On (x1) On (x1) On (x2) On (x2) On (x3) On (x1) On (x1) On (x1) On (x2) On (x2) On (x3) On (x1) On (x1) On (x1) On (x2) PLL Circuit 2 On (x1) On (x1) On (x1) On (x1) On (x1) On (x1) On (x4) On (x4) On (x4) On (x4) On (x4) On (x4) On (x1) On (x1) On (x1) On (x1) Clock Ratio* (I:B:P) 1:1:1/2 1:1:1/3 1:1:1/4 2:1:1/2 2:1:1/3 3:1:1/2 4:4:2 4:4:4/3 4:4:1 8:4:2 8:4:4/3 12:4:2 1:1:1/2 1:1:1/3 1:1:1/4 2:1:1/2 Frequency Range of Input Clock and Frequency Range of Crystal Resonator CKIO Pin 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 10.00 MHz to 16.67 MHz 10.00 MHz to 16.67 MHz 10.00 MHz to 16.67 MHz 10.00 MHz to 16.67 MHz 10.00 MHz to 16.67 MHz 10.00 MHz to 16.67 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 40.00 MHz to 66.67 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz Mode 0 Rev. 1.00 Dec. 27, 2005 Page 317 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Mode 4 FRQCR Value 1104 1204 Clock PLL PLL Ratio* Circuit 1 Circuit 2 (I:B:P) On (x2) On (x3) On (x1) On (x1) On (x1) On (x2) On (x2) On (x3) On (x1) On (x1) On (x1) On (x2) On (x2) On (x3) On (x1) On (x1) On (x1) On (x1) On (x1) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) On (x2) Off Off Off 2:1:1/3 3:1:1/2 2:2:1 2:2:2/3 2:2:1/2 4:2:1 4:2:2/3 6:2:1 2:2:1 2:2:2/3 2:2:1/2 4:2:1 4:2:2/3 6:2:1 1:1:1/2 1:1:1/3 1:1:1/4 Frequency Range of Input Clock and Frequency Range of Crystal Resonator CKIO Pin 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 16.67 MHz to 33.34 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 48.00 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 5 1001 1002 1003 1103 1104 1204 6 1001 1002 1003 1103 1104 1204 7 1001 1002 1003 Rev. 1.00 Dec. 27, 2005 Page 318 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Mode 7 FRQCR Value 1103 1104 1204 Clock PLL PLL Ratio* Circuit 1 Circuit 2 (I:B:P) On (x2) On (x2) On (x3) Off Off Off 2:1:1/2 2:1:1/3 3:1:1/2 Frequency Range of Input Clock and Frequency Range of Crystal Resonator CKIO Pin 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz Notes: * 1. 2. 3. 4. 5. 6. The input clock is 1. Maximum frequency: I = 200.00 MHz, B (CKIO) = 66.67 MHz, P = 33.34 MHz Use the CKIO frequency within 33.34 MHz CKIO 66.67 MHz. The input to divider 1 is the output of PLL circuit 1. Use the internal clock frequency within 33.34 MHz I 200.00 MHz. The internal clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and the division ratio selected by the IFC bit in FRQCR. Do not set the internal clock frequency lower than the CKIO pin frequency. Use the peripheral clock frequency within 8.34 MHz P 33.34 MHz. The peripheral clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and the division ratio selected by the PFC bit in FRQCR. Do not set the peripheral clock frequency higher than the frequency of the CKIO pin. x 1, x 2, or x 3 can be used as the multiplication ratio of PLL circuit 1. x 1, x 1/2, or x 1/3 can be selected as the division ratio of an internal clock. x 1/2, x 1/3, x 1/4, or x 1/6 can be selected as the division ratio of a peripheral clock. Set the rate in FRQCR. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. Use the output frequency under 200.00 MHz. Rev. 1.00 Dec. 27, 2005 Page 319 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.4 Register Description The CPG has the following register. For details on register addresses and register access size, refer to section 23, List of Registers. * Frequency control register (FRQCR) 11.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. FRQCR is initialized to H'1003 by a power-on reset, but retains its value in a manual reset and in standby mode. The write values to bits 15 to 13, 11 to 10, 7 to 6, and 3 should always be 0. Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 CKOEN 1 R/W Clock Output Enable CKOEN specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the level-fixed state in the standby mode, CKIO pin is fixed at low during STATUS 1 = L, and STATUSO = H, when CKOEN is set to 0. Therefore, the malfunction of an external circuit because of an unstable CKIO clock in releasing the standby mode can be prevented. The CKIO pin becomes to input pin regardless of the value of the CKOEN bit in clock operating mode 7. 0: CKIO pin goes to low level state in standby mode. 1: Clock is output from CKIO pin 11 10 0 0 R R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 320 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Bit 9 8 Bit Name STC1 STC0 Initial Value 0 0 R/W R/W R/W Description Frequency Multiplication Ratio of PLL Circuit 1 00: x 1 time 01: x 2 times 10: x 3 times 11: Reserved (setting prohibited) 7 6 5 4 IFC1 IFC0 0 0 0 0 R R R/W R/W Reserved These bits are always read as 0. The write value should always be 0. Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock (I) with respect to the output frequency of PLL circuit 1. 00: x 1 time 01: x 1/2 time 10: x 1/3 time 11: Reserved (setting prohibited) 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PFC2 PFC1 PFC0 0 1 1 R/W R/W R/W Peripheral Clock Frequency Division Ratio These bits specify the division ratio of the peripheral clock (P) frequency with respect to the output frequency of PLL circuit 1. 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time Other than above: Reserved (setting prohibited) Rev. 1.00 Dec. 27, 2005 Page 321 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.5 Changing Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are controlled by software through FRQCR. The methods are described below. 11.5.1 Changing Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: TME bit in WTCSR = 0: WDT stops CKS2 to CKS0 bits in WTCSR: Division ratio of WDT count clock WTCNT: Initial counter value 3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC1 and IFC0 bits and PFC2 to PFC0 bits. 4. The processor pauses internally and the WDT starts incrementing. The internal and peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. 11.5.2 Changing Division Ratio The WDT will not count unless the multiplication rate is changed simultaneously. 1. In the initial state, IFC1 and IFC0 = 00 and PFC2 to PFC0 = 011. 2. Set the IFC1, IFC0, and PFC2 to PFC0 bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio. Rev. 1.00 Dec. 27, 2005 Page 322 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.6 11.6.1 Overview of WDT Block Diagram of WDT Figure 11.2 shows a block diagram of the WDT. WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Reset control Clock selection Overflow Divider Clock selector Interrupt control Clock WTCSR Bus interface WTCNT Peripheral bus [Legend] WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 11.2 Block Diagram of WDT Rev. 1.00 Dec. 27, 2005 Page 323 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.7 Register Descriptions of WDT The WDT has the following two registers that select the clock, switch the timer mode, and perform other functions. For details on register addresses and register access size, refer to section 23, List of Registers. * Watchdog timer counter (WTCNT) * Watchdog timer control/status register (WTCSR) 11.7.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable counter. WTCNT increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. WTCNT is initialized to H'00 only by a power-on reset through the RESETP pin. Use a word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: WTCNT differs from other registers in that it is more difficult to write to. See section 11.7.3, Notes on Register Access, for details. 11.7.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow causes an internal reset, WTCSR retains its value. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: WTCSR differs from other registers in that it is more difficult to write to. See section 11.7.3, Notes on Register Access, for details. Rev. 1.00 Dec. 27, 2005 Page 324 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Bit 7 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode Rev. 1.00 Dec. 27, 2005 Page 325 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period in the table is the value when the peripheral clock (P) is 15 MHz. Clock Select 000 001 010 011 100 101 110 111 Clock Overflow Period Division Ratio (when P =15MHz) 1 17 s 1/4 68 s 1/16 273 s 1/32 546 s 1/64 1.09 ms 1/256 4.36 ms 1/1024 17.48 ms 1/4096 69.91 ms Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. 11.7.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 11.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. Rev. 1.00 Dec. 27, 2005 Page 326 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits WTCNT write 15 Address: H'A415FF84 H'5A 8 7 Write data 0 WTCSR write 15 Address: H'A415FF86 H'A5 8 7 Write data 0 Figure 11.3 Writing to WTCNT and WTCSR 11.8 11.8.1 Using WDT Canceling Standbys The WDT can be used to cancel standby mode with an interrupt such as an NMI. The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RESETP or RESETM pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Move to standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set at this time. 6. Since the WDT continues counting from H'00, clear the STBY bit in STBCR to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. Rev. 1.00 Dec. 27, 2005 Page 327 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.8.2 Changing Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written, the processor stop temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set at this time. 5. The counter stops at the values H'00. 6. Before changing the WTCNT after the execution of the frequency change instruction, always confirm that the value of the WTCNT is H'00 by reading the WTCNT. 11.8.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. 11.8.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting. Rev. 1.00 Dec. 27, 2005 Page 328 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits 11.9 Notes on Board Design When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. Avoid crossing signal lines CL1 CL2 R EXTAL XTAL This LSI Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal manufacturer. Figure 11.4 Points for Attention when Using Crystal Resonator Bypass Capacitors: Insert a laminated ceramic capacitor as a bypass capacitor for each Vss/VssQ and Vcc/VccQ pair. Mount the bypass capacitors to the power supply pins, and use components with a frequency characteristic suitable for the operating frequency of the LSI, as well as a suitable capacitance value. Pin assignments of HQFP2828-256 (FP-256G/GV) Vss/VssQ and Vcc/VccQ pair of digital circuitry 3 and 4, 13 and 14, 15 and 16, 25 and 26, 35 and 36, 43 and 44, 49 and 50, 57 and 58, 72 and 73, 81 and 82, 83 and 84, 92 and 93, 99 and 100, 107 and 108, 113 and 114, 121 and 122, 136 and 137, 146 and 147, 148 and 149, 158 and 159, 167 and 168, 176 and 177, 185 and 186, 191 and 192, 206 and 207, 208 and 209, 221 and 222, 227 and 228, 235 and 236, 241 and 242 Vss/VssQ and Vcc/VccQ pair of the on-chip oscillator 193 and 196, 251 and 252, 253 and 254 Rev. 1.00 Dec. 27, 2005 Page 329 of 932 REJ09B0269-0100 Section 11 On-Chip Oscillation Circuits Pin assignments of P-LFBGA1717-256 (BP-256H/HV) Vss/VssQ and Vcc/VccQ pair of digital circuitry D2-B1, E1-F4, G2-G3, J2-J4, L3-L2, N3-N2, R4-P2, U2-W1, V4-Y4, Y6-U7, W8-V8, V10W10, V11-W11, V13-W13, U15-W14, W17-Y19, U18-U20, P17-N19, N18-P20, L17-L20, J18-J19, E20-F17, D19-B20, C19-A20, D15-B14, C14-A15, B11-D11, C10-B10, C8-B8, D6B7 Vss/VssQ and Vcc/VccQ pair of the on-chip oscillator B19-A19, C3-B5, and C5-C4 When Using a PLL Oscillator Circuit: Keep the wiring from the PLL Vcc and PLL Vss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. Connect the EXTAL pin to VccQ or VssQ and make the XTAL pin open in clock mode 7. The analog power supply system of the PLL is sensitive to a noise. Therefore the system malfunction may occur by the intervention with other power supply. Do not supply the analog power supply with the same resource as the digital power supply of Vcc and VccQ. Avoid crossing signal lines Vcc(PLL2) Power Vcc supply Vss(PLL2) Vcc(PLL1) Vss Vss(PLL1) Figure 11.5 Points for Attention when Using PLL Oscillator Circuit Rev. 1.00 Dec. 27, 2005 Page 330 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Section 12 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. The BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 12.1 Features The BSC has the following features: 1. External address space * A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B, CS6A and CS6B, totally 384 Mbytes (divided into eight areas). * A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a total of 384 Mbytes (divided into six areas). * Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous or asynchronous), SDRAM, PCMCIA for each address space. * Can select the data bus width (8, 16, or 32 bits) for each address space. * Controls the insertion of the wait state for each address space. * Controls the insertion of the wait state for each read access and write access. * Can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), or the first cycle is a write access. 2. Normal space interface * Supports the interface that can directly connect to the SRAM. 3. Burst ROM (clock asynchronous) interface * High-speed access to the ROM that has the page mode function. 4. * * * * * SDRAM interface Can set the SDRAM in up to 2 areas. Multiplex output for row address/column address. Efficient access by single read/single write. High-speed access by bank-active mode. Supports an auto-refresh and self-refresh. Rev. 1.00 Dec. 27, 2005 Page 331 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 5. Byte-selection SRAM interface * Can connect directly to a byte-selection SRAM. 6. PCMCIA direct interface * Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver 4.2 (PCMCIA2.1 Rev 2.1). * Controls the insertion of the wait state using software. * Supports the bus sizing function of the I/O bus width (only in little endian mode). 7. Burst ROM (clock synchronous) interface * Can connect directly to a burst ROM of the clock synchronous type. 8. Bus arbitration * Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 9. * * * Refresh function Supports the auto-refresh and self-refresh functions. Specifies the refresh interval using the refresh counter and clock selection. Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 10. Interval timer using refresh counter * Generates an interrupt request by a compare match. The block diagram of the BSC is shown in figure 12.1. Rev. 1.00 Dec. 27, 2005 Page 332 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) BACK BREQ Bus mastership controller CMNCR Internal bus Internal master module Internal slave module CS0WCR WAIT Wait controller ... ... CS6BWCR MD5 to MD3 A25 to A0, D31 to D0 BS, RD/WR, RD, WE3(BE3) to WE0(BE0), RAS, CAS, CKE, DQMxx, CE2A, CE2B CS6BBCR Memory controller IOIS16 SDCR RTCSR RTCNT REFOUT Refresh controller Comparator Interrupt controller RTCOR BSC [Legend] CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Figure 12.1 Block Diagram of BSC Rev. 1.00 Dec. 27, 2005 Page 333 of 932 REJ09B0269-0100 Module bus CS0, CS2, CS3, CS4, CS5A, CS5B, CS6A, CS6B Area controller CS0BCR ... ... ... Section 12 Bus State Controller (BSC) 12.2 Input/Output Pins The configuration of pins in this module is shown in table 12.1. Table 12.1 Pin Configuration Name A25 to A0 D31 to D0 BS I/O O I/O O Function Address bus Data bus Bus cycle start Asserted when a normal space, burst ROM (clock synchronous/asynchronous), or PCMCIA is accessed. Asserted by the same timing as CAS in SDRAM access. CS0, CS2 to CS4 CS5A CS5B/CE1A O O O Chip select Chip select Active only for address map 1 Chip select Corresponds to PCMCIA card select signals D7 to D0 when the PCMCIA is used. CE2A CS6A CS6B/CE1B O O O Corresponds to PCMCIA card select signals D15 to D8 when the PCMCIA is used. Chip select Active only for address map 1 Chip select Corresponds to PCMCIA card select signals D7 to D0 when the PCMCIA is used. CE2B RD/WR O O Corresponds to PCMCIA card select signals D15 to D8 when the PCMCIA is used. Read/write Connects to WE pins when SDRAM or byte-selection SRAM is connected. RD O Read pulse signal (read data output enable signal) A strobe signal to indicate the memory read cycle when the PCMCIA is used. Rev. 1.00 Dec. 27, 2005 Page 334 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Name I/O Function Indicates that D31 to D24 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the I/O write strobe signal when the PCMCIA is used. WE3(BE3)/ICIOWR O WE2(BE2)/ICIORD O Indicates that D23 to D16 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the I/O read strobe signal when the PCMCIA is used. WE1(BE1)/WE O Indicates that D15 to D8 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. Functions as the memory write strobe signal when the PCMCIA is used. WE0(BE0) O Indicates that D7 to D0 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. RAS CAS CKE IOIS16 O O O I Connects to RAS pin when SDRAM is connected. Connects to CAS pin when SDRAM is connected. Connects to CKE pin when SDRAM is connected. PCMCIA 16-bit I/O signal Valid only in little endian mode. Make it into low level at the time of big endian mode. DQMUU DQMUL DQMLU DQMLL WAIT BREQ BACK MD5 to MD3 REFOUT O Connected to the DQMxx when the SDRAM is connected. DQMUU: Selects D31 to D24 DQMUL: Selects D23 to D16 DQMLU: Selects D15 to D8 DQMLL: Selects D7 to D0 I I O I O External wait input Bus request input Bus acknowledge output MD5: Selects data alignment (big endian or little endian) MD4 and MD3: Specify area 0 bus width (8/16/32 bits) Refresh request output when a bus is released Rev. 1.00 Dec. 27, 2005 Page 335 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.3 12.3.1 Area Overview Area Division In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces. The upper three bits divide into the P0 to P4 areas, and specify the cache access method. For details see section 6, Cache. The remaining 29 bits are used for division of the space into ten areas (address map 1) or eight areas (address map 2) according to the MAP bit in CMNCR setting. The BSC performs control for this 29-bit space. As listed in tables 12.2 and 12.3, this LSI can be connected directly to eight areas of memory, and it outputs chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of them. CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address map 1 is selected; and CS5B is asserted when address map 2 is selected. 12.3.2 Shadow Area Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by physical addresses A28 to A25, which correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space in P1 to P3 areas obtained by adding to it H'20000000 x n (n = 1 to 6). The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n (n = 0 to 6) corresponding to the area 7 shadow space is reserved, so do not use it. Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is assigned for internal register addresses. Therefore, area P4 does not become shadow space. Rev. 1.00 Dec. 27, 2005 Page 336 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 Address Space P0 Area 0 (CS0) Area 1 (Internal I/O) Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5A (CS5A) Area 5B (CS5B) Area 6A (CS6A) Area 6B (CS6B) Area 7 (Reserved area) Physical address space Figure 12.2 Address Space Rev. 1.00 Dec. 27, 2005 Page 337 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.3.3 Address Map The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces (address map 1) or 6 partial spaces (address map 2). The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 12.2 Address Space Map 1 (CMNCR.MAP = 0) Physical Address H00000000 to H03FFFFFF Area Area 0 Memory to be Connected Normal memory* 3 Capacity 64 Mbytes Burst ROM (Asynchronous) Burst ROM (Synchronous) H04000000 to H07FFFFFF H08000000 to H0BFFFFFF Area 1 Area 2 Internal I/O register area* Normal memory* SDRAM H0C000000 to H0FFFFFFF Area 3 Normal memory* SDRAM H10000000 to H13FFFFFF Area 4 Normal memory* 3 3 3 2 64 Mbytes 64 Mbytes Byte-selection SRAM 64 Mbytes Byte-selection SRAM 64 Mbytes Byte-selection SRAM Burst ROM (Asynchronous) H14000000 to H15FFFFFF H16000000 to H17FFFFFF H18000000 to H19FFFFFF H1A000000 to H1BFFFFFF H1C000000 to H1FFFFFFF Area 5A Area 5B Area 6A Area 6B Area 7 Normal memory* Normal memory* Normal memory* 3 32 Mbytes 32 Mbytes 32 Mbytes 32 Mbytes 64 Mbytes 3 Byte-selection SRAM 3 Normal memory* Reserved area* 1 3 Byte-selection SRAM Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 2. Set the top three bits of the address to 101 to allocate in the P2 space. 3. Memory that has an interface such as SRAM. Rev. 1.00 Dec. 27, 2005 Page 338 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.3 Address Space Map 2 (CMNCR.MAP = 1) Physical Address H00000000 to H03FFFFFF Area Area 0 Memory to be Connected Normal memory* 4 Capacity 64 Mbytes Burst ROM (Asynchronous) Burst ROM (Synchronous) H04000000 to H07FFFFFF H08000000 to H0BFFFFFF Area 1 Area 2 Internal I/O register area* Normal memory* SDRAM H0C000000 to H0FFFFFFF Area 3 Normal memory* SDRAM H10000000 to H13FFFFFF Area 4 Normal memory* 4 4 4 3 64 Mbytes 64 Mbytes Byte-selection SRAM 64 Mbytes Byte-selection SRAM 64 Mbytes Byte-selection SRAM Burst ROM (Asynchronous) H14000000 to H17FFFFFF Area 5* 2 Normal memory* PCMCIA 4 64 Mbytes Byte-selection SRAM H18000000 to H1BFFFFFF Area 6* 2 Normal memory*4 Byte-selection SRAM PCMCIA 64 Mbytes H1C000000 to H1FFFFFFF Area 7 Reserved area* 1 64 Mbytes Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 2. For area 5, CS5BBCR and CS5BWCR are valid. For area 6, CS6BBCR and CS6BWCR are valid. 3. Set the top three bits of the address to 101 to allocate in the P2 space. 4. Memory that has an interface such as SRAM. Rev. 1.00 Dec. 27, 2005 Page 339 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.3.4 Area 0 Memory Type and Memory Bus Width The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The memory bus width of the other area is set by the register. The correspondence between the memory type, external pins (MD3, MD4), and bus width is listed in the table below. Table 12.4 Correspondence between External Pins (MD3 and MD4), Memory Type of CS0, and Memory Bus Width MD4 0 MD3 0 1 1 Note: * 0 1 Memory Type Normal memory Bus Width Reserved (Setting prohibited) 8 bits* 16 bits 32 bits The bus width must not be specified as eight bits if the burst ROM (clock synchronous) interface is selected. 12.3.5 Data Alignment This LSI supports the big endian and little endian methods of data alignment. The data alignment is specified using the external pin (MD5) at power-on reset as shown in table 12.5. Table 12.5 Correspondence between External Pin (MD5) and Endians MD5 0 1 Endian Big endian Little endian Rev. 1.00 Dec. 27, 2005 Page 340 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4 Register Descriptions The BSC has the following registers. Refer to section 23, List of Registers, for the addresses and access size for these registers. Do not access spaces other than CS0 until the termination of the setting the memory interface. * * * * * * * * * * * * * * * * * * * * * * * Common control register (CMNCR) Bus control register for area 0 (CS0BCR) Bus control register for area 2 (CS2BCR) Bus control register for area 3 (CS3BCR) Bus control register for area 4 (CS4BCR) Bus control register for area 5A (CS5ABCR) Bus control register for area 5B (CS5BBCR) Bus control register for area 6A (CS6ABCR) Bus control register for area 6B (CS6BBCR) Wait control register for area 0 (CS0WCR) Wait control register for area 2 (CS2WCR) Wait control register for area 3 (CS3WCR) Wait control register for area 4 (CS4WCR) Wait control register for area 5A (CS5AWCR) Wait control register for area 5B (CS5BWCR) Wait control register for area 6A (CS6AWCR) Wait control register for area 6B (CS6BWCR) SDRAM control register (SDCR) Refresh timer control/status register (RTCSR)*1 Refresh timer counter (RTCNT)*1 Refresh time constant register (RTCOR)*1 SDRAM mode register for area 2 (SDMR2)*2 SDRAM mode register for area 3 (SDMR3)*2 Notes: 1. This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits of the data must be H'A55A. Otherwise, writing cannot be performed. In reading, the upper 16 bits are read as H'0000. 2. The contents of this register are stored in SDRAM. When this register space is accessed, the corresponding register in SDRAM is written to. For details, see description of Power-on Sequence in section 12.5.5, SDRAM Interface. Rev. 1.00 Dec. 27, 2005 Page 341 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Do not access external memory other than area 0 until the CMNCR initialization is complete. Bit 31 to 15 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BSD 0 R/W Bus Access Start Timing Specification After Bus Acknowledge Specifies the bus access start timing after the external bus acknowledge signal is received. 0: Starts the external access at the same timing as the address drive start after the bus acknowledge signal is received. 1: Starts the external access one cycle following the address drive start after the bus acknowledge signal is received. 13 0 R Reserved This bit is always read as 0. The write value should always be 0. 12 MAP 0 R/W Space Specification Selects the address map for the external address space. The address maps to be selected are shown in tables 12.2 and 12.3. 0: Selects address map 1. 1: Selects address map 2. 11 BLOCK 0 R/W Bus Lock Bit Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. Rev. 1.00 Dec. 27, 2005 Page 342 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 Bit Name DPRTY1 DPRTY0 Initial Value 0 0 R/W R/W R/W Description DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer 01: Accepts a refresh request but does not accept a bus mastership request during DMA burst transfer 10: Accepts neither a refresh request nor a bus mastership request during DMA burst transfer 11: Reserved (Setting prohibited) 8 7 6 DMAIW2 DMAIW1 DMAIW0 0 0 0 R/W R/W R/W Wait States between Access Cycles when DMA Single Address is Transferred Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycled inserted 100: 6 idle cycled inserted 101: 8 idle cycle inserted 110: 10 idle cycles inserted 111: 12 idle cycled inserted 5 DMAIWA 0 R/W Method of Inserting Wait States between Access Cycles when DMA Single Address is Transferred Specifies the method of inserting the idle cycles specified by the DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. When the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles even when the continuous accesses to an external device with DACK are performed. Rev. 1.00 Dec. 27, 2005 Page 343 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 4 Bit Name Initial Value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. 3 ENDIAN 0/1* R Endian Flag Samples the external pin for specifying endian on power-on reset (MD5). All address spaces are defined by this bit. This is a read-only bit. 0: The external pin for specifying endian (MD5) was low level on power-on reset. This LSI is being operated as big endian. 1: The external pin for specifying endian (MD5) was high level on power-on reset. This LSI is being operated as little endian. 2 CK2DRV 0 R/W CKIO2 Drive Specifies whether the CKIO2 pin outputs a low level signal or clock (B). 0: Outputs a low level signal 1: Outputs a clock (B) 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in standby mode for A25 to A0, BS, CSn, RD/WR, WEn (BEn)/DQMxx, and RD. When a bus is released, these pins enter the high-impedance state regardless of the setting of this bit. 0: High impedance in standby mode 1: Driven in standby mode Rev. 1.00 Dec. 27, 2005 Page 344 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 0 Bit Name HIZCNT Initial Value 0 R/W R/W Description High-Z Control Specifies the state in standby mode and bus released for CKIO, CKIO2, CKE, RAS, and CAS. 0: High impedance in standby mode and bus released for CKIO, CKIO2, CKE, RAS, and CAS. 1: Driven in standby mode and bus released for CKIO, CKIO2, CKE, RAS, and CAS. Note: If one of clock operating modes 4 to 6 is set, CKIO, CKIO2, CKE, RAS, and CAS should be driven in standby mode and bus released. Note: * The external pin (MD5) for specifying endian is sampled on power-on reset. When big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1. 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and the number of wait cycles between access cycles. Do not access external memory other than area 0 until the CSnBCR initialization is completed. Bit 31 Initial Bit Name Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 345 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 30 29 28 Bit Name IWW2 IWW1 IWW0 Initial Value 0 1 1 R/W R/W R/W R/W Description Idle Cycles between Write-Read Cycles and Write-Write Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 27 26 25 IWRWD2 IWRWD1 IWRWD0 0 1 1 R/W R/W R/W Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous accesses switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Dec. 27, 2005 Page 346 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 24 23 22 Initial Bit Name Value IWRWS2 IWRWS1 IWRWS0 0 1 1 R/W R/W R/W R/W Description Idle Cycles for Read-Write in Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous accesses are for the same space. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 21 20 19 IWRRD2 IWRRD1 IWRRD0 0 1 1 R/W R/W R/W Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses switch between different space. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Dec. 27, 2005 Page 347 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 18 17 16 Initial Bit Name Value IWRRS2 IWRRS1 IWRRS0 0 1 1 R/W R/W R/W R/W Description Idle Cycles for Read-Read in Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses are for the same space. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Dec. 27, 2005 Page 348 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 15 14 13 12 Initial Bit Name Value TYPE3 TYPE2 TYPE1 TYPE0 0 0 0 0 R/W R/W R/W R/W R/W Description Memory Type Specify the type of memory connected to a space. 0000: Normal space 0001: Burst ROM (clock asynchronous) 0010: Reserved (setting prohibited) 0011: Byte-selection SRAM 0100: SDRAM 0101: PCMCIA 0110: Reserved (setting prohibited) 0111: Burst ROM (clock synchronous)*2 1000: Reserved (setting prohibited) 1001: Reserved (setting prohibited) 1010: Reserved (setting prohibited) 1011: Reserved (setting prohibited) 1100: Reserved (setting prohibited) 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Note: Memory type for area 0 immediately after reset is normal space. The normal space, burst ROM (clock asynchronous), or burst ROM (clock synchronous) can be selected by these bits. For details on memory type in each area, see tables 12.2 and 12.3. Rev. 1.00 Dec. 27, 2005 Page 349 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 11 Initial Bit Name Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10 9 BSZ1 BSZ0 1*1 1* 1 R/W R/W Data Bus Size Specify the data bus sizes of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size Notes: 1. The data bus width for area 0 is specified by the external pin. The BSZ1 and BSZ0 bit settings in CS0BCR are ignored. 2. If area 5 or area 6 is specified as PCMCIA space, the bus width can be specified as either 8 bits or 16 bits. 3. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as either 16 bits or 32 bits. 8 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at a power-on reset. 2. The burst ROM (clock synchronous) must be accessed as a cacheable space. Rev. 1.00 Dec. 27, 2005 Page 350 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) This register specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. Normal Space, Byte-Selection SRAM: * CS0WCR, CS6BWCR Bit 31 to 21 20 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn (BEn) signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 13 12 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Dec. 27, 2005 Page 351 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Reserved (Setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 352 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 1 0 Initial Bit Name Value HW1 HW0 0 0 R/W R/W R/W Description Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles * CS2WCR, CS3WCR Bit 31 to 21 20 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn (BEn) signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 353 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 8 7 Initial Bit Name Value WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 354 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) * CS4WCR Bit 31 to 21 20 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn (BEn) signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 17 16 WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 355 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 12 11 Bit Name SW1 SW0 Initial Value 0 0 R/W R/W R/W Description Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored Rev. 1.00 Dec. 27, 2005 Page 356 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 5 to 2 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles * CS5AWCR Bit 31 to 19 18 17 16 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 357 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 12 11 Bit Name SW1 SW0 Initial Value R/W 0 0 R/W R/W Description Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored Rev. 1.00 Dec. 27, 2005 Page 358 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 5 to 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles * CS5BWCR Bit 31 to 21 20 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn (BEn) signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 359 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 18 17 16 Bit Name WW2 WW1 WW0 Initial Value 0 0 0 R/W R/W R/W R/W Description Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Dec. 27, 2005 Page 360 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Dec. 27, 2005 Page 361 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) * CS6AWCR Bit 31 to 13 12 11 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 1.00 Dec. 27, 2005 Page 362 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 6 Initial Bit Name Value WM 0 R/W R/W Description External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Dec. 27, 2005 Page 363 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Burst ROM (Clock Asynchronous): * CS0WCR Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BEN 0 R/W Burst Enable Specification Enables or disables 8-burst access for a 16-bit bus width or 16-burst access for an 8-bit bus width during 16-byte access. If this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. To use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: Enables 8-burst access for a 16-bit bus width and 16burst access for an 8-bit bus width. 1: Disables 8-burst access for a 16-bit bus width and 16burst access for an 8-bit bus width. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 31 to 21 Rev. 1.00 Dec. 27, 2005 Page 364 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name W3 W2 W1 W0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 365 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) * CS4WCR Bit 31 to 21 20 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BEN 0 R/W Burst Enable Specification Enables or disables 8-burst access for a 16-bit bus width or 16- burst access for an 8-bit bus width during 16-byte access. If this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. To use a device that does not support 8-burst access or 16-burst access, set this bit to 1. 0: Enables 8-burst access for a 16-bit bus width and 16burst access for an 8-bit bus width. 1: Disables 8-burst access for a 16-bit bus width and 16burst access for an 8-bit bus width. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 16 BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 366 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 12 11 Bit Name SW1 SW0 Initial Value 0 0 R/W R/W R/W Description Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. These bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored Rev. 1.00 Dec. 27, 2005 Page 367 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 5 to 2 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. These bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles SDRAM*: * CS2WCR Bit 31 to 11 10 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 R Reserved These bits are always read as 1. The write value should always be 1. 9 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 7 A2CL1 A2CL0 1 0 R/W R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles Rev. 1.00 Dec. 27, 2005 Page 368 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 6 to 0 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. * CS3WCR Bit 31 to 15 14 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. TRP1 TRP0 0 0 R/W R/W Number of Wait Cycles Waiting Completion of Precharge Specify the number of minimum wait cycles to be inserted to wait the completion of precharge. The setting for areas 2 and 3 is common. (1) From starting auto-charge to issuing the ACTV command for the same bank (2) From issuing the PRE/PALL command to issuing the ACTV command for the same bank (3) To transiting to power-down mode/deep power-down mode (4) From issuing the PALL command at auto-refresh to issuing the REF command (5) From issuing the PALL command at self-refresh to issuing the SELF command 00: 0 cycle 01: 1 cycles 10: 2 cycles 11: 3 cycles 12 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 369 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 11 10 Bit Name TRCD1 TRCD0 Initial Value 0 1 R/W R/W R/W Description Number of Wait Cycles from ACTV Command to READ (A)/WRIT (A) Command Specify the number of minimum wait cycles from issuing the ACTV command to issuing the READ (A)/WRIT (A) command. The setting for areas 2 and 3 is common. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8 7 A3CL1 A3CL0 1 0 R/W R/W CAS Latency for Area 3. Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 370 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 4 3 Initial Bit Name Value TRWL1 TRWL0 0 0 R/W R/W R/W Description Number of Wait Cycles Waiting Start of Precharge Specify the number of minimum wait cycles to be inserted to wait the start of precharge. The setting for areas 2 and 3 is common. (1) This LSI is in non-bank active mode from the issue of the WRITA command to the start of auto-precharge in SDRAM, and issues the ACTV command for the same bank after issuing the WRITA command. Confirm how many cycles are required from the reception of the WRITA command to the start of autoprecharge in each SDRAM data sheet. Set this bit so that the number of cycles is not above the cycles specified by this bit. (2) This LSI is in bank active mode from issuing the WRIT command to issuing the PRE command, and the access to different row address in the same bank is performed. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 371 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 1 0 Bit Name TRC1 TRC0 Initial Value 0 0 R/W R/W R/W Description Number of Idle Cycles from REF Command/Self-refresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles between the commands in the following cases. The setting for areas 2 and 3 is common. (1) From issuing the REF command to issuing the ACTV/REF/MSR command (2) From releasing self-refresh to issuing the ACTV/REF/MSR command 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, TRP1/0, TRCD0/1, TRWL1/0, and TRC1/0 bit settings are common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM. Rev. 1.00 Dec. 27, 2005 Page 372 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) PCMCIA: * CS5BWCR, CS6BWCR Bit 31 to 22 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 20 SA1 SA0 0 0 R/W R/W Space Attribute Specification Specify memory card interface or I/C card interface when the PCMCIA interface is selected. SA1 0: Specifies memory card interface when A25 = 1 1: Specifies I/O card interface when A25 = 1 SA0 0: Specifies memory card interface when A25 = 0 1: Specifies I/O card interface when A25 = 0 19 to 15 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 373 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 14 13 12 11 Initial Bit Name Value TED3 TED2 TED1 TED0 0 0 0 0 R/W R/W R/W R/W R/W Description Delay from Address to RD or WE Assert Specify the delay time from address output to RD or WE assert in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 1.00 Dec. 27, 2005 Page 374 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 10 9 8 7 Initial Bit Name Value PCW3 PCW2 PCW1 PCW0 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5, 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 375 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 3 2 1 0 Initial Bit Name Value TEH3 TEH2 TEH1 TEH0 0 0 0 0 R/W R/W R/W R/W R/W Description Delay from RD or WE Negate to Address Specify the address hold time from RD or WE negate in the PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Burst ROM (Clock Synchronous): * CS0WCR Bit 31 to 18 17 16 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. BW1 BW0 0 0 R/W R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 1.00 Dec. 27, 2005 Page 376 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 15 to 11 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 377 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit 31 to 21 20 19 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. A2ROW1 0 A2ROW0 0 R/W R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17 16 A2COL1 A2COL0 0 0 R/W R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) 15, 14 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low-power SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode Rev. 1.00 Dec. 27, 2005 Page 378 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 12 Initial Bit Name Value SLOW 0 R/W R/W Description Low-Frequency Mode Specifies the output timing of command, address, and write data for SDRAM and the latch timing of read data from SDRAM. Setting this bit makes the hold time for command, address, write and read data extended for half cycle (output or read at the falling edge of CKIO). When this bit set to 1, the hold time for command, address, and write and read data can be extended. This mode is suitable for SDRAM with low-frequency clock. 0: Command, address, and write data for SDRAM is output at the rising edge of CKIO. Read data from SDRAM is latched at the rising edge of CKIO. 1: Command, address, and write data for SDRAM is output at the falling edge of CKIO. Read data from SDRAM is latched at the falling edge of CKIO. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refresh or self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 PDOWN 0 R/W Power-Down Mode Specify whether SDRAM is put in power-down mode or not after the access to memory other than SDRAM is completed. This bit, when set to 1, drives the CKE pin low and places SDRAM in power-down mode by using an access to a memory other than SDRAM as a trigger. 0: Does not place SDRAM in power-down mode after an access to a memory other than SDRAM. 1: Places SDRAM in power-down mode after an access to a memory other than SDRAM. Rev. 1.00 Dec. 27, 2005 Page 379 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 8 Bit Name BACTV Initial Value 0 R/W R/W Description Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be used only in area 3. In this case, the bus width can be selected as 16 or 32 bits. When both areas 2 and 3 are set to SDRAM, specify auto-precharge mode. 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 3 A3ROW1 A3ROW0 0 0 R/W R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 A3COL1 A3COL0 0 0 R/W R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Rev. 1.00 Dec. 27, 2005 Page 380 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/W Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables a CMF interrupt request when the CMF bit of RTCSR is set to 1. 0: Disables the CMF interrupt request 1: Enables the CMF interrupt request 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: B/4 010: B/16 011: B/64 100: B/256 101: B/1024 110: B/2048 111: B/4096 31 to 8 Rev. 1.00 Dec. 27, 2005 Page 381 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Bit 2 1 0 Initial Bit Name Value RRC2 RRC1 RRC0 0 0 0 R/W R/W R/W R/W Description Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: Once 001: Twice 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) 12.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 All 0 R/W 8-bit Counter 31 to 8 Rev. 1.00 Dec. 27, 2005 Page 382 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. If the CMIE bit of the RTCSR is set to 1, an interrupt is requested by this matching signal. This request is maintained until the CMF bit in RTCSR is cleared to 0. Clearing the CMF bit in RTCSR affects only interrupts and does not affect refresh requests. This makes it possible to count the number of refresh requests during refresh by interrupts, and to specify the refresh and interval timer interrupts simultaneously. When the RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 All 0 R/W 8-bit Counter 31 to 8 Rev. 1.00 Dec. 27, 2005 Page 383 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5 12.5.1 Operation Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low level on power-on reset, the endian will become big endian and when MD5 pin is high level on power-on reset, the endian will become little endian. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byteselection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed in accordance with the data bus width of the device and endian. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit. Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation D31 to D24 D23 to D16 D15 to D8 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), D7 to D0 DQMUU DQMUL DQMLU DQMLL Byte access Data at 0 7 to 0 Byte access at 1 Byte access at 2 Byte access at 3 Word Data access at 0 15 to 8 Word access at 2 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Data Data 15 to 8 7 to 0 Longword Data Data Data Data access at 0 31 to 24 23 to 16 15 to 8 7 to 0 Rev. 1.00 Dec. 27, 2005 Page 384 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation D31 to D23 to D15 to D24 D16 D8 D7 to D0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), DQMUU DQMUL DQMLU DQMLL Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Data Data 15 to 8 7 to 0 Data Data 15 to 8 7 to 0 Data 31 to 24 Data 23 to 16 Longword 1st access time at at 0 0 2nd time at 2 Data Data 15 to 8 7 to 0 Assert Assert Rev. 1.00 Dec. 27, 2005 Page 385 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation D31 to D23 to D15 to D7 to D24 D16 D8 D0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), DQMUU DQMUL DQMLU DQMLL Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Word 1st time access at 0 at 0 2nd time at 1 Word 1st time access at 2 at 2 2nd time at 3 Longword 1st time access at 0 at 0 2nd time at 1 3rd time at 2 4th time at 3 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Assert Assert Assert Assert Data 15 to 8 Data 7 to 0 Assert Assert Rev. 1.00 Dec. 27, 2005 Page 386 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), DQMUU DQMUL DQMLU DQMLL Byte access at 0 Byte access at 1 Byte access at 2 Byte access Data at 3 7 to 0 Word access at 0 Word Data access at 2 15 to 8 Longword Data access at 0 31 to 24 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Rev. 1.00 Dec. 27, 2005 Page 387 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation D31 to D23 to D15 to D24 D16 D8 D7 to D0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), DQMUU DQMUL DQMLU DQMLL Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Longword 1st access time at at 0 0 2nd time at 2 Data Data 31 to 24 23 to 16 Assert Assert Rev. 1.00 Dec. 27, 2005 Page 388 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation D31 to D23 to D15 D7 to D24 D16 to D8 D0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), DQMUU DQMUL DQMLU DQMLL Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Word 1st time access at 0 at 0 2nd time at 1 Word 1st time access at 2 at 2 2nd time at 3 Longword 1st time access at 0 at 0 2nd time at 1 3rd time at 2 4th time at 3 Data 15 to 8 Data 7 to 0 Assert Assert Data 15 to 8 Data 7 to 0 Assert Assert Data 15 to 8 Data 23 to 16 Data 31 to 24 Assert Assert Rev. 1.00 Dec. 27, 2005 Page 389 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byteselection pin, see section 12.5.7, Byte-Selection SRAM Interface. Figure 12.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 T2 CKIO A25 to A0 CSn RD/WR Read RD D31 to D0 RD/WR Write WEn(BEn) D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.3 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always Rev. 1.00 Dec. 27, 2005 Page 390 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn (BEn) signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 12.4 and 12.5 show the basic timings of normal space accesses. If the WM bit of the CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 12.4). If the WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 12.5). Rev. 1.00 Dec. 27, 2005 Page 391 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 T2 Tnop T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn(BEn) Write D15 to D0 BS DACKn* WAIT Note: * The waveform for DACKn is when active low is specified. Figure 12.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00 Dec. 27, 2005 Page 392 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn(BEn) Write D15 to D0 BS * DACKn WAIT Note: * The waveform for DACKn is when active low is specified. Figure 12.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00 Dec. 27, 2005 Page 393 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) This LSI **** **** **** 128k x 8-bit SRAM **** **** **** **** **** **** **** **** A18 A2 CSn RD D31 **** A16 A0 CS OE I/O7 I/O0 WE **** **** **** **** D8 WE1(BE1) D7 D0 WE0(BE0) **** D16 WE2(BE2) D15 **** D24 WE3(BE3) D23 **** **** **** A16 A0 CS OE I/O7 I/O0 WE **** **** A16 A0 CS OE I/O7 I/O0 WE **** **** A16 A0 CS OE I/O7 I/O0 WE Figure 12.6 Example of 32-Bit Data-Width SRAM Connection Rev. 1.00 Dec. 27, 2005 Page 394 of 932 REJ09B0269-0100 **** Section 12 Bus State Controller (BSC) This LSI A17 *** *** *** 128 k x 8 bits SRAM A16 A0 CS OE I/O7 *** *** A1 CSn RD D15 *** *** D8 WE1(BE1) D7 *** I/O0 WE *** D0 WE0(BE0) A16 *** A0 CS OE I/O7 *** I/O0 WE Figure 12.7 Example of 16-Bit Data-Width SRAM Connection 128 k x 8 bits SRAM A16 A0 CS OE I/O7 I/O0 WE This LSI A16 ... A0 CSn RD D7 D0 WE0(BE0) Figure 12.8 Example of 8-Bit Data-Width SRAM Connection ... Rev. 1.00 Dec. 27, 2005 Page 395 of 932 REJ09B0269-0100 ... ... *** *** *** Section 12 Bus State Controller (BSC) 12.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access. The areas other than 4, 5A, and 5B have common access wait for read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a normal space access shown in figure 12.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn(BEn) Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. Rev. 1.00 Dec. 27, 2005 Page 396 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 CKIO A25 to A0 CSn RD/WR RD Read Tw Tw Wait states inserted by WAIT signal Twx T2 D 31 to D0 WEn(BEn) Write D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.10 Wait State Timing for Normal Space Access (Wait State Insertion by WAIT Signal) Rev. 1.00 Dec. 27, 2005 Page 397 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 12.11 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn (BEn) are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn(BEn) Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.11 CSn Assert Period Expansion Rev. 1.00 Dec. 27, 2005 Page 398 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.5 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands are shown below. * * * * * * * * * * * NOP Auto-refresh (REF) Self-refresh (SELF) All banks precharge (PALL) Specified bank precharge (PRE) Bank active (ACTV) Read (READ) Read with precharge (READA) Write (WRIT) Write with precharge (WRITA) Write mode register (MRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, refer to section 12.5.1, Endian/Access Size and Data Alignment. Figures 12.12 and 12.13 show examples of the connection of the SDRAM with the LSI. Rev. 1.00 Dec. 27, 2005 Page 399 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) This LSI A15 64-Mbit synchronous SDRAM (1M x 16 bits x 4 banks) A13 A0 CKE CLK CS A2 CKE CKIO CSn ... RAS CAS RD/WR D31 RAS CAS WE I/O15 I/O0 DQMU DQML D16 DQMUU DQMUL D15 ... ... D0 DQMLU DQMLL A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML Figure 12.12 Example of 32-Bit Data-Width SDRAM Connection Rev. 1.00 Dec. 27, 2005 Page 400 of 932 REJ09B0269-0100 ... ... ... ... Section 12 Bus State Controller (BSC) This LSI A14 ... 64-Mbit synchronous SDRAM (1M x 16 bits x 4 banks) A13 A0 CKE CLK CS ... A1 CKE CKIO CSn RAS CAS RD/WR D15 ... RAS CAS WE I/O15 I/O0 DQMU DQML ... D0 DQMLU DQMLL Figure 12.13 Example of 16-Bit Data-Width SDRAM Connection Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0]in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.12 to 12.17 show the relationship between the settings of bits BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on. Rev. 1.00 Dec. 27, 2005 Page 401 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 00 (11 bits) A2/3 COL [1:0] 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Output Pin Function A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A25 A24 A23 A22* 2 A17 A16 A15 A22*2 A21*2 L/H*1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A12 (BA1)*3 A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Specifies bank A21*2 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Specifies address/precharge Address Rev. 1.00 Dec. 27, 2005 Page 402 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 00 (11 bits) A2/3 COL [1:0] 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Output Pin Function A1 A0 A9 A8 A1 A0 Example of connected memory 64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification 3. If the number of 16-Mbit SDRAM (512 kwords x 16 bits x 2 banks: pin with 8-bit column) is two, the bank address specification is not required. Therefore, the bank address should be not used. Unused Rev. 1.00 Dec. 27, 2005 Page 403 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 00 (8 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A23* A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 A17 A16 A23*2 A22* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 2 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused 128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 404 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 01 (9 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24* A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 2 A17 A16 A24*2 A23* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 2 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused 256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 405 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 10 (10 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A27 A26 A25* A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 2 2 A17 A16 A25*2 A24* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 1 2 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 Specifies bank Address Specifies address/precharge Address Rev. 1.00 Dec. 27, 2005 Page 406 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 10 (10 bits) Function Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A2 A1 A0 A12 A11 A10 A2 A1 A0 Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2 A0 Unused Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 407 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 10 (13 bits) A2/3 COL [1:0] 01 (9 bits) Function Unused 2 Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25* A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 2 A17 A25* A24* A14 A13 L/H*1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 Specifies bank Address Specifies address/precharge Address Unused 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 408 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 00 (11 bits) A2/3 COL [1:0] 00 (8 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 A17 A16 A15 A14 A21 A20*2 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Specifies address/precharge Address Unused 16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 409 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-2 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 00 (8 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22* 2 A17 A16 A15 A22*2 A21*2 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank A21*2 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 Address Specifies address/precharge Address Unused 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 410 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.16 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 01 (9 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24 A23* 2 A17 A16 A15 A23*2 A22*2 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank A22*2 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Address Specifies address/precharge Address Unused 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 411 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.16 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-2 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 10 (10 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A27 A26 A25 A24* 2 A17 A16 A15 A24*2 A23*2 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank A23*2 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Address Specifies address/precharge Address Unused 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 412 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.17 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-1 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 10 (13 bits) A2/3 COL [1:0] 01 (9 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24* A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 2 A17 A16 A24*2 A23* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 2 A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 413 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.17 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-2 Setting A2/3 BSZ [1:0] 10 (16 bits) A2/3 ROW [1:0] 10 (13 bits) A2/3 COL [1:0] 10 (10 bits) Function Unused Output Pin of Row Address Column Address Synchronous This LSI Output Output DRAM Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A27 A26 A25* A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 2 A17 A16 A25*2 A24* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Example of connected memory 1 2 A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused 512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Dec. 27, 2005 Page 414 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Burst Read: A burst read occurs in the following cases with this LSI. 1. Access size in reading is larger than data bus width. 2. 16-byte transfer in cache miss. 3. 16-byte transfer in DMAC or E-DMAC (access to non-cachable area) This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. Table 12.18 shows the relationship between the access size and the number of bursts. Table 12.18 Relationship between Access Size and Number of Bursts Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bytes 32 bits 8 bits 16 bits 32 bits 16 bytes Number of Bursts 1 1 2 8 1 1 1 4 Figures 12.14 and 12.15 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1 and TRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM in variable frequencies. Figure 12.15 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READA command is output can be specified using the TRCD1 and TRCD0 bits in CS3WCR. If the TRCD1 and TRCD0 bits specify one cycle or more, a Trw cycle where the NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle Rev. 1.00 Dec. 27, 2005 Page 415 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) where the READA command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the synchronous DRAM. Td1 Tc2 Tr Tc1 Td2 Tc3 Td3 Tc4 Td4 Tde Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.14 Burst Read Basic Timing (Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 416 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde Tap Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.15 Burst Read Wait Specification Timing (Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 417 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Single Read: A read access ends in one cycle when data exists in non-cachable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Figure 12.16 shows the single read basic timing. Tr Tc1 Td1 Tde Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.16 Basic Timing for Single Read (Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 418 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Burst Write: A burst write occurs in the following cases in this LSI. 1. Access size in writing is larger than data bus width. 2. Copyback of the cache 3. 16-byte transfer in DMAC or E-DMAC (access to non-cachable region) This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus. The relationship between the access size and the number of bursts is shown in table 12.18. Figure 12.17 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the TRP1 and TRP0 bits in CS3WCR. Rev. 1.00 Dec. 27, 2005 Page 419 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tr Tc1 Tc2 Tc3 Tc4 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.17 Basic Timing for Burst Write (Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 420 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Single Write: A write access ends in one cycle when data is written in non-cachable region and the data bus width is larger than or equal to access size. Figure 12.18 shows the single write basic timing. Tr CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Trwl Tap Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.18 Basic Timing for Single Write (Auto-Precharge) Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bankactive mode, area 2 should be set to normal space or byte-selection SRAM. When areas 2 and 3 are both set to SDRAM, auto precharge mode must be set. When a bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As synchronous DRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, Rev. 1.00 Dec. 27, 2005 Page 421 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the TRP[1:0] bits in CSnWCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 12.19, a burst read cycle for the same row address in figure 12.20, and a burst read cycle for different row addresses in figure 12.21. Similarly, a single write cycle without auto-precharge is shown in figure 12.22, a single write cycle for the same row address in figure 12.23, and a single write cycle for different row addresses in figure 12.24. In figure 12.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 12.19 or 12.22, followed by repetition of the cycle in figure 12.20 or 12.23. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 12.21 or 12.24 is executed instead of that in figure 12.20 or 12.23. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Rev. 1.00 Dec. 27, 2005 Page 422 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.19 Burst Read Timing (No Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 423 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tnop CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.20 Burst Read Timing (Bank Active, Same Row Address) Rev. 1.00 Dec. 27, 2005 Page 424 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.21 Burst Read Timing (Bank Active, Different Row Addresses) Rev. 1.00 Dec. 27, 2005 Page 425 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tr Tc1 CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.22 Single Write Timing (No Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 426 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tnop Tc1 CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.23 Single Write Timing (Bank Active, Same Row Address) Rev. 1.00 Dec. 27, 2005 Page 427 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tr Tc1 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.24 Single Write Timing (Bank Active, Different Row Addresses) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Autorefreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. Rev. 1.00 Dec. 27, 2005 Page 428 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0] in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the count-up is restarted. Figure 12.25 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to precharged state from active state when some bank is being precharged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the TRP[1:0]bits in CSnWCR. A new command is not issued for the duration of the number of cycles specified by the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is inserted between the Tp cycle and Trr cycle when the setting value of the TRP[1:0] bits in CSnWCR is longer than or equal to 1 cycle. Rev. 1.00 Dec. 27, 2005 Page 429 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp Tpw Trr Trc Trc Trc CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Hi-z Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.25 Auto-Refresh Timing 2. Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the TRP[1:0] bits in CSnWSR. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TRC[1:0] bits in CSnWCR. Rev. 1.00 Dec. 27, 2005 Page 430 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Self-refresh timing is shown in figure 12.26. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode by an interrupt. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Rev. 1.00 Dec. 27, 2005 Page 431 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Trr Trc Trc Trc Trc Trc Hi-z Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.26 Self-Refresh Timing Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. This LSI supports requests by the REFOUT pin for the bus mastership while waiting for the refresh request. The REFOUT pin is asserted low until the bus mastership is acquired. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the self-refresh is completed. Low-Frequency Mode: When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency. Rev. 1.00 Dec. 27, 2005 Page 432 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Figure 12.27 shows the access timing in low-frequency mode. In this mode, commands, addresses, and write data are output in synchronization with the falling edge of CKIO, which is half a cycle delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a cycle faster than the normal timing. This timing allows the hold time of commands, addresses, write data, and read data to be extended. If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. Take the operating frequency and timing design into consideration when making the SLOW bit setting. Tr Tc1 Td1 Tde Tap Tr Tc1 Tnop Trwl Tap CKIO CKE (High) A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.27 Access Timing in Low-Frequency Mode Power-Down Mode: If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the powerdown mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note Rev. 1.00 Dec. 27, 2005 Page 433 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the CKE in order to cancel power-down mode is inserted. Figure 12.28 shows the access timing in power-down mode. Power-down Tnop Tr Tc1 Td1 Tde Tap Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1.Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.28 Access Timing in Power-Down Mode Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'A4FD4000 + X for area 2 synchronous DRAM, and to address H'A4FD5000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, Rev. 1.00 Dec. 27, 2005 Page 434 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a bytesize access to the addresses shown in table 12.19. In this time 0 is output at the external address pins of A12 or later. Table 12.19 Access Address in SDRAM Mode Register Write * Setting for Area 2 (SDMR2) Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address HA4FD4440 HA4FD4460 HA4FD4880 HA4FD48C0 External Address Pin H0000440 H0000460 H0000880 H00008C0 Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address HA4FD4040 HA4FD4060 HA4FD4080 HA4FD40C0 External Address Pin H0000040 H0000060 H0000080 H00000C0 * Setting for Area 3 (SDMR3) Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address HA4FD5440 HA4FD5460 HA4FD5880 HA4FD58C0 External Address Pin H0000440 H0000460 H0000880 H00008C0 Rev. 1.00 Dec. 27, 2005 Page 435 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address HA4FD5040 HA4FD5060 HA4FD5080 HA4FD50C0 External Address Pin H0000040 H0000060 H0000080 H00000C0 Mode register setting timing is shown in figure 12.29. A PALL command (all bank precharge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Rev. 1.00 Dec. 27, 2005 Page 436 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Hi-Z Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.29 Write Timing for SDRAM Mode Register (Based on JEDEC) Low-Power SDRAM: The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which data in a work area other than the specific area can be lost without severe repercussions. For details, refer to the data sheet for the low-power SDRAM to be used. The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the EMRS command. The EMRS command is issued according to the conditions specified in table 12.20. For example, if data H'0YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued to the CS3 space in the following sequence: PALL -> REF x 8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XXX and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Rev. 1.00 Dec. 27, 2005 Page 437 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.20 Output Addresses when EMRS Command is Issued Command to Access be Issued Address CS2 MRS CS3 MRS CS2 MRS +EMRS (with refresh) CS3 MRS +EMRS (with refresh) CS2 MRS +EMRS (without refresh) CS3 MRS +EMRS (without refresh) H'A4FD5XXX H'1YYYYYYY 32 bits H'0000XXX H'YYYYYYY H'A4FD4XXX H'1YYYYYYY 32 bits H'0000XXX H'YYYYYYY H'A4FD5XXX H'0YYYYYYY 32 bits H'0000XXX H'YYYYYYY H'A4FD4XXX H'A4FD5XXX H'A4FD4XXX Write MRS Command EMRS Command Access Data Access Size Issue Address Issue Address H'******** H'******** 16 bits 16 bits H'0000XXX H'0000XXX H'0000XXX H'YYYYYYY H'0YYYYYYY 32 bits Rev. 1.00 Dec. 27, 2005 Page 438 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop Temw EMRS Tnop CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*4 Hi-Z Notes: 1. Address pin to be connected to the BA1 pin of SDRAM. 2. Address pin to be connected to the BA0 pin of SDRAM. 3. Address pin to be connected to the A10 pin of SDRAM. 4. The waveform for DACKn is when active low is specified. Figure 12.30 EMRS Command Issue Timing * Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit of the SDCR is set to 1 while the DEEP and RFSH bits of the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. Rev. 1.00 Dec. 27, 2005 Page 439 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tp CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tdpd Trc Trc Trc Trc Trc Hi-Z Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.31 Transition Timing in Deep Power-Down Mode 12.5.6 Burst ROM (Clock Asynchronous) Interface The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at the falling edge of the CKIO. For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the BW[1:0] bits in CSnWCR is inserted. In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that do not perform the burst operation in the burst ROM (clock asynchronous) interface, access timing is same as a normal space. Rev. 1.00 Dec. 27, 2005 Page 440 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Table 12.21 lists a relationship between bus width, access size, and the number of bursts. Figure 12.32 shows a timing chart. Table 12.21 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width 8 bits BEN Bit Not affected Not affected Not affected 0 1 16 bits Not affected Not affected Not affected 0 1 32 bits Not affected Not affected Not affected Not affected 8 bits 16 bits 32 bits 16 bytes 8 bits 16 bits 32 bits 16 bytes Access Size 8 bits 16 bits 32 bits 16 bytes Number of Bursts 1 2 4 16 4 1 1 2 8 2 1 1 1 4 Number of Accesses 1 1 1 1 4 1 1 1 1 4 1 1 1 1 Rev. 1.00 Dec. 27, 2005 Page 441 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 CKIO A25 to A0 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 CS RD/WR RD D31 to D0 WAIT BS DACK Figure 12.32 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits, 16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2, Access Wait for 2nd Time and after = 1) 12.5.7 Byte-Selection SRAM Interface The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin (WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byteselection SRAM interface is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin, which is different from that for the normal space interface. The basic access timing is shown in figure 12.33. In write access, data is written to the memory according to the timing of the byteselection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. Figure 12.34 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 12.35 shows the access timing when a software wait is specified. Rev. 1.00 Dec. 27, 2005 Page 442 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn(BEn) RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: The waveform for DACKn is when active low is specified. Figure 12.33 Basic Access Timing for Byte-Selection SRAM (BAS = 0) Rev. 1.00 Dec. 27, 2005 Page 443 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn(BEn) RD/WR Read RD D31 to D0 RD/WR Write High RD D31 to D0 BS DACKn* Note: The waveform for DACKn is when active low is specified. Figure 12.34 Basic Access Timing for Byte-Selection SRAM (BAS = 1) Rev. 1.00 Dec. 27, 2005 Page 444 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Th T1 Tw T2 Th CKIO A25 to A0 CSn WEn(BEn) RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: The waveform for DACKn is when active low is specified. Figure 12.35 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only) Rev. 1.00 Dec. 27, 2005 Page 445 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) This LSI A17 ... 64 k x 16 bits SRAM A15 ... A2 CSn RD RD/WR D31 ... A0 CS OE WE I/O15 I/O0 UB LB ... D16 WE3(BE3) WE2(BE2) D15 ... A15 A0 CS OE WE I/O15 I/O0 UB LB ... ... D0 WE1(BE1) WE0(BE0) Figure 12.36 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM 64 k x 16 bits SRAM A16 A1 CSn RD RD/WR D15 D0 WE1(BE1) WE0(BE0) A15 A0 CS OE WE I/O 15 I/O 0 UB LB This LSI Figure 12.37 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Rev. 1.00 Dec. 27, 2005 Page 446 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.8 PCMCIA Interface With this LSI, if address map (2) is selected using the MAP bit in CMNCR, the PCMCIA interface can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying the TYPE[3:0] bits of CSnBCR (n = 5B, 6B) to B'0101. In addition, the SA[1:0] bits of CSnWCR (n = 5B, 6B) assign the upper or lower 32 Mbytes of each area to an IC memory card or I/O card interface. For example, if the SA1 and SA0 bits of the CS5BWCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32 Mbytes of area 5B are used as an IC memory card interface and I/O card interface, respectively. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the BSZ[1:0] bits in CS5BBCR or CS6BBCR. Figure 12.38 shows an example of a connection between this LSI and the PCMCIA card. To enable insertion and removal of the PCMCIA card during system power-on, a three-state buffer must be connected between the LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in the big endian mode is not clearly defined. Consequently, an original definition is provided for the PCMCIA interface in big endian mode in this LSI. Rev. 1.00 Dec. 27, 2005 Page 447 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) This LSI A25 to A0 D7 to D0 D15 to D8 RD/WR CE1A CE2A G DIR PC card (memory I/O) G A25 to A0 D7 to D0 D15 to D8 G DIR CE1 CE2 RD WE ICIORD ICIOWR I/O Port G OE WE/PGM IORD IOWR REG WAIT IOIS16 Card detection circuit WAIT IOIS16 CD1,CD2 Figure 12.38 Example of PCMCIA Interface Connection Basic Timing for Memory Card Interface: Figure 12.39 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA interface, accessing the common memory areas in areas 5 and 6 automatically accesses the IC memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold times for the address pins (A25 to A0) to RD and WE, card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) become insufficient. To prevent this error, the LSI can specify the setup times and hold times for areas 5 and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait can be inserted using the WAIT pin. Figure 12.40 shows the PCMCIA memory bus wait timing. Rev. 1.00 Dec. 27, 2005 Page 448 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS Figure 12.39 Basic Access Timing for PCMCIA Memory Card Interface Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS WAIT Figure 12.40 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Wait = 1, Hardware Wait = 1) Rev. 1.00 Dec. 27, 2005 Page 449 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) If all 32 Mbytes of the memory space are used as an IC memory card interface, the REG signal that switches between the common memory and attribute memory can be generated by a port. If the memory space used for the IC memory card interface is 16 Mbytes or less, the A24 pin can be used as the REG signal by using the memory space as a 16-Mbyte common memory space and a 16-Mbyte attribute memory space. PCMCIA interface area is 32 Mbytes (An I/O port is used as the REG) Area 5 : H'14000000 Attribute memory/common memory Area 5 : H'16000000 I/O space Area 6 : H'18000000 Attribute memory/common memory Area 6 : H'1A000000 I/O space PCMCIA interface area is 16 Mbytes (A24 is used as the REG) Area 5 : H'14000000 Area 5 : H'15000000 Area 5 : H'16000000 H'17000000 Area 6 : H'18000000 Area 6 : H'19000000 Area 6 : H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 12.41 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B10, CS6BWCR.SA[1:0] = B10) Basic Timing for I/O Card Interface: Figures 12.42 and 12.43 show the basic timings for the PCMCIA I/O card interface. The I/O card and IC memory card interfaces can be switched using an address to be accessed. If area 5 of the physical space is specified as the PCMCIA, the I/O card interface can automatically be accessed by accessing the physical addresses from H'16000000 to H'17FFFFFF. If area 6 of the physical space is specified as the PCMCIA, the I/O card interface can automatically be accessed by accessing the physical addresses from H1A000000 to H1BFFFFFF. Note that areas to be accessed as the PCMCIA I/O card must be non-cached if they are logical space (space P2 or P3) areas, or a non-cached area specified by the MMU. Rev. 1.00 Dec. 27, 2005 Page 450 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is brought high in a wordsize I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8 bits and data is accessed twice in 8-bit units in the I/O bus cycle to be executed. The IOIS16 signal is sampled at the falling edge of CKIO in the Tpci0, Tpci0w, and Tpci1 cycles when the TED[3:0] bits are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5 cycles after the CKIO sampling point. The TED[3:0] bits must be specified appropriately to satisfy the setup time from ICIORD and ICIOWR of the PC card to CEn. Figure 12.44 shows the dynamic bus sizing basic timing. Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the IOIS16 signal must be fixed low. Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS Figure 12.42 Basic Timing for PCMCIA I/O Card Interface Rev. 1.00 Dec. 27, 2005 Page 451 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS WAIT IOIS16 Figure 12.43 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Wait = 1, Hardware Wait = 1) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CE1x CE2x RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS WAIT IOIS16 Figure 12.44 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface (TED[3:0] = B0010, TEH[3:0] = B0001, Software Waits = 3) Rev. 1.00 Dec. 27, 2005 Page 452 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.9 Burst ROM (Clock Synchronous) Interface The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR. While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or 16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the same way as normal space access. Note: The burst ROM (clock synchronous) must be accessed as cacheable space. T1 Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2 CKIO Address CSn RD/WR RD D15 to D0 WAIT BS DACKn* Note: The waveform for DACKn is when active low is specified. Figure 12.45 Burst ROM (Clock Synchronous) Access Timing (Burst Length = 8, Wait Cycles inserted in First Access = 2, Wait Cycles inserted in Second and Subsequent Accesses = 1) Rev. 1.00 Dec. 27, 2005 Page 453 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) 12.5.10 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. This LSI has a function that avoids data collisions by inserting wait cycles between continuous access cycles. The number of wait cycles between access cycles can be set by bits IWW[2:0], IWRWD[2:0], IWRWS[2:0], IWRRD[2:0], and IWRRS[2:0] in CSnBCR, and bits DMAIW[2:0] and DMAIWA in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. 2. 3. 4. 5. 6. Continuous accesses are write-read or write-write Continuous accesses are read-write for different spaces Continuous accesses are read-write for the same space Continuous accesses are read-read for different spaces Continuous accesses are read-read for the same space Data output from an external device caused by DMA single transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single transfer is followed by any type of access (DMAIWA = 1) 12.5.11 Bus Arbitration To prevent device malfunction while the bus mastership is transferred between master and slave, the LSI negates all of the bus control signals before bus release. When the bus mastership is received, all of the bus control signals are first negated and then driven appropriately. In this case, output buffer contention can be prevented because the master and slave drive the same signals with the same values. In addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn Rev. 1.00 Dec. 27, 2005 Page 454 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. 2. 3. 4. 16-byte transfer because of a cache miss During copyback operation for the cache Between the read and write cycles of a TAS instruction Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the DMAC or E-DMAC 6. Setting the BLOCK bit in CMNCR to 1 Bits DPRTY[1:0] in CMNCR can select whether or not the bus request is received during DMAC burst transfer. This LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the slave has released the bus, it negates the BACK signal and resumes the bus usage. The SDRAM issues a all bank precharge command (PALL) when active banks exist and releases the bus after completion of a PALL command. The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals (BS, CSn, RAS, CAS, DQMxx, WEn (BEn), RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CKIO. Bus request signals are sampled at the falling edge of CKIO. The sequence for reclaiming the bus mastership from a slave is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The BACK is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 12.46 shows the bus arbitration timing. In an original slave device designed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh correctly, the slave device must be designed to release the bus mastership within the refresh interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership Rev. 1.00 Dec. 27, 2005 Page 455 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus mastership is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the SDRAM refresh. The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing the cycles required for master to slave bus mastership transitions streamlines the system design. CKIO BREQ BACK A25 to A0 D31 to D0 CSn Other bus control signals Figure 12.46 Bus Arbitration Timing 12.5.12 Others Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, the current bus cycle being executed is completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache or if another LSI on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword units because the access request is cancelled by the bus master at manual reset. If a manual reset is requested during cache fill operations, the contents of the cache cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. Note, however, a bus arbitration request by the BREQ signal can't be accepted during manual reset signal assertion. Some flash memories may specify a minimum time from reset release to the first access. To ensure this minimum time, the bus state controller supports a 5-bit reset wait counter (RWTCNT). At power-on reset, the RWTCNT is cleared to 0. After a power-on reset, RWTCNT is counted up synchronously together with CKIO and an external access will not be generated until RWTCNT is counted up to H007F. At a manual reset, RWTCNT is not cleared. RWTCNT cannot be read from or written to. Rev. 1.00 Dec. 27, 2005 Page 456 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the cache bus. Internal bus masters other than the CPU and bus state controller are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory and debugging modules such as a UBC and AUD are connected bidirectionally to the cache bus and internal bus. Access from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. Internal bus masters such as DMAC or E-DMAC other than the CPU can access on-chip memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation on the external interface. For a non-Cacheable area, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus. In a write cycle for the cache area, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. Rev. 1.00 Dec. 27, 2005 Page 457 of 932 REJ09B0269-0100 Section 12 Bus State Controller (BSC) In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. On-Chip Peripheral Module Access: To access an on-chip module register, two or more peripheral module clock (P) cycles are required. Care must be taken in system design. Rev. 1.00 Dec. 27, 2005 Page 458 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Section 13 Direct Memory Access Controller (DMAC) The direct memory access controller (DMAC) can be used in place of the CPU to perform highspeed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 13.1 Features * Six channels (Two channels can receive an external request) * 4-Gbyte physical address space * Data transfer unit is selectable: Byte, Word (two bytes), Longword (four bytes), and 16 bytes (longword x 4) * Maximum transfer count: 16,777,216 transfers (24 bits) * Address mode: Dual address mode and single address mode are supported. * Transfer requests: An external request, on-chip peripheral module request, or auto request can be selected. The following modules can issue an on-chip peripheral module request. SCIF0, SCIF1, SIOF0, SIOF1 * Bus mode: Cycle steal mode or burst mode can be selected. * Channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. * Interrupt request: An interrupt request can be generated to the CPU at the end of the specified counts of data transfer. * External request detection: There are following four types of DREQ input detection. Low-level detection High-level detection Rising-edge detection Falling-edge detection * Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Rev. 1.00 Dec. 27, 2005 Page 459 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Figure 13.1 shows a block diagram of the DMAC. DMAC module On-chip memory Iteration control SAR_n DAR_n On-chip peripheral module Register control Peripheral bus Internal bus DMATCR_n Start-up control CHCR_n DMAOR Request priority control DMA transfer request signal DMA transfer acknowledge signal DMARS0-2 Interrupt controller DEIn External ROM External RAM External I/O (memory mapped) External I/O (with acknowledgement) Bus interface Bus state controller DACK0, DACK1, TEND0, TEND1 DREQ0, DREQ1 Legend : DMA source address register SAR_n : DMA destination address register DAR_n DMATCR_n : DMA transfer count register CHCR_n : DMA channel control register : DMA operation register DMAOR DMARS0-2 : DMA extension resource selector : DMA transfer end interrupt request to the CPU DEIn n : 0, 1, 2, 3, 4, 5 Figure 13.1 Block Diagram of DMAC Rev. 1.00 Dec. 27, 2005 Page 460 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.2 Input/Output Pins The external pins for the DMAC are described below. Table 13.1 lists the configuration of the pins that are connected to external bus. The DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Table 13.1 Pin Configuration Channel Name 0 Abbreviation I/O I O Function DMA transfer request input from external device to channel 0 DMA transfer request acknowledge output from channel 0 to external device DMA transfer end output for channel 0 DMA transfer request input from external device to channel 1 DMA transfer request acknowledge output from channel 1 to external device DMA transfer end output for channel 1 DMA transfer request DREQ0 DMA transfer request DACK0 acknowledge DMA transfer end TEND0 O I O 1 DMA transfer request DREQ1 DMA transfer request DACK1 acknowledge DMA transfer end TEND1 O Rev. 1.00 Dec. 27, 2005 Page 461 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.3 Register Descriptions The DMAC has the following registers. Refer to section 23, List of Registers, for the addresses and access size of these registers. Channel 0: * * * * DMA source address register_0 (SAR_0) DMA destination address register_0 (DAR_0) DMA transfer count register_0 (DMATCR_0) DMA channel control register_0 (CHCR_0) Channel 1: * * * * DMA source address register_1 (SAR_1) DMA destination address register_1 (DAR_1) DMA transfer count register_1 (DMATCR_1) DMA channel control register _1 (CHCR_1) Channel 2: * * * * DMA source address register_2 (SAR_2) DMA destination address register_2 (DAR_2) DMA transfer count register_2 (DMATCR_2) DMA channel control register_2 (CHCR_2) Channel 3: * * * * DMA source address register_3 (SAR_3) DMA destination address register_3 (DAR_3) DMA transfer count register_3 (DMATCR_3) DMA channel control register_3 (CHCR_3) Channel 4: * * * * DMA source address register_4 (SAR_4) DMA destination address register_4 (DAR_4) DMA transfer count register_4 (DMATCR_4) DMA channel control register_4 (CHCR_4) Rev. 1.00 Dec. 27, 2005 Page 462 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Channel 5: * * * * DMA source address register_5 (SAR_5) DMA destination address register_5 (DAR_5) DMA transfer count register_5 (DMATCR_5) DMA channel control register_5 (CHCR_5) Common: * * * * DMA operation register (DMAOR) DMA extension resource selector 0 (DMARS0) DMA extension resource selector 1 (DMARS1) DMA extension resource selector 2 (DMARS2) DMA Source Address Register (SAR) 13.3.1 SAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer. During a DMA transfer, SAR indicates the next source address. When the data is transferred from an external device with the DACK in single address mode, SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. SAR is undefined at reset and retains the current value in standby or module standby mode. 13.3.2 DMA Destination Address Register (DAR) DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer. During a DMA transfer, DAR indicates the next destination address. When the data is transferred to an external device with the DACK in single address mode, DAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. DAR is undefined at reset and retains the current value in standby or module standby mode. Rev. 1.00 Dec. 27, 2005 Page 463 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.3.3 DMA Transfer Count Register (DMATCR) DMATCR is a 32-bit readable/writable registers that specifies the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, DMATCR indicates the remaining transfer count. The upper eight bits of DMATCR will return 0 if read, and should only be written with 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. DMATCR is undefined at reset and retains the current value in standby or module standby mode. 13.3.4 DMA Channel Control Register (CHCR) CHCR is a 32-bit readable/writable register that controls the DMA transfer mode. CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode. Bit 31 to 24 23 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. DO 0 R/W DMA Overrun Selects whether the DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR0 and CHCR1.This bit is reserved and always read as 0 in CHCR2 to CHCR5. The write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 Rev. 1.00 Dec. 27, 2005 Page 464 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 22 Bit Name TL Initial Value 0 R/W R/W Description Transfer End Level Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR0 and CHCR1.This bit is reserved and always read as 0 in CHCR2 to CHCR5. The write value should always be 0. 0: Low-active output of TEND 1: High-active output of TEND 21 to 18 17 All 0 R Reserved These bits are always read as 0. The write value should always be 0. AM 0 R/W Acknowledge Mode Specifies whether the DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, the DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR0 and CHCR1.This bit is reserved and always read as 0 in CHCR2 to CHCR5. The write value should always be 0. 0: DACK output in read cycle (Dual address mode) 1: DACK output in write cycle (Dual address mode) 16 AL 0 R/W Acknowledge Level Specifies the DACK signal output is high active or low active. This bit is valid only in CHCR0 and CHCR1.This bit is reserved and always read as 0 in CHCR2 to CHCR5. The write value should always be 0. 0: Low-active output of DACK 1: High-active output of DACK Rev. 1.00 Dec. 27, 2005 Page 465 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 15 14 Bit Name DM1 DM0 Initial Value 0 0 R/W R/W R/W Description Destination Address Mode Specify whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, the DM1 and DM0 bits are ignored when data is transferred to an external device with the DACK.) 00: Fixed destination address (setting prohibited in 16-byte transfer) 01: Destination address is incremented (+1 in byte transfer, +2 in word transfer, +4 in longword transfer, +16 in 16byte transfer) 10: Destination address is decremented (-1 in byte transfer, -2 in word transfer, -4 in longword transfer; setting prohibited in 16-byte transfer) 11: Reserved (setting prohibited) 13 12 SM1 SM0 0 0 R/W R/W Source Address Mode Specify whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, the SM1 and SM0 bits are ignored when data is transferred from an external device with the DACK.) 00: Fixed source address (setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in byte transfer, +2 in word transfer, +4 in longword transfer, +16 in 16-byte transfer) 10: Source address is decremented (-1 in byte transfer, -2 in word transfer, -4 in longword transfer; setting prohibited in 16-byte transfer) 11: Reserved (setting prohibited) Rev. 1.00 Dec. 27, 2005 Page 466 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 11 10 9 8 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Resource Select Specify which transfer requests will be sent to the DMAC. The change of transfer request source should be done in the state that the DMA enable bit (DE) is cleared to 0. 0000: External request, dual address mode 0010: External request, single address mode External address space external device with DACK 0011: External request, single address mode External device with DACK external address space 0100: Auto request 1000: DMA extension resource selector Other than above: Reserved (setting prohibited) Note: An external request specification is valid only in CHCR0 and CHCR1. None of the external request specification can be selected in CHCR2 to CHCR5. DREQ Level and DREQ Edge Select Specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR0 and CHCR1. These bits are reserved and always read as 0 in CHCR2 to CHCR5. The write value should always be 0. In channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an autorequest is specified, the specification by this bit is invalid. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 7 6 DL DS 0 0 R/W R/W 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode when the DMA transfers data. 0: Cycle steal mode 1: Burst mode Rev. 1.00 Dec. 27, 2005 Page 467 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 4 3 Bit Name TS1 TS0 Initial Value 0 0 R/W R/W R/W Description Transfer Size Specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte size 01: Word (two bytes) size 10: Longword (four bytes) size 11: 16-byte (four longwords) size 2 IE 0 R/W Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when the TE bit is set to 1. 0: Interrupt request is disabled 1: Interrupt request is enabled 1 TE 0 R/(W)* Transfer End Flag The TE bit is set to 1 when data transfer ends when DMATCR becomes to 0. The TE bit is not set to 1 in the following cases. * * DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0. DMA transfer is ended by clearing the DE bit and DME bit in the DMA operation register (DMAOR). Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been interrupted 1: DMA transfer ends by the specified count (DMATCR = 0) [Clearing condition] Writing 0 after reading 1 from this bit Rev. 1.00 Dec. 27, 2005 Page 468 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 0 Bit Name DE Initial Value 0 R/W R/W Descriptions DMA Enable Enables or disables the DMA transfer. In auto-request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF in DMAOR, and AE in DMAOR must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0 as in the case of auto-request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag. 13.3.5 DMA Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register indicates the DMA transfer status. DMAOR is initialized to H0000 at a reset and retains the current value in standby or module standby mode. Bit 15 to 10 9 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. PR1 PR0 0 0 R/W R/W Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5 10: Reserved (setting prohibited) 11: All channel round-robin mode Rev. 1.00 Dec. 27, 2005 Page 469 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag Indicates that an address error occurred by the DMAC. When this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error 1: DMAC address error [Clear conditions] Writing 0 after reading 1 from this bit 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. When this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the DMAC is not in operational, this bit is set to 1 when the NMI interrupt was input. 0: No NMI interrupt 1: NMI interrupt occurs [Clearing conditions] Writing 0 after reading 1 from this bit 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfers on all channels. If the DME bit and the DE bit in CHCR are set to 1, DMA transfer is enabled. Note that transfer is enabled if the TE bit in CHCR and the NMIF and AE bits in DMAOR are all 0. If this bit is cleared, DMA transfers in all the channels can be terminated. 0: Disables DMA transfers on all channels 1: Enables DMA transfers on all channels Note: * Only 0 can be written to clear the flag. Rev. 1.00 Dec. 27, 2005 Page 470 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2) DMARS is a 16-bit readable/writable register that specifies the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the transfer requests of the SCIF0, SCIF1, SIOF0, and SIOF1. When MID and RID other than the values listed in table 13.2 are set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when bits RS3 to RS0 has been set to B'1000 in CHCR0 to CHCR5. Otherwise, even if DMARS has been set, a transfer request source is not accepted. DMARS is initialized to H'0000 at reset and retains the current value in standby or module standby mode. * DMARS0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Bit Name Value C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request register ID for DMA channel 0 (RID) See table 13.2. Transfer request register ID for DMA channel 1 (RID) See table 13.2. Transfer request module ID for DMA channel 0 (MID) See table 13.2. Description Transfer request module ID for DMA channel 1 (MID) See table 13.2. Rev. 1.00 Dec. 27, 2005 Page 471 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) * DMARS1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Bit Name Value C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request module ID for DMA channel 2 (RID) See table 13.2. Transfer request module ID for DMA channel 3 (RID) See table 13.2. Transfer request module ID for DMA channel 2 (MID) See table 13.2. Description Transfer request module ID for DMA channel 3 (MID) See table 13.2. Rev. 1.00 Dec. 27, 2005 Page 472 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) * DMARS2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name C5MID5 C5MID4 C5MID3 C5MID2 C5MID1 C5MID0 C5RID1 C5RID0 C4MID5 C4MID4 C4MID3 C4MID2 C4MID1 C4MID0 C4RID1 C4RID0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request module ID for DMA channel 4 (RID) See table 13.2. Transfer request module ID for DMA channel 5 (RID) See table 13.2. Transfer request module ID for DMA channel 4 (MID) See table 13.2. Description Transfer request module ID for DMA channel 5 (MID) See table 13.2. Rev. 1.00 Dec. 27, 2005 Page 473 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Transfer requests from the various modules are specified by the MID and RID as shown in table 13.2. Table 13.2 DMARS Setting Peripheral Module SCIF0 Setting Value for One Channel (MID + RID) H'21 H'22 SCIF1 H'29 H'2A SIOF0 H'51 H'52 SIOF1 H'55 H'56 B'010101 B'010100 B'001010 MID B'001000 RID B'01 B'10 B'01 B'10 B'01 B'10 B'01 B'10 Function Transmit Receive Transmit Receive Transmit Receive Transmit Receive 13.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In the bus mode, the burst mode or the cycle steal mode can be selected. 13.4.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extension resource selector (DMARS) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. Rev. 1.00 Dec. 27, 2005 Page 474 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Rev. 1.00 Dec. 27, 2005 Page 475 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Figure 13.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated DMATCR = 0? No Yes TE = 1 DEI interrupt request (when IE = 1) NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer end Normal end NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer aborted No No Notes: *1 In auto-request mode, transfer begins when NMIF, AE and TE are all 0 and the DE and DME bits are set to 1. *2 DREQ = level detection in burst mode (external request) or cycle-steal mode. *3 DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 13.2 DMA Transfer Flowchart Rev. 1.00 Dec. 27, 2005 Page 476 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits in the DMA channel control registers 0 to 5 (CHCR_0 to CHCR_5), and the DMA extension resource selectors 0 to 2 (DMARS0 to DMARS2). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR_0 to CHCR_5 and the DME bit of the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_5 AE bit of DMAOR, and the NMIF bit of DMAOR are all 0. External Request Mode: In this mode a transfer is performed at the request signals (DREQ0 or DREQ1) of an external device. Choose one of the modes shown in table 13.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 13.3 Selecting External Request Modes with RS Bits RS3 0 0 RS2 0 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Any External memory, memory-mapped external device External device with DACK Destination Any External device with DACK External memory, memory-mapped external device 1 Whether the DREQ is detected by either the edge or level of the signal input is selected with the DREQ level (DL) bit and DREQ select (DS) bit in CHCR_0 and CHCR_1 as shown in table 13.4. The source of the transfer request does not have to be the data transfer source or destination. Rev. 1.00 Dec. 27, 2005 Page 477 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Table 13.4 Selecting External Request Detection with DL, DS Bits CHCR DL 0 DS 0 1 1 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests. Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 13.5 Selecting External Request Detection with DO Bit CHCR DO 0 1 External Request Overrun 0 Overrun 1 On-Chip Peripheral Module Request Mode: In this mode, the transfer is performed in response to the transfer request signal of an on-chip peripheral module. The DMA transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the SCIF0, SCIF1, SIOF0, and SIOF1 set by DMARS0 to DMARS2. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal. When a transfer request is set to TXI of the SCIF0, the transfer destination must be the SCIF0's transmit data Rev. 1.00 Dec. 27, 2005 Page 478 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) register. Likewise, when a transfer request is set to RXI of the SCIF0, the transfer source must be the SCIF0's receive data register. These conditions also apply to the SCIF1, SIOF0, and SIOF1. Depending on the on-chip peripheral module, the number of receive FIFO triggers can be set as a transfer request. If the receive FIFO trigger condition is not satisfied, data may be remained in the receive FIFO. Therefore, data needs to be read upon completion of the DMA transfer. Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR RS[3:0] 1000 DMARS MID RID DMA Transfer Request DMA Transfer Source Request Signal SCIF0 transmitter SCIF0 receiver SCIF1 transmitter SCIF1 receiver SIOF0 transmitter SIOF0 receiver SIOF1 transmitter SIOF1 receiver TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) TXI (transmit FIFO data empty interrupt) RXI (receive FIFO data full interrupt) Bus Mode Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Source Any SCFRDR_0 Any SCFRDR_1 Any SIOF0/ SIRDR_0 Any SIOF1/ SIRDR_1 Destination SCFTDR_0 Any SCFTDR_1 Any SITDR_0 Any SITDR_1 Any 001000 01 10 001010 01 10 010100 01 10 010101 01 10 13.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The two modes (fixed mode and round-robin mode) can be selected using bits PR0 and PR1 in DMAOR. Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5 These are selected by the PR1 and the PR0 bits in DMAOR. Rev. 1.00 Dec. 27, 2005 Page 479 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Round-Robin Mode: Each time one word, byte, longword or 16-byte unit is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 13.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediately after a reset. When round-robin mode is specified, the bus mode setting of multiple channels does not allow a mixture of cycle steal mode and burst mode. (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Channel 0 becomes bottom priority Priority order afrer transfer CH1 > CH2 > CH3 > CH4 > CH5 > CH0 (2) When channel 1 transfers Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order afrer transfer CH2 > CH3 > CH4 > CH5 > CH0 > CH1 (3) When channel 2 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order afrer transfer CH3 > CH4 > CH5 > CH0 > CH1 > CH2 Post-transfer priority order when there is an CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediate transfer request to channel 5 only Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 5 only, channel 5 becomes bottom priority and the priority of channels 3 and 4, which were higher than channel 5, are also shifted. (4) When channel 5 transfers Initial priority order Priority order afrer transfer CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order does not change Figure 13.3 Round-Robin Mode Rev. 1.00 Dec. 27, 2005 Page 480 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Figure 13.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 (3) Channel 1 3 (2) Channel 0 transfer start Priority order changes 0>1>2>3>4>5 1,3 (4) Channel 0 transfer ends (5) Channel 1 transfer starts 1>2>3>4>5>0 3 (6) Channel 1 transfer ends Priority order changes 2>3>4>5>0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 4>5>0>1>2>3 Figure 13.4 Changes in Channel Priority in Round-Robin Mode Rev. 1.00 Dec. 27, 2005 Page 481 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer, They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 13.7. Table 13.7 Supported DMA Transfers Destination External Device with DACK Not available Single Single Not available Not available MemoryMapped External Device Single Dual Dual Dual Dual On-Chip Peripheral Module X/Y Memory Not available Dual Dual Dual Dual Not available Dual Dual Dual Dual Source External device with DACK External memory Memory-mapped external device On-chip peripheral module X/Y memory External Memory Single Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is not available for on-chip peripheral modules. Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selected) by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 13.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Rev. 1.00 Dec. 27, 2005 Page 482 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 13.5 Data Flow in Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit of the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 13.6 shows an example of DMA transfer timing in dual address mode. Rev. 1.00 Dec. 27, 2005 Page 483 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-Low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 13.6 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary memory, Destination: Ordinary memory) 2. Single Address Mode In single address mode, either the transfer source or transfer destination external device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 13.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. Rev. 1.00 Dec. 27, 2005 Page 484 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) External address bus This LSI DMAC External data bus External memory External device with DACK DACK DREQ Data flow Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figures 13.8 shows example of DMA transfer timing in single address mode. Rev. 1.00 Dec. 27, 2005 Page 485 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) CKIO A25 to A0 CSn WE D31 to D0 DACKn Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CKIO A25 to A0 CSn RD D31 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (ordinary memory) external device with DACK Figure 13.8 Example of DMA Transfer Timing in Single Address Mode Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the channel control register (CHCR). * Cycle-Steal Mode In the cycle-steal mode, the bus mastership is given to another bus master after a one-transferunit (byte, word, long-word, or 16 bytes unit) DMA transfer. When another transfer request occurs, the bus masterships are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. Figure 13.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection Rev. 1.00 Dec. 27, 2005 Page 486 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC CPU Read Write Figure 13.9 DMA Transfer Example in Cycle-Steal Mode (Dual Address, DREQ Low Level Detection) * Burst Mode In the burst mode, once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used when the on-chip peripheral module is the transfer request source. Figure 13.10 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC CPU Read Write Read Write Figure 13.10 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 13.8 shows the relationship between request modes and bus modes by DMA transfer category. Rev. 1.00 Dec. 27, 2005 Page 487 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Table 13.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Size (bits) Usable Channels Dual External device with DACK and external memory External B/C B/C B/C B/C B/C C C C B/C B/C C B/C B/C B/C 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32*3 8/16/32*3 8/16/32* 3 0, 1 0, 1 0 to 5*2 0 to 5*2 0 to 5*2 0 to 5*2 0 to 5*2 0 to 5* 2 External device with DACK and memory- External mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module On-chip peripheral module and on-chip peripheral module X/Y memory and X/Y memory X/Y memory and memory-mapped external device X/Y memory and on-chip peripheral module X/Y memory and external memory Single External device with DACK and external memory External, auto External, auto External, auto All*1 All*1 All* 1 External, auto External, auto All*1 External, auto External 8/16/32/128 8/16/32/128 8/16/32*3 8/16/32/128 8/16/32 8/16/32 0 to 5*2 0 to 5*2 0 to 5*2 0 to 5* 0, 1 0, 1 2 External device with DACK and memory- External mapped external device [Legend] B: Burst, C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, the request-source register must be designated as the transfer source or the transfer destination. 2. If the transfer request is an external request, channels 0 and 1 are only available. 3. Access size permitted for each module must be used when accessing the on-chip peripheral module. Rev. 1.00 Dec. 27, 2005 Page 488 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority: Even if channel 1 is performing burst-mode transfer in priority fixed mode (CH0 > CH1), channel 0 starts transfer immediately when a request is made for transfer on channel 0 with higher priority. If channel 0 is also in burst mode at this time, channel 1 resumes transfer after transfer on channel 0 with higher priority is completed. If channel 0 is in cycle-steal mode, channel 0 with higher priority transfers one transfer unit then allows channel 1 to perform transfers without releasing bus mastership. Next, transfers are performed alternately by channel 0, channel 1, channel 0, channel 1, and so on. This means that a bus state is set for the CPU cycle after completion of the cycle-steal mode transfer is replaced with the burst-mode transfer. (This operation is hereinafter referred to as burst-mode priority execution.) Figure 13.11 shows an example. If multiple channels are conflicting in burst mode, the channel with the highest priority is selected for execution. If multiple channels perform DMA transfers, bus mastership is not released to the bus master until all conflicting burst transfers are completed. CPU DMA CH1 DMA CH1 DMA CH0 CH0 DMA CH1 CH1 DMA CH0 CH0 DMA CH1 DMA CH1 CPU CPU DMAC CH1 Burst mode Cycle-steal mode in DMAC CH0 and CH1 DMAC CH1 Burst mode CPU Priority: CH0 > CH1 CH0: Cycle-steal mode CH1: Burst mode Figure 13.11 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes according to the specification shown in figure 13.11. However, no mixture of channels in cycle-steal mode and channels in burst mode is allowed. 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 12, Bus State Controller (BSC). Rev. 1.00 Dec. 27, 2005 Page 489 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) DREQ Pin Sampling Timing: CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Figure 13.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance CPU Acceptance start Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Rev. 1.00 Dec. 27, 2005 Page 490 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising edge) DACK (High active) Burst acceptance CPU CPU DMAC DMAC Non sensitive period Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance Non sensitive period CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Acceptance start Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance DMAC 3rd acceptance Non sensitive period Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection CKIO End of DMA transfer Bus cycle DREQ DACK (High active) TEND (High active) DMAC CPU DMAC CPU CPU Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection) Rev. 1.00 Dec. 27, 2005 Page 491 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) T1 T2 Taw T1 T2 CKIO Address CS RD Data WEn DACKn (Active low) TENDn (Active low) WAIT Note: TEND is asserted for the last transfer unit of DMA transfers. If a transfer unit is divided into multiple bus cycles and if CS is negated during the bus cycle, TEND is also divided. Figure 13.17 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle = 1, Longword Access to 16-bit Device) Rev. 1.00 Dec. 27, 2005 Page 492 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) 13.5 Usage Note When using the DMAC, note the following: Note on Using TEND Pin: If a DMA transfer is performed under one of the conditions described below and, after completion of the transfer, retransfer is performed on the same channel, the TEND pin is asserted once in the first DMA transfer in retransfer when the retransfer condition satisfies (1) DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0) and the DMA transfer source address (SAR) is in external memory space or (2) in single address mode. Conditions: * DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0) and the DMA transfer source address (SAR) is in external memory space. * DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and the DMA transfer destination address (DAR) is in external memory space. * Single address mode Method of Avoidance: Perform a dummy DMA transfer under one of the settings below. After start of a dummy DMA transfer, clear all bits in the DMA channel control register (CHCR) of the corresponding channel to suspend the dummy DMA transfer forcibly. * DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0) and the DMA transfer source address (SAR) is in external memory space. * DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and the DMA transfer destination address (DAR) is in external memory space. Rev. 1.00 Dec. 27, 2005 Page 493 of 932 REJ09B0269-0100 Section 13 Direct Memory Access Controller (DMAC) Rev. 1.00 Dec. 27, 2005 Page 494 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) Section 14 Timer Unit (TMU) This LSI includes a three-channel (channel 0 to 2) 32-bit timer unit (TMU). 14.1 Features The TMU has the following features: * Each channel is provided with an auto-reload 32-bit down counter * All channels are provided with 32-bit constant registers and 32-bit down counters for an autoreload function that can be read or written to at any time * All channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF) * Allows selection among 4 counter input clocks: P/4, P/16, P/64, and P/256 Note: P is the internal clock for peripheral modules. See section 11, On-Chip Oscillation Circuits, for more information on the clock pulse generator. 14.1.1 Block Diagram Figure 14.1 shows a block diagram of the TMU. Rev. 1.00 Dec. 27, 2005 Page 495 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) P Prescaler Clock controller Ch. 0 TSTR TCR0 Counter controller TCNT0 TCOR0 TUNI0 Interrupt controller Ch. 1 TCR1 Counter controller TCNT1 TCOR1 TUNI1 Interrupt controller Ch. 2 TCR2 Counter controller TCNT2 TCOR2 TUNI2 Interrupt controller Module bus TMU Legend TSTR: Timer start register TCR: Timer control register TCNT: 32-bit timer counter TCOR: 32-bit timer constant register Figure 14.1 TMU Block Diagram Rev. 1.00 Dec. 27, 2005 Page 496 of 932 REJ09B0269-0100 Internal bus Bus interface Section 14 Timer Unit (TMU) 14.2 Register Descriptions The TMU has the following registers. Refer the section 23, List of Registers, for the addresses and access size for these registers. * * * * * * * * * * Timer start register (TSTR) Timer constant register 0 (TCOR0) Timer counter 0 (TCNT0) Timer control register 0 (TCR0) Timer constant register 1 (TCOR1) Timer counter 1 (TCNT1) Timer control register 1 (TCR1) Timer constant register 2 (TCOR2) Timer counter 2 (TCNT2) Timer control register 2 (TCR2) Timer Start Register (TSTR) 14.2.1 The timer start register (TSTR) selects whether to run or halt the timer counters (TCNT) for channels 0 to 2. TSTR is an 8-bit readable/writable register. It is initialized to H'00 by a power-on reset or manual reset. It is initialized in standby mode when the multiplication ratio of PLL circuit 1 (PLL1) is changed or when the MSTP2 bit in STBCR is set to 1. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 STR2 0 R/W Counter Start 2 Selects whether to run or halt TCNT2. 0: TCNT2 count halted 1: TCNT2 counts 1 STR1 0 R/W Counter Start 1 Selects whether to run or halt TCNT1. 0: TCNT1 count halted 1: TCNT1 counts 7 to 3 Rev. 1.00 Dec. 27, 2005 Page 497 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) Bit 0 Bit Name STR0 Initial Value 0 R/W R/W Description Counter Start 0 Selects whether to run or halt TCNT0. 0: TCNT0 count halted 1: TCNT0 counts 14.2.2 Timer Control Registers (TCR) The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has three TCR registers, one for each channel. The TCR registers control the issuance of interrupts when the flag indicating timer counters (TCNT) underflow has been set to 1, and also carry out counter clock selection. The TCR registers are 16-bit readable/writable registers. They are initialized to H'0000 by a power-on reset and manual reset, but are not initialized, and retain their contents, in standby mode. Bit Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 8 UNF 0 R/W Underflow Flag Status flag that indicates occurrence of a TCNT underflow. 0: TCNT has not underflowed [Clearing condition] 0 is written to UNF 1: TCNT has underflowed [Setting condition] TCNT underflows* Note: * Contents do not change when 1 is written to UNF. 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 or 9 Rev. 1.00 Dec. 27, 2005 Page 498 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) Bit 5 Bit Name UNIE Initial Value R/W 0 R/W Description Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1. 0: Interrupt due to UNF (TUNI) is disabled 1: Interrupt due to UNF (TUNI) is enabled 4, 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 Select the TCNT count clock. 000: Count on P/4 001: Count on P/16 010: Count on P/64 011: Count on P/256 100: Reserved (Setting prohibited) 101: Reserved (Setting prohibited) 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited) 14.2.3 Timer Constant Registers (TCOR) The TMU has three timer constant registers (TCOR), one for each channel. The TCOR registers set the value to be set in TCNT when TCNT underflows. The TCOR registers are 32-bit readable/writable registers. They are initialized to H'FFFFFFFF by a power-on reset or manual reset, but are not initialized, and retain their contents, in standby mode. 14.2.4 Timer Counters (TCNT) The TMU has three timer counters (TCNT), one for each channel. The timer counters (TCNT) counts down upon input of a clock. The input clock is selected using the TPSC2 to TPSC0 bits in the timer control registers (TCR). Rev. 1.00 Dec. 27, 2005 Page 499 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) When a TCNT count-down results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in TCR of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the count-down continues from that value. TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode. 14.3 TMU Operation Each of the three channels has a 32-bit TCNT and a 32-bit TCOR. TCNT counts down. The autoreload function enables synchronized counting and counting by external events. 14.3.1 Counter Operation When the STR0 to STR2 bits in TSTR are set to 1, the corresponding TCNT starts counting. When TCNT underflows, the underflow flag (UNF) of the corresponding TCR is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the down-count operation is continued. Count Operation Setting Procedure: An example of the procedure for setting the count operation is shown in figure 14.2. Rev. 1.00 Dec. 27, 2005 Page 500 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) Select operation Select counter clock (1) Set underflow interrupt generation (2) Set timer constant register Initialize timer counter (3) (4) (1) Select the counter clock with the TPSC2 to TPSC0 bits in TCR. (2) Use the UNIE bit in TCR to set whether to generate an interrupt when TCNT underflows. (3) Set a value in TCOR (the cycle is the set value plus 1). (4) Set the initial value in TCNT. (5) Set the STR bit in TSTR to 1 to start operation. Start counting (5) Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 14.2 Setting Count Operation Auto-Reload Count Operation: Figure 14.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR H'00000000 STR0-STR2 UNF Time Figure 14.3 Auto-Reload Count Operation Rev. 1.00 Dec. 27, 2005 Page 501 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) TCNT Count Timing: Set the TPSC2 to TPSC0 bits in TCR to select whether peripheral module clock P or one of the four internal clocks created by dividing it is used (P/4, P/16, P/64, P/256). Figure 14.4 shows the timing. P Internal clock TCNT input clock TCNT N+1 N N-1 Figure 14.4 Count Timing when Internal Clock Is Operating Rev. 1.00 Dec. 27, 2005 Page 502 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) 14.4 Interrupts The interrupt source of TMU is underflow interrupt (TUNI). 14.4.1 Status Flag Set Timing The UNF bit is set to 1 when the TCNT underflows. Figure 14.5 shows the timing. P TCNT Underflow signal UNF TUNI H'00000000 TCOR value Figure 14.5 UNF Set Timing 14.4.2 Status Flag Clear Timing The status flag can be cleared by writing 0 from the CPU. Figure 14.6 shows the timing. TCR write cycle T1 P Peripheral address bus UNF TCR address T2 T3 Figure 14.6 Status Flag Clear Timing Rev. 1.00 Dec. 27, 2005 Page 503 of 932 REJ09B0269-0100 Section 14 Timer Unit (TMU) 14.4.3 Interrupt Sources and Priorities The TMU generates underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event register (INTEVT2) for these interrupts and interrupt processing occurs according to the codes. The relative priorities of channels can be changed using the interrupt controller (see section 4, Exception Handling, and section 8, Interrupt Controller (INTC)). Table 14.1 lists TMU interrupt sources. Table 14.1 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Low Priority High 14.5 14.5.1 Usage Notes Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in TSTR to halt timer counting. 14.5.2 Reading Registers Synchronization processing is performed for timer counting during register reads. When timer counting and register read processing are performed simultaneously, the register value before TCNT counting down (with synchronization processing) is read. Rev. 1.00 Dec. 27, 2005 Page 504 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Section 15 Realtime Clock (RTC) This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. A block diagram of the RTC is shown in figure 15.1. 15.1 Feature The RTC has following features: * Clock and calendar functions (BCD format): Seconds, minutes, hours, date, day of the week, month, and year * 1-Hz to 64-Hz timer (binary format) * Start/stop function * 30-second adjust function * Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt * Periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read * Automatic leap year adjustment Rev. 1.00 Dec. 27, 2005 Page 505 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Externally connected circuit EXTAL2 Oscillator circuit XTAL2 32.768 kHz Prescaler (/ 2) 16.384 kHz Prescaler (/ 128) Reset 128Hz 30second ADJ Peripheral bus R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT Bus interface ATI PRI RSECAR RMINAR CUI Carry detection circuit RHRAR RWKAR RDAYAR RMONAR RYRAR RCR1 RCR2 RCR3 RTC [Legend] R64CNT: 64-Hz counter RSECCNT: Second counter RMINCNT: Minute counter RHRCNT: Hour counter RWKCNT: Day of the week counter RDAYCNT: Date counter RMONCNT: Month counter RYRCNT: Year counter RSECAR: Second alarm register RMINAR: RHRAR: RWKAR: RDAYAR: RMONAR: RYRAR: RCR1: RCR2: RCR3: Minute alarm register Hour alarm register Day of the week alarm register Date alarm register Month alarm register Year alarm register RTC control register 1 RTC control register 2 RTC control register 3 Figure 15.1 RTC Block Diagram Rev. 1.00 Dec. 27, 2005 Page 506 of 932 REJ09B0269-0100 Module bus Interrupt control circuit Comparator Section 15 Realtime Clock (RTC) 15.2 Input/Output Pins Table 15.1 shows the RTC pin configuration. Table 15.1 Pin Configuration Pin Name RTC external clock RTC crystal RTC oscillator power supply RTC oscillator ground Note: Abbreviation I/O EXTAL2 XTAL2 VccQ-RTC VssQ-RTC I O -- -- Function Connects crystal to RTC oscillator*1 Connects crystal to RTC oscillator*1 Dedicated power-supply pin for RTC*2 Dedicated GND pin for RTC 1. Pull up (VccQ-RTC) the EXTAL2 pin, and open (NC) the XTAL2 pin when the realtime clock (RTC) is not used. 2. RTC in this LSI does not operate even if VccQ-RTC is turned on. The crystal oscillator circuit for RTC operates with VccQ-RTC. The control circuit and the RTC counter operate with Vcc (common to the internal circuit). Therefore, all power supplies other than VccQ-RTC should always be turned on even if only RTC operates. 15.3 Register Descriptions The RTC has the following registers. Refer to section 23, List of Registers, for more details on the address and access size. * * * * * * * * * * * * * * * 64-Hz counter (R64CNT) Second counter (RSECCNT) Minute counter (RMINCNT) Hour counter (RHRCNT) Day of week counter (RWKCNT) Date counter (RDAYCNT) Month counter (RMONCNT) Year counter (RYRCNT) Second alarm register (RSECAR) Minute alarm register (RMINAR) Hour alarm register (RHRAR) Day of week alarm register (RWKAR) Date alarm register (RDAYAR) Month alarm register (RMONAR) Year alarm register (RYRAR) Rev. 1.00 Dec. 27, 2005 Page 507 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) * RTC control register 1 (RCR1) * RTC control register 2 (RCR2) * RTC control register 3 (RCR3) 15.3.1 64-Hz Counter (R64CNT) R64CNT indicates the state of the divider circuit (RTC prescaler and R64CNT) between 64 Hz and 1 Hz. R64CNT is reset to H'00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1. R64CNT is an 8-bit read-only register and not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 6 to 0 Bit Name Initial Value 0 R/W R R Description Reserved This bit is always read as 0. 64-Hz Counter Each bit (bits 6 to 0) indicates the state of the RTC divider circuit between 64 and 1Hz. Bit 6: 5: 4: 3: 2: 1: 0: Frequency 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 15.3.2 Second Counter (RSECCNT) RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is performed by a carry for each second of the 64-Hz counter. The range of second can be set is 0 to 59 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. Rev. 1.00 Dec. 27, 2005 Page 508 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) RSECCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 3 to 0 R/W R/W Counter for 10-unit of second in the BCD-code. The range can be set from 0 to 5 (decimal). Counter for 1-unit of second in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.3 Minute Counter (RMINCNT) RMINCNT is used for setting/counting in the BCD-coded minute section. The count operation is performed by a carry for each minute of the second counter. The range of minute can be set is 0 to 59 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. RMINCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0.The write value should always be 0. 6 to 4 3 to 0 R/W R/W Counter for 10-unit of minute in the BCD-code. The range can be set from 0 to 5 (decimal). Counter for 1-unit of minute in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.4 Hour Counter (RHRCNT) RHRCNT is used for setting/counting in the BCD-coded hour section. The count operation is performed by a carry for each 1 hour of the minute counter. Rev. 1.00 Dec. 27, 2005 Page 509 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) The range of hour can be set is 0 to 23 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. RHRCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0.The write value should always be 0. 5, 4 3 to 0 R/W R/W Counter for 10-unit of hour in the BCD-code. The range can be set from 0 to 2 (decimal). Counter for 1-unit of hour in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.5 Day of Week Counter (RWKCNT) RWKCNT is used for setting/counting day of week section. The count operation is performed by a carry for each day of the date counter. The range for day of the week can be set is 0 to 6 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. RWKCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 510 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 R/W Counter for the day of week in the BCD-code. The range can be set from 0 to 6 (decimal). Code 0: 1: 2: 3: 4: 5: 6: Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Rev. 1.00 Dec. 27, 2005 Page 511 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.3.6 Date Counter (RDAYCNT) RDAYCNT is used for setting/counting in the BCD-coded date section. The count operation is performed by a carry for each day of the hour counter. Though the range of date which can be set is 1 to 31 (decimal), it changes with each month and in leap years. Please confirm the correct setting. Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. RDAYCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5, 4 3 to 0 R/W R/W Counter for 10-unit of date in the BCD-code. The range can be set from 0 to 3 (decimal). Counter for 1-unit of date in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.7 Month Counter (RMONCNT) RMONCNT is used for setting/counting in the BCD-coded month section. The count operation is performed by a carry for each month of the date counter. The range of month can be set is 1 to 12 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. RMONCNT is an 8-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 512 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 3 to 0 R/W R/W Counter for 10-unit of month in the BCD-code. The range can be set from 0 to 1 (decimal). Counter for 1-unit of month in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.8 Year Counter (RYRCNT) RYRCNT is used for setting/counting in the BCD-coded year section. The 4 digits of the year are displayed. The count operation is performed by a carry for each year of the month counter. The range for year which can be set is 0000 to 9999 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2 or using a carry flag. RYRCNT is a 16-bit readable/writable register and not initialized by a power-on reset or manual reset, or in standby mode. Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. The year counter value of 0000 is included in the leap year. Bit Bit Name Initial Value R/W R/W R/W R/W R/W Description Counter for 1000-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal) 11 to 8 7 to 4 3 to 0 Counter for 100-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal). Counter for 10-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal). Counter for 1-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal). 15 to 12 Rev. 1.00 Dec. 27, 2005 Page 513 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.3.9 Second Alarm Register (RSECAR) RSECAR is an alarm register corresponding to the second counter RSECCNT of the RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of second alarm which can be set is 0 to 59 (decimal). Errant operation will result if any other value is set. RSECAR is an 8-bit readable/writable register. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Second Alarm Enable Specifies whether comparison of RSECCNT and RSECAR is performed as an alarm condition. 0: Not compared 1: Compared 6 to 4 R/W Setting value for 10-unit of second alarm in the BCD-code. The range can be set from 0 to 5 (decimal). 3 to 0 R/W Setting value for 1-unit of second alarm in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.10 Minute Alarm Register (RMINAR) RMINAR is an alarm register corresponding to the minute counter RMINCNT. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of minute alarm which can be set is 0 to 59 (decimal). Errant operation will result if any other value is set. Rev. 1.00 Dec. 27, 2005 Page 514 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) RMINAR is an 8-bit readable/writable register. The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Minute Alarm Enable Specifies whether comparison of RMINCNT and RMINAR is performed as an alarm condition. 0: Not compared 1: Compared 6 to 4 R/W Setting value for 10-unit of minute alarm in the BCD-code. The range can be set from 0 to 5 (decimal). 3 to 0 R/W Setting value for 1-unit of minute alarm in the BCD-code. The range can be set from 0 to 9 (decimal). 15.3.11 Hour Alarm Register (RHRAR) RHRAR is an alarm register corresponding to the hour counter RHRCNT of the RTC. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of hour alarm which can be set is 0 to 23 (decimal). Errant operation will result if any other value is set. RHRAR is an 8-bit readable/writable register. The ENB bit in RHRAR is initialized by a poweron reset. The remaining RHRAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 515 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Hour Alarm Enable Specifies whether comparison of RHRCNT and RHRAR is performed as an alarm condition. 0: Not compared 1: Compared 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5, 4 R/W Setting value for 10-unit of hour alarm in the BCD-code. The range can be set from 0 to 2 (decimal). Setting value for 1-unit of hour alarm in the BCDcode. The range can be set from 0 to 9 (decimal). 3 to 0 R/W 15.3.12 Day of Week Alarm Register (RWKAR) RWKAR is an alarm register corresponding to the day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of day of the week alarm which can be set is 0 to 6 (decimal). Errant operation will result if any other value is set. RWKAR is an 8-bit readable/writable register. The ENB bit in RWKAR is initialized by a poweron reset. The remaining RWKAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 516 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Day of Week Alarm Enable Specifies whether comparison of RWKCNT and RWKAR is performed as an alarm condition. 0: Not compared 1: Compared 6 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 R/W Day of Week Alarm Code The range can be set from 0 to 6 (decimal). Code 0: 1: 2: 3: 4: 5: 6: Day of the Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday 15.3.13 Date Alarm Register (RDAYAR) RDAYAR is an alarm register corresponding to the date counter RDAYCNT. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/ and RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of date alarm which can be set is 1 to 31 (decimal). Errant operation will result if any other value is set. The RDAYCNT range that can be set changes with some months and in leap years. Please confirm the correct setting. RDAYAR is an 8-bit readable/writable register. The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 517 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Date Alarm Enable Specifies whether comparison of RDAYCNT and RDAYAR is performed as an alarm condition. 0: Not compared 1: Compared 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5, 4 R/W Setting value for 10-unit of date alarm in the BCD-code. The range can be set from 0 to 3 (decimal). Setting value for 1-unit of date alarm in the BCDcode. The range can be set from 0 to 9 (decimal). 3 to 0 R/W 15.3.14 Month Alarm Register (RMONAR) RMONAR is an alarm register corresponding to the month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/ and RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of month alarm which can be set is 1 to 12 (decimal). Errant operation will result if any other value is set. RMONAR is an 8-bit readable/writable register. The ENB bit in RMONAR is initialized by a power-on reset. The remaining RMONAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 518 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 7 Bit Name ENB Initial Value 0 R/W R/W Description Month Alarm Enable Specifies whether comparison of RMONCNT and RMONAR is performed as an alarm condition. 0: Not compared 1: Compared 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 R/W Setting value for 10-unit of month alarm in the BCD-code. The range can be set from 0 to 1 (decimal). Setting value for 1-unit of month alarm in the BCD-code. The range can be set from 0 to 9 (decimal). 3 to 0 R/W 15.3.15 Year Alarm Register (RYRAR) RYRAR is an alarm register corresponding to the year counter RYRCNT. When the YAEN bit in RCR3 is set to 1, a comparison with the RYRCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/ and RMONAR, the counter and alarm register comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of year alarm which can be set is 0000 to 9999 (decimal). Errant operation will result if any other value is set. RYRAR is a 16-bit readable/writable register. The contents are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 1.00 Dec. 27, 2005 Page 519 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit Bit Name Initial Value R/W R/W Description Setting value for 1000-unit of year alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Setting value for 100-unit of year alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Setting value for 10-unit of year alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Setting value for 1-unit of year alarm in the BCDcode. The range can be set from 0 to 9 (decimal). 15 to 12 11 to 8 R/W 7 to 4 R/W 3 to 0 R/W 15.3.16 RTC Control Register 1 (RCR1) RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is an 8-bit readable/writable register. RCR1 is initialized to H'00 by a power-on reset or a manual reset, all bits are initialized to 0 except for the CF flag, which is undefined. When using the CF flag, it must be initialized beforehand. This register is not initialized in standby mode. Bit 7 Bit Name CF Initial Value Undefined R/W R/W Description Carry Flag Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to R64CNT or RSECCNT occurs. A count register value read at this time cannot be guaranteed; another read is required. 0: No count up of R64CNT or RSECCNT. Clearing condition: When 0 is written to CF 1: Count up of R64CNT or RSECCNT. Setting condition: When 1 is written to CF or if the carry of R64CNT or RSECCNT occurs when R64CNT or RSECCNT is read. Rev. 1.00 Dec. 27, 2005 Page 520 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 6 5 4 Bit Name -- -- CIE Initial Value 0 0 0 R/W R R R/W Description Reserved These bits are always read as 0. The write value should always be 0. Carry Interrupt Enable Flag When the carry flag (CF) is set to 1, the CIE bit enables interrupts. 0: A carry interrupt is not generated when the CF flag is set to 1 1: A carry interrupt is generated when the CF flag is set to 1 3 AIE 0 R/W Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1 2 1 0 -- -- AF 0 0 0 R R R/W Reserved These bits are always read as 0. The write value should always be 0. Alarm Flag The AF flag is set to 1 when the alarm time set in an alarm register (only registers with the ENB bit of the corresponding alarm registers and YAEN bit in RCR3 set to 1) matches the clock and calendar time. This flag is cleared to 0 when 0 is written, but holds the previous value when 1 is to be written. 0: Clock/calendar and alarm register have not matched. Clearing condition: When 0 is written to AF 1: Clock/calendar and alarm register have matched. Setting condition: Clock/calendar and alarm register have matched (only registers with the ENB bit and YAEN bit in RCR3 set to 1) Rev. 1.00 Dec. 27, 2005 Page 521 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.3.17 RTC Control Register 2 (RCR2) RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. RCR2 is an 8-bit readable/writable register. It is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a manual reset. It is not initialized in standby mode, and retains its contents. Bit 7 Bit Name PEF Initial Value 0 R/W R/W Description Periodic Interrupt Flag Indicates interrupt generation with the period designated by the PES2 to PES0 bits. When set to 1, PEF generates periodic interrupts. 0: Interrupts not generated with the period designated by the PES bits. Clearing condition: When 0 is written to PEF 1: Interrupts generated with the period designated by the PES bits. Setting condition: When an interrupt is generated with the period designated by the PES0 to PES2 bits or when 1 is written to the PEF flag 6 5 4 PES2 PES1 PES0 0 0 0 R/W R/W R/W Periodic Interrupt Flags These bits specify the periodic interrupt. 000: No periodic interrupts generated 001: Periodic interrupt generated every 1/256 second 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second 101: Periodic interrupt generated every 1/2 second 110: Periodic interrupt generated every 1 second 111: Periodic interrupt generated every 2 seconds Rev. 1.00 Dec. 27, 2005 Page 522 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) Bit 3 Bit Name RTCEN Initial Value 1 R/W R/W Description Controls the operation of the crystal oscillator for the RTC. 0: Halts the crystal oscillator for the RTC. 1: Runs the crystal oscillator for the RTC. 2 ADJ 0 R/W 30-Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit (RTC prescaler and R64CNT) will be simultaneously reset. This bit always reads 0. 0: Runs normally. 1: 30-second adjustment. 1 RESET 0 R/W Reset When 1 is written, initializes the divider circuit (RTC prescaler and R64CNT). This bit always reads 0. 0: Runs normally. 1: Divider circuit is reset. 0 START 1 R/W Start Bit Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. 1: Second/minute/hour/day/week/month/year counter runs normally. Note: The 64-Hz counter always runs unless stopped with the RTCEN bit. Rev. 1.00 Dec. 27, 2005 Page 523 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.3.18 RTC Control Register 3 (RCR3) RCR3 is a register that controls comparison of the BCD-coded year counter RYRCNT and the year alarm register RYRAR of the RTC. RCR3 is an 8-bit readable/writable register. Bit 7 Bit Name YAEN Initial Value 0 R/W R/W Description Year Alarm Enable When this bit is set to 1, comparison of the year alarm register (RYRAR) and the year counter (RYRCNT) is performed. From among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 524 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.4 15.4.1 Operation Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 15.4.2 Setting Time Figure 15.2 shows how to set the time when the clock is stopped. Stop clock, reset divider circuit Write 1 to RESET and 0 to START in the RCR2 register Set seconds, minutes, hour, day, day of the Order is irrelevant week, month, and year Write 1 to START in the RCR2 register Start clock Figure 15.2 Setting Time 15.4.3 Reading Time Figure 15.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. Rev. 1.00 Dec. 27, 2005 Page 525 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) (a) To read the time without using interrupts Disable the carry interrupt Clear the carry flag Read counter register Yes Carry flag = 1? No Read RCR1 and check CF Write 0 to CIE in RCR1 Write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. (b) To use interrupts Enable the carry interrupt Clear the carry flag Read counter register Yes Interrupt generated? No Disable the carry interrupt Write 1 to CIE in RCR1, and write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. Write 0 to CIE in RCR1 Figure 15.3 Reading Time Rev. 1.00 Dec. 27, 2005 Page 526 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.4.4 Alarm Function Figure 15.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. Set the ENB bit or YAEN bit in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is not placed to 0. When the clock and alarm times match, 1 is set in the AF bit in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is set in the AIE bit in RCR1, an interrupt is generated when an alarm occurs. Clock running Set whether to use alarm interrupt Disable interrupt to prevent errorneous interruption.(AIE bit in RCR1 is cleared) Then write 1. Set alarm time Always clear, since the flag may have been set while the alarm time was being set. (Write 0 to AF of RCR1 to clear it. ) Clear alarm flag Monitor alarm time (wait for interrupt or check alarm flag) Figure 15.4 Using Alarm Function Rev. 1.00 Dec. 27, 2005 Page 527 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.4.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 15.2, and the RTC crystal oscillator circuit in figure 15.5. Table 15.2 Recommended Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10 to 22 pF Cout 10 to 22 pF SH7712 EXTAL2 Rf RD XTAL2 XTAL Cin Cout Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k 3. Cin and Cout values include stray capacitance due to the wiring. Take care when using a ground plane. 4. The crystal oscillation settling time depends on the mounted circuit constants, stray capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. Figure 15.5 Example of Crystal Oscillator Circuit Connection Rev. 1.00 Dec. 27, 2005 Page 528 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.5 15.5.1 Usage Notes Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while the START bit = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be stopped before writing to any of the above registers. 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 15.6. A periodic interrupt can be generated periodically at the interval set by the periodic interrupt flag (PES0-PES2) in RCR2. When the time set by the PES0-PES2 has elapsed, the PEF is set to 1. The PEF is cleared to 0 upon periodic interrupt generation or when the periodic interrupt flag (PES0 to PES2) is set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. Set PES0 to PES2, and clear PEF to 0, in RCR2 Set PES, clear PEF Elapse of time set by PES Clear PEF Clear PEF to 0 Figure 15.6 Using Periodic Interrupt Function 15.5.3 Transition to Standby Mode after Setting Register When a transition to standby mode is made after registers in the RTC are set, sometimes counting is not performed correctly. In case the registers are set, be sure to make a transition to standby mode after waiting for two RTC clocks or more. Rev. 1.00 Dec. 27, 2005 Page 529 of 932 REJ09B0269-0100 Section 15 Realtime Clock (RTC) 15.5.4 Usage Note about RTC Power Supply RTC in this LSI does not operate even if VccQ-RTC is turned on. The crystal oscillator circuit for RTC operates with VccQ-RTC. The control circuit and the RTC counter operate with Vcc (common to the internal circuit). Therefore, all power supplies other than VccQ-RTC should always be turned on even if only RTC operates. Rev. 1.00 Dec. 27, 2005 Page 530 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock synchronous serial communication. The SCIF provides a 16-stage FIFO register for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1 Features The SCIF features are listed below. * Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Receive error detection: Parity, framing, and overrun errors Break detection: If a framing error is following by at least one frame at the space "0" (low) level, a break is detected. * Clock synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. Data length: 8 bits Receive error detection: Overrun error * Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. * On-chip baud rate generator allows any bit rate to be selected. SCIS3C3A_000020020900 Rev. 1.00 Dec. 27, 2005 Page 531 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) * Choice of serial clock source: Internal clock from the baud rate generator or external clock from the SCIF0CK and SCIF1CK pins. * There are four interrupt sourcestransmit-FIFO-data-empty, receive-FIFO-data-full, receiveerror, and break. Each source can be requested independently. * The DMA controller (DMAC) can be activated to execute a data transfer in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full. * On-chip modem control functions (CTS0/CTS1 and RTS0/RTS1) * When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. * The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. * On reception a time out error (DR) can be detected * The contents of the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR) are undefined after a power-on or manual reset. Other registers are initialized by a power-on or manual reset, and retain their values in standby mode and in the module standby state. Rev. 1.00 Dec. 27, 2005 Page 532 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Module data bus Bus interface Internal data bus SCFRDR_n (16-stage) SCFTDR_n (16-stage) SCTSR_n RxDn SCRSR_n SCSMR_n SCLSR_n SCFDR_n SCFCR_n SCFSR_n SCSCR_n Transmission/ reception control SCBRR_n Baud rate generator P P/4 P/16 P/64 TxDn Parity generation Parity check SCIFnCK CTSn RTSn Clock External clock TXIn RXIn ERIn BRIn SCIFn [Legend] SCRSR_n: SCFRDR_n: SCTSR_n: SCFTDR_n: SCSMR_n: SCSCR_n: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR_n: SCBRR_n: SCFCR_n: SCFDR_n: SCLSR_n: n: Serial status register Bit rate register FIFO control register FIFO data count register Line status register 0, 1 Figure 16.1 Block Diagram of SCIF Rev. 1.00 Dec. 27, 2005 Page 533 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2 Input/Output Pins Table 16.1 shows the SCIF pin configuration. Table 16.1 Pin Configuration Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin 1 Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation SCIF0CK RxD0 TxD0 CTS0 RTS0 SCIF1CK RxD1 TxD1 CTS1 RTS1 I/O Function Input/output Clock input/output Input Output Input Output Receive data input Transmit data output Transmission clear Transmit request Input/output Clock input/output Input Output Input Output Receive data input Transmit data output Transmission clear Transmit request Note: These pins function as serial pins by making the SCIF operation settings with the C/A bit in SCSMR, TE, RE, CKE1, and CKE0 bits in SCSCR, and MCE bit in SCFCR. Rev. 1.00 Dec. 27, 2005 Page 534 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3 Register Descriptions The SCIF has the following registers. For details on addresses and access sizes of these registers, see section 23, List of Registers. Channel 0: * Serial mode register_0 (SCSMR_0) * Bit rate register_0 (SCBRR_0) * Serial control register_0 (SCSCR_0) * Transmit FIFO data register_0 (SCFTDR_0) * Serial status register_0 (SCFSR_0) * Receive FIFO data register_0 (SCFRDR_0) * FIFO control register_0 (SCFCR_0) * FIFO data count register_0 (SCFDR_0) * Line status register_0 (SCLSR_0) * Receive shift register_0 (SCRSR_0) * Transmit shift register_0 (SCTSR_0) Channel 1: * Serial mode register_1 (SCSMR_1) * Bit rate register_1 (SCBRR_1) * Serial control register_1 (SCSCR_1) * Transmit FIFO data register_1 (SCFTDR_1) * Serial status register_1 (SCFSR_1) * Receive FIFO data register_1 (SCFRDR_1) * FIFO control register_1 (SCFCR_1) * FIFO data count register_1 (SCFDR_1) * Line status register_1 (SCLSR_1) * Receive shift register_1 (SCRSR_1) * Transmit shift register_1 (SCTSR_1) Rev. 1.00 Dec. 27, 2005 Page 535 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive serial data. The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO data register SCFRDR, automatically. SCRSR cannot be directly read or written to by the CPU. 16.3.2 Receive FIFO Data Register (SCFRDR) SCFRDR is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO data register is full (16 data bytes). SCFRDR is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO data register, an undefined value will be returned. When the receive FIFO data register is full of receive data, subsequent serial data is lost. The contents of SCFRDR are undefined after a power-on reset or manual reset. Rev. 1.00 Dec. 27, 2005 Page 536 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.3 Transmit Shift Register (SCTSR) SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data sequentially to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be directly read or written to by the CPU. 16.3.4 Transmit FIFO Data Register (SCFTDR) SCFTDR is an 8-bit 16-stage FIFO data register that stores data for serial transmission. If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR are undefined after a power-on reset or manual reset. 16.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register used to set the SCIF's serial communication format and select the clock source of the baud rate generator. SCSMR can be read or written to by the CPU at all times. SCSMR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Rev. 1.00 Dec. 27, 2005 Page 537 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects asynchronous mode or clock synchronous mode as the SCIF operating mode. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length Selects 7 or 8 bits as the asynchronous mode data length. In clock synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register (SCFTDR) is not transmitted. 5 PE 0 R/W Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clock synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. 0: Parity bit addition and checking disabled 1: Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Rev. 1.00 Dec. 27, 2005 Page 538 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name O/E Initial Value 0 R/W R/W Description Parity Mode Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking in asynchronous mode. The O/E bit setting is invalid in clock synchronous mode, and when parity addition and checking is disabled in asynchronous mode. 0: Even parity* 1: Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. 1 Rev. 1.00 Dec. 27, 2005 Page 539 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Length Selects 1 or 2 bits as the stop bit length. The STOP bit setting is only valid in asynchronous mode. When clock synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. 0: 1 stop bit* 1 2 1: 2 stop bits* Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 Select the clock source for the on-chip baud rate generator. 00: P 01: P/4 10: P/16 11: P/64 Rev. 1.00 Dec. 27, 2005 Page 540 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.6 Serial Control Register (SCSCR) SCSCR performs enabling or disabling of the SCIF transfer operations and interrupt requests, and selection of the serial clock source. SCSCR can be read or written to by the CPU at all times. SCSCR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables generation of a transmit-FIFOdata-empty interrupt (TXI) request when the TDFE flag in SCFSR is set to 1 after the serial transmit data is transferred from SCFTDR to SCTSR and the number of data bytes in the transmit FIFO register is equal to or below the trigger set number. 0: Transmit-FIFO-data-empty interrupt (TXI) request disabled* 1: Transmit-FIFO-data-empty interrupt (TXI) request enabled Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. Rev. 1.00 Dec. 27, 2005 Page 541 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name RIE Initial Value 0 R/W R/W Description Receive Interrupt Enable Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, or break-interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1. 0: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break-interrupt (BRI) request disabled* 1: Receive-data-full interrupt (RXI) request, receiveerror interrupt (ERI) request, and break-interrupt (BRI) request enabled Note: * An RXI request can be cleared by reading 1 from the RDF flag or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. The ERI and BRI requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or clearing the RIE and REIE bits to 0. 5 TE 0 R/W Transmit Enable Enables or disables the start of serial transmission by the SCIF. 0: Transmission disabled 1: Transmission enabled* Note: * SCSMR and SCFCR settings must be made, the transmit format decided, and the transmit FIFO reset, before the TE bit is set to 1. Rev. 1.00 Dec. 27, 2005 Page 542 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name RE Initial Value 0 R/W R/W Description Receive Enable Enables or disables the start of serial reception by the SCIF. 0: Reception disabled*1 1: Reception enabled* 2 Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their state. 2. SCSMR and SCFCR settings must be made, the receive format decided, and the receive FIFO reset, before the RE bit is set to 1. 3 REIE 0 R/W Receive Error Interrupt Enable Enables or disables generation of receive-error interrupt (ERI) request and break interrupt (BRI) request. The REIE bit setting is available when the RIE bit is cleared to 0. 0: Receive-error interrupt (ERI) request and break interrupt (BRI) request disabled* 1: Receive-error interrupt (ERI) request and break interrupt (BRI) request enabled Note: * A receive-error interrupt (ERI) request and break interrupt (BRI) request can be cleared by reading 1 from the ER, BRK, and ORER flags, then clearing the flags to 0, or by clearing the RIE and REIE bits to 0. Even if the RIE bit is cleared to 0, setting the REIE bit to 1 enables generation of the ERI and BRI requests. This setting is achieved to notify the ERI and BRI requests to the interrupt controller at the DMAC transfer. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 543 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 Select the SCIF clock source and enable or disable clock output from the SCIFnCK pin. The combination of the CKE1 bit and CKE0 bit determines whether the SCIFnCK pin is set as a serial clock output pin or a serial clock input pin. The setting of the CKE0 bit is available in internal clock operation (CKE1 = 0). In the case of external clock operation (CKE1 = 1), the setting of the CKE0 bit is not available. The CKE1 and CKE0 bits must be set before the SCIF operating mode is selected by SCSMR. * Asynchronous mode 00: Internal clock/SCIFnCK pin functions as input pin (input signal ignored) 01: Internal clock/SCIFnCK pin functions as clock 2 output* 1-*1: External clock/SCIFnCK pin functions as clock 3 input* * Clock synchronous mode 00: Internal clock/SCIFnCK pin functions as synchronous clock output 01: Internal clock/SCIFnCK pin functions as synchronous clock output 1-*1: External clock/SCIFnCK pin functions as synchronous clock input Notes: 1. When CKE1 = 1, the value of CKE0 is don't care. 2. The output clock frequency is 16 times the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev. 1.00 Dec. 27, 2005 Page 544 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The lower 8 bits specify the status flags that indicate the SCIF operating status. The upper 8 bits indicate the receive error number of data in the receive-FIFO register. SCFSR can be read or written to by the CPU at all times. However, 1 cannot be written to the ER, TEND, TDFE, BRK, RDF, and DR flags. Also note that in order to clear these flags to 0, they must be read as 1 beforehand. The FER and PER flags are read-only flags and cannot be modified. SCFSR is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Bit 15 14 13 12 Bit Name PER3 PER2 PER1 PER0 Initial Value 0 0 0 0 R/W R R R R Description Parity Error Number 3 to 0 Indicate the number of data bytes, in which parity errors are generated, in receive data stored in SCFRDR. After setting the ER bit in SCFSR, the values of bits 15 to 12 indicate the number of parity error generated data. When all 16 bytes of receive data in SCFRDR has parity errors, the PER3 to PER0 bits indicate 0. Framing Error Number 3 to 0 Indicate the number of data bytes, in which framing errors are generated, in receive data stored in SCFRDR. After setting the ER bit in SCFSR, the values of bits 11 to 8 indicate the number of framing error generated data. When all 16 bytes of receive data in SCFRDR has framing errors, the FER3 to FER0 bits indicate 0. 11 10 9 8 FER3 FER2 FER1 FER0 0 0 0 0 R R R R Rev. 1.00 Dec. 27, 2005 Page 545 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 7 Bit Name ER Initial Value 0 R/W R/(W)* Description Receive Error Indicates that a framing error or parity error 1 occurred during reception.* 0: No framing error or parity error occurred during reception [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ER after reading ER = 1 1: A framing error or parity error occurred during reception [Setting conditions] * When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception 2 ends, and the stop bit is 0* * When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCFSR can be used to determine whether there is a receive error in the data read from SCFRDR. 2. When the stop length is 2 bits, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev. 1.00 Dec. 27, 2005 Page 546 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name TEND Initial Value 1 R/W R/(W)* Description Transmit End Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended. 0: Transmission is in progress [Clearing conditions] * When the TEND flag is cleared to 0 after the transmit data is written to SCFTDR and TEND = 1 is read When data is written to SCFTDR by the DMAC * 1: Transmission has been ended [Setting conditions] * * * Power-on reset or manual reset The TE bit in SCSCR is cleared to 0 When there is no transmit data in SCFTDR on transmission of the last bit of 1-byte serial transmit character Rev. 1.00 Dec. 27, 2005 Page 547 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name TDFE Initial Value 1 R/W R/(W)* Description Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has been equal to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in SCFCR, and new transmit data can be written to SCFTDR. 0: A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] * When transmit data exceeding the transmit trigger set number is written to SCFTDR, and 0 is written to the TDFE bit after reading TDFE = 1 When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC * 1: The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR transmit data bytes is equal to or below the transmit trigger set number as the result of a transmit operation* Note: * As SCFTDR is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR is indicated by the upper bits in SCFDR. Rev. 1.00 Dec. 27, 2005 Page 548 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name BRK Initial Value 0 R/W R/(W)* Description Break Detect In asynchronous mode, indicates that a receive data break signal has been detected or not. 0: A break signal has not been received [Clearing conditions] * * Power-on reset or manual reset When 0 is written to BRK after reading BRK = 1 1: A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space "0" level (low level) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR. When the break ends and the receive signal returns to mark "1", receive data transfer is resumed. 3 FER 0 R Framing Error In asynchronous mode, indicates that there is a framing error or not in the data read from SCFRDR. 0: There is no framing error in the receive data read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no framing error in SCFRDR read data 1: There is a framing error in the receive data read from SCFRDR [Setting condition] When there is a framing error in SCFRDR read data Rev. 1.00 Dec. 27, 2005 Page 549 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name PER Initial Value 0 R/W R Description Parity Error In asynchronous mode, indicates that there is a parity error or not in the data read from SCFRDR. 0: There is no parity error in the receive data read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no parity error in SCFRDR read data 1: There is a parity error in the receive data read from SCFRDR [Setting condition] When there is a parity error in SCFRDR read data Rev. 1.00 Dec. 27, 2005 Page 550 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name RDF Initial Value 0 R/W R/(W)* Description Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. 0: The number of receive data bytes in SCFRDR is less than the receive trigger set number [Clearing conditions] * * Power-on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR is less than the receive trigger set number, and 0 is written to RDF after reading RDF = 1 When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR is less than the receive trigger set number * 1: The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If data is read when SCFRDR is empty, an undefined value will be returned. The number of receive data bytes in SCFRDR is indicated by the lower bits in SCFDR. Rev. 1.00 Dec. 27, 2005 Page 551 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 0 Bit Name DR Initial Value 0 R/W R/(W)* Description Receive Data Ready In asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received. 0: Reception is in progress or has ended successfully and there is no receive data left in SCFRDR [Clearing conditions] * * Power-on reset or manual reset When all the receive data in SCFRDR has been read, and 0 is written to DR after reading DR = 1 When all the receive data in SCFRDR is read by the DMAC * 1: No further receive data has arrived [Setting condition] When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: * Corresponds to 1.5 frame time when the format of 8-bit length and 1 stop bit is used. etu: Elementary time unit (time for transfer of 1 bit) Note: * Only 0 can be written for clearing the flags. Rev. 1.00 Dec. 27, 2005 Page 552 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can be read or written to by the CPU at all times. SCBRR is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. The SCBRR setting is found from the following equation. Asynchronous mode: N= P 64x22n-1 x B x 106 - 1 Clock synchronous mode: N= P 8 x 22n-1 x B x 106 - 1 Where B: N: P: n: Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See table 16.2 for the relation between n and the clock.) Table 16.2 Relationship between n and Clock SCSMR Setting n 0 1 2 3 Clock P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: Rev. 1.00 Dec. 27, 2005 Page 553 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) P x 106 Error (%) = - 1 x 100 2n-1 (N + 1) x B x 64 x 2 16.3.9 FIFO Control Register (SCFCR) SCFCR performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can be read or written to by the CPU at all times. SCFCR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Bit 15 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R/W R/W R/W RTS Output Active Trigger 2 to 0 The RTS signal goes high when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown in below. RTS active trigger: 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 Rev. 1.00 Dec. 27, 2005 Page 554 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 7 6 Bit Name RTRG1 RTRG0 Initial Value 0 0 R/W R/W R/W Description Receive FIFO Data Number Trigger 1 and 0 Set the number of receive data bytes that sets the RDF flag in SCFSR. The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown in below. Asynchronous mode 00: 1 01: 4 10: 8 11: 14 Clock synchronous mode 00: 1 01: 2 10: 8 11: 14 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Number Trigger 1 and 0 Set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when, as the result of a transmit operation, the number of transmit data bytes in SCFTDR is equal to or below the trigger set number shown in below. 00: 8 (8) 01: 4 (12) 10: 2 (14) 11: 0 (16) Note: The values in parentheses are the number of empty bytes in SCFTDR when the flag is set. 3 MCE 0 R/W Modem Control Enable Enables modem control signals CTS and RTS. This bit is valid only in asynchronous mode. 0: Modem signal disabled* 1: Modem signal enabled Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Rev. 1.00 Dec. 27, 2005 Page 555 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name TFRST Initial Value 0 R/W R/W Description Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset. 0 LOOP 0 R/W Loopback Test Internally connects the transmit output pin (TxD) and receive input pin (RxD), and RTS pin and CTS pin, enabling loopback testing. 0: Loopback test disabled 1: Loopback test enabled 16.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and SCFRDR. Bits 12 to 8 show the number of transmit data bytes in SCFTDR, and bits 4 to 0 show the number of receive data bytes in SCFRDR. SCFDR can be read by the CPU at all times. SCFDR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Rev. 1.00 Dec. 27, 2005 Page 556 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 10 9 8 7 to 5 T4 T3 T2 T1 T0 0 0 0 0 0 All 0 R R R R R R Bits 12 to 8 in SCFDR show the number of untransmitted data bytes in SCFTDR. A value of H'00 means that there is no transmit data, and a value of H'10 means that SCFTDR is full of transmit data. Reserved These bits are always read as 0. The write value should always be 0. 4 3 2 1 0 R4 R3 R2 R1 R0 0 0 0 0 0 R R R R R Bits 4 to 0 in SCFDR show the number of receive data bytes in SCFRDR. A value of H'00 means that there is no receive data, and a value of H'10 means that SCFRDR is full of receive data. Rev. 1.00 Dec. 27, 2005 Page 557 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.11 Line Status Register (SCLSR) SCLSR is a 16-bit register that indicates whether an overrun error occurs or not during reception. Bit 15 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred during reception and reception is ended abnormally. 0: Reception is in progress, or reception has 1 ended successfully* [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ORER after reading ORER =1 1: An overrun error occurred during reception*2 [Setting condition] When serial reception is completed while the receive FIFO is full Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Dec. 27, 2005 Page 558 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.4 16.4.1 Operation Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and in clock synchronous mode, in which synchronization is achieved with clock pulses. 16-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. Also, the RTS and CTS signals are included as modem control signals. Transfer format is selected by SCSMR. This is shown in table 16.3. The SCIF clock source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. This is shown in table 16.4. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, overrun errors, receive-FIFO-data-full state, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * The SCIF clock source: Choice of internal or external clock When internal clock is selected: The SCIF operates on the baud rate generator clock. When external clock is selected: Clock with frequency16 times the bit rate must be input. (The on-chip baud rate generator is not used.) Clock synchronous Mode * Transfer format: Fixed to 8-bit data * Detection of overrun errors during reception * The SCIF clock source: Choice of internal or external clock When internal clock is selected: The SCIF operates on the baud rate generator clock and outputs the synchronous clock When external clock is selected: The SCIF operates on the input synchronous clock. The onchip baud rate generator is not used. Rev. 1.00 Dec. 27, 2005 Page 559 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.3 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings Bit 7: Bit 6: Bit 5: Bit 3: STOP C/A CHR PE 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Clock synchronous mode 8-bit data No Yes 7-bit data No Yes Mode Asynchronous mode The SCIF Transfer Format Parity Data Length Bit 8-bit data No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No Table 16.4 SCSMR and SCSCR Settings for the SCIF Clock Source Selection SCSMR Bit 1: Bit 7: C/A CKE1 0 0 SCSCR Bit 0: CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clock synchronous mode Internal Clock Source Mode SCIFnCK Pin Function SCIF does not use the SCIFnCK pin Outputs a clock with frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the synchronous clock Asynchronous Internal mode External External Inputs the synchronous clock Rev. 1.00 Dec. 27, 2005 Page 560 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.2 Serial Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial communication character consists of a start bit (low), data (LSB first), parity bit (high/low), and stop bit (high), in this order. In asynchronous mode, the SCIF synchronizes at the falling edge of the start bit during reception. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Therefore, communication data is latched at the center of each bit. Idle state (mark state) 1 1 Serial data 0 Start bit 1 bit D0 D1 D2 D3 D4 D5 D6 D7 0/1 Parity bit 1 bit or no bit 1 1 Transmit/Receive data Stop bit 1 bit or 2 bits 7 bits or 8 bits One unit of communication data (character or frame) Figure 16.2 Data Format in Asynchronous Communication (Example of 8-Bit Data with Parity and 2 Stop Bits) Rev. 1.00 Dec. 27, 2005 Page 561 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transfer Format: Table 16.5 shows the transfer formats that can be used in asynchronous mode. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 16.5 Serial Transfer Formats SCSMR Settings CHR 0 PE 0 STOP 0 1 1 0 1 1 0 0 1 1 0 1 S: Start bit STOP: Stop bit P: Parity bit 1 S S S S S S S S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data STOP STOP STOP P P STOP STOP STOP STOP STOP P P STOP STOP STOP Clock: The SCIF transfer clock is set by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details, see table 16.4. When an external clock is input to the SCIFnCK pin, the clock with frequency 16 times the bit rate must be input. When the SCIF operates on an internal clock, it can output a clock from the SCIFnCK pin. At this time output clock frequency is 16 times the bit rate. Rev. 1.00 Dec. 27, 2005 Page 562 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transfer Operations: The SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND bit in SCFSR has been set to 1. Clearing to 0 can also be performed during transmission, but the data being transmitted will go to the high-impedance state after the clearance. Before setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR. When an external clock is used, the clock should not be stopped during operation including initialization because its operation becomes unreliable. Figure 16.3 shows a sample the SCIF initialization flowchart. Rev. 1.00 Dec. 27, 2005 Page 563 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Initialization 1. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. 2. Set the transfer format in SCSMR. 3. Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, TIE, and REIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR to B'00 (Internal clock/ SCIFnCK pin is input pin (input signal is ignored)) (leaving TE, RE, TIE, and RIE bitscleared to 0) Set C/A bit in SCSMR to 0, and set transfer format Set value in SCBRR Wait No 1-bit interval elapsed? Yes Set RTRG1, RTRG0, TTRG1, and TTRG0 bits in SCFCR. Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set RIE, TIE, and REIE bits End Figure 16.3 Sample the SCIF Initialization Flowchart Serial Data Transmission: Figure 16.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Rev. 1.00 Dec. 27, 2005 Page 564 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Start of transmission Read TDFE bit in SCFSR No TDFE = 1? Yes 1. SCIF status check and transmit data write: Read the serial status register (SCFSR) and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of data bytes that can be written is 16 - (transmit trigger set number). 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the port data register (DR) to 0 before clearing the TE bit in SCSCR to 0, and then specify the TxD pin as an output port by the PFC. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR. Write (16 - transmit trigger set number) bytes of transmit data to SCFTDR, read 1 from TDFE bit and TEND flag in SCFSR, then clear to 0 No All data transmitted? Yes Read TEND bit in SCFSR No TEND = 1? Yes Break output? Yes No Clear port DR to 0 Clear TE bit in SCSCR to 0 Specify TxD pin as output port by PFC End of transmission Figure 16.4 Sample Serial Transmission Flowchart Rev. 1.00 Dec. 27, 2005 Page 565 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 16 - (transmit trigger set number). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One 0-bit is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1-bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Rev. 1.00 Dec. 27, 2005 Page 566 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.5 shows an example of the operation for transmission in asynchronous mode. Start bit 1 Serial data Data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 Idle state (mark state) 0 1 TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 and then cleared to 0 by TXI interrupt handler One frame TXI interrupt request Figure 16.5 Example of Transmit Operation (Example of 8-Bit Data with Parity and 1 Stop Bit) Rev. 1.00 Dec. 27, 2005 Page 567 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figures 16.6 and 16.7 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, and BRK flags in SCFSR and ORER flag in SCLSR Yes ER, DR, BRK, or ORER = 1? No 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR and ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. 2. SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading the lower bits of SCFDR. Error handling Read RDF flag in SCFSR No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Figure 16.6 Sample Serial Reception Flowchart (1) Rev. 1.00 Dec. 27, 2005 Page 568 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored. Yes Overrun error handling No ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR Clear DR, ER, and BRK flags in SCFSR and ORER flag in SCLSR to 0 End Figure 16.7 Sample Serial Reception Flowchart (2) Rev. 1.00 Dec. 27, 2005 Page 569 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR. C. Overrun error check: The SCIF checks that the ORER flag is cleared to 0 and an overrun error does not occur. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: Reception continues when a receive error (a framing error or parity error) occurs. 4. If the RIE bit in SCSCR is set to 1 when the RDF flag or DR flag changes to 1, a receiveFIFO-data-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK flag or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 16.8 shows an example of the operation for reception in asynchronous mode. Rev. 1.00 Dec. 27, 2005 Page 570 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 1 Serial data Start bit Data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 Idle state (mark state) 0 1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.8 Example of SCIF Receive Operation (Example of 8-Bit Data with Parity and 1 Stop Bit) Modem Function: When using a modem function, transmission can be stopped and started again according to the CTS input value. When the CTS is set to 1 during transmission, the data enters a mark state after transmitting one frame. When CTS is set to 0, the next transmit data is output starting with a start bit. Start bit Transmit data TxD Parity Stop bit bit Start bit 0 D0 D1 D6 D7 0/1 0 D0 D1 D6 D7 0/1 CTS Transmission stops when CTS goes high Transmission starts again when CTS goes low Figure 16.9 CTS Control Operation Rev. 1.00 Dec. 27, 2005 Page 571 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) When using a modem function and the receive FIFO (SCFRDR) is at least the number of the RTS output trigger, the RTS signal goes high. Start bit Receive data RxD Parity Stop bit bit 0 D0 D1 D6 D7 0/1 RTS RTS goes high when receive data is at least number of RTS output trigger RTS goes low when receive data is less than number of RTS output trigger Figure 16.10 RTS Control Operation 16.4.3 Serial Operation in Clock Synchronous Mode In clock synchronous mode, the SCIF transmits and receives data synchronizing with clock pulses. This mode is suitable for high-speed serial communication. In the SCIF, the transmitter and receiver are independent. Therefore, by sharing the same clock, full-duplex communication can be performed. Figure 16.11 shows the general format of clock synchronous serial communication. One unit of transfer data (character or frame) * Serial clock * LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care Note: * High except in continuous transmission/reception Figure 16.11 Data Format in Clock Synchronous Communication In clock synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In serial communication, each character is output starting with the LSB and ending with the MSB. After the MSB is output, the communication line remains in the state of the MSB. Rev. 1.00 Dec. 27, 2005 Page 572 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) In clock synchronous mode, the SCIF receives data in synchronization with the rise of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity bit is added. Clock: An internal clock generated by the on-chip baud rate generator or an external synchronous clock input from the SCIFnCK pin can be selected, according to the setting of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. For details, see table 16.4. When the SCIF is operated on an internal clock, synchronous clock is output from the SCIFnCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. If an internal clock is selected when only reception is performed, clock pulse is output continuously until the number of data bytes in the receive FIFO reaches the receive trigger set number while the RE bit in SCSCR is 1. Data Transfer Operations: The SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the mode, communication format etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized. Note that the RDF, PER, FER, and ORER flags and contents of SCFRDR are retained even if the RE bit is cleared to 0. Rev. 1.00 Dec. 27, 2005 Page 573 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.12 shows a sample the SCIF initialization flowchart. Start Initialization Clear TE and RE bits in SCSCR to 0 1. Keep the TE and RE bits cleared to 0 until initialization has been completed. 2. Set the CKE1 and CKE0 bits. 3. Set the transfer or receive format in SCSMR. 4. Write a value corresponding to the bit rate in SCBRR. (Not necessary if an external clock is used.) After this setting wait for at least 1-bit interval. 5. Set the external pins. Specifies the pins as RxD input in reception and TxD output in transmission. Set the SCIFnCK input/output according to the CKE1 and CKE0 settings. 6. Set the TE bit or RE bit in SCSCR to 1. Also, set the TIE, RIE, and REIE bits. At this time, the TxD, RxD, and SCIFnCK pins can be used. In transmission, the TxD pin is in the mark state. When reception in clock synchronous mode and synchronous clock output (clock master) are selected, a clock is output from the SCIFnCK pin. Set TFRST and RFRST bits in SCFCR to 1 and clear buffer of FIFO Read BRK, DR, and ER flags in SCFSR and clear the flags by writing 0 Set CKE1 and CKE0 bits in SCSCR (TE, RE, TIE, and RIE bits are cleared to 0) Set transmit or receive format in SCSMR Set value in SCBRR Wait No 1-bit interval elapsed? Yes Set RTRG1, RTRG0, TTRG1, and TTRG0 bits in SCFCR. Clear TFRST and RFRST bits to 0. Set external pins (SCIFnCK, TxD, RxD) Set TE and RE bits in SCSCR to 1 and set RIE, TIE, and REIE bits End Figure 16.12 Sample the SCIF Initialization Flowchart Rev. 1.00 Dec. 27, 2005 Page 574 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission: Figure 16.13 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Initialization 1. SCIF initialization: See figure 16.3, Sample SCIF Initialization Flowchart. 2. SCIF status check and transmit data write: Read SCFSR, check that the TDFE flag is set to 1, then write transmit data in SCFTDR and clear the TDFE flag to 0. 3. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data in SCFTDR and clear the TDFE flag to 0. Start transmission Read TDFE bit in SCFSR No TDFE = 1? Yes Write transmit data in SCFTDR and clear TDFE and TEND bits in SCFSR to 0 No All data transmitted? Yes Read TEND bit in SCFSR No TEND = 1? Yes Clear TE bit in SCSCR to 0 End transmission Figure 16.13 Sample Serial Transmission Flowchart In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCFTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 16 - (transmit trigger set number). Rev. 1.00 Dec. 27, 2005 Page 575 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. If and external clock is specified, the SCIF outputs data in synchronization with the input clock. Serial transmit data is output in order from LSB to MSB from the TxD pin. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the state of the TxD pin is held. 4. After serial transmission has completed, the SCIFnCK pin is fixed to high. Figure 16.14 shows an example of the SCIF transmit operation. Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDFE TEND TXI request TXI handling routine writes data in SCFTDR and clears the TDFE flag to 0 TXI request 1 frame Figure 16.14 Example of the SCIF Transmit Operation Rev. 1.00 Dec. 27, 2005 Page 576 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figures 16.15 and 16.16 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. To change the operating mode from asynchronous mode to clock synchronous mode without initialization, be sure to confirm that the flags ORER, PER3 to PER0, and FER3 to FER0 are cleared to 0. Initialization Start reception 1. SCIF initialization: See figure 16.3, Sample SCIF Initialization Flowchart. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCLSR, then after executing the necessary error handling, clear the ORER flag to 0. Serial reception cannot be continued while the ORER flag is set to 1. Yes 3. SCIF status check and receive data read: Read SCFSR, check that the RDF flag is set to 1, then read receive data in SCFRDR and clear the RDF flag to 0. Notification that the RDF flag has changed from 0 to 1 can also be given by the RXI. 4. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The number of receive data in SCFRDR can be ascertained by reading the lower bits of SCFDR. However, if the DMAC is activated by the RXI and the value is read from SCFRDR, the RDF flag is cleared automatically. Read ORER flag in SCLSR ORER = 1? No Error handling Read RDF flag in SCFSR No RDF = 1? Yes Read receive data from SCFRDR and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End reception Figure 16.15 Sample Serial Reception Flowchart Rev. 1.00 Dec. 27, 2005 Page 577 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 16.16 Sample Serial Reception Flowchart In serial reception, the SCIF operates as described below. 1. The SCIF internally initializes in synchronization with the synchronous clock input or output. 2. The SCIF stores receive data in SCRSR in order from LSB to MSB. After reception, the SCIF checks whether receive data can be transmitted from SCRSR to SCFRDR. If this check is passed, the SCIF stores the receive data in SCFRDR. If an overrun error is detected by an error check, following reception can not be performed. 3. If the RDF flag is set to 1 and the RIE bit in SCSCR is set to 1, the SCIF requests a receiveFIFO-data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit or REIE bit in SCSCR is set to 1, the SCIF requests a break interrupt (BRI). Rev. 1.00 Dec. 27, 2005 Page 578 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.17 shows an example of the SCIF receive operation. Serial clock LSB Serial data MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Bit 7 Bit 0 RDF ORER RXI request RXI handling RXI routine reads data request of SCFRDR and clears RDF flag to 0 BRI request generated by overrun error 1 frame Figure 16.17 Example of the SCIF Receive Operation Rev. 1.00 Dec. 27, 2005 Page 579 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Simultaneous Serial Data Transmission and Reception: Figure 16.18 shows a sample flowchart for simultaneous serial transmission and reception. Before performing simultaneous serial data transmission and reception according to the processes described below, specify the SCIF as the transmit/receive enable state. Rev. 1.00 Dec. 27, 2005 Page 580 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Initialization Start transmission and reception 1. SCIF initialization: See figure 16.3, Sample SCIF Initialization Flowchart. 2. SCIF status check and receive data write: Read SCFSR, check that the TDFE flag is set to 1, then write transmit data in SCFTDR and clear the TDFE flag to 0. Notification that the TDFE flag has changed from 0 to 1 can also be given by the TXI. 3. Receive error handling: If a receive error occurs, read the ORER flag in SCLSR, then after executing the necessary error handling, clear the ORER flag to 0. Serial reception cannot be continued while the ORER flag is set to 1. 4. SCIF status check and receive data read: Read SCFSR, check that the RDF flag is set to 1, then read receive data from SCFRDR and clear the RDF flag to 0. Notification that the RDF flag has changed from 0 to 1 can also be given by the RXI. Yes 5. Serial transmission/reception continuation procedure: To continue serial reception, before the MSB of the current frame is received, read the RDF flag and SCFRDR and clear the RDF flag to 0. Also, check that the TDFE flag is set to 1 and data can be written before transmitting the MSB of the current frame. Futhermore, write data in SCFTDR and clear the TDFE flag to 0. Note: When switching from transmission or reception to simultaneous transmission and reception, clear the TE and RE bits to 0, then set the both bits to 1 simultaneously. Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data in SCFTDR and read TDFE flag in SCFSR Read ORER flag in SCLSR ORER = 1? No Error handling Read RDF flag in SCFSR No RDF = 1? Yes Read receive data in SCFRDR and clear RDF flag in SCFSR to 0 No All data received? Yes Clear TE and RE bits in SCSCR to 0 End Figure 16.18 Sample Serial Data Transmission/Reception Flowchart Rev. 1.00 Dec. 27, 2005 Page 581 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) 16.5 SCIF Interrupt Sources and DMAC The SCIF supports four interrupt sources--transmit-FIFO-data-empty interrupt (TXI), receiveerror interrupt (ERI), receive-FIFO-data-full interrupt (RXI), and break interrupt (BRI). Table 16.6 shows the interrupt sources and their order of priority. For priorities and the relationship with nonthe SCIF interrupts, see section 4, Exception Handling. The interrupt sources can be enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TXI is enabled by the TIE bit, if the TDFE flag in SCFSR is set to 1, a TXI request and a transmit-FIFO-data-empty DMA transfer request are generated. When the TXI is disabled by the TIE bit, if the TDFE flag is set to 1, only the transmit-FIFO-data-empty DMA transfer request is generated. The DMAC can be activated and data transfer performed on generation of the transmitFIFO-data-empty DMA transfer request. When the RXI is enabled by the RIE bit, if the RDF flag or DR flag in SCFSR is set to 1, an RXI request and a receive-FIFO-data-full DMA transfer request are generated. When the RXI is disabled by the RIE bit, if the RDF flag or DR flag is set to 1, only the receive-FIFO-data-full DMA transfer request is generated. The DMAC can be activated and data transfer performed on generation of the receive-FIFO-data-full DMA transfer request. The generation of the RXI and the receive-FIFO-data-full DMA transfer requests by setting the DR flag to 1 occurs only in asynchronous mode. When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI request is generated. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 13, Direct Memory Access Controller (DMAC), for details on the DMAC setting procedure. Also set the RXI and TXI requests not to be output to the interrupt controller. If the interrupt requests are set to be generated, the interrupt requests to the interrupt controller are cleared by the DMAC regardless of the interrupt handling program. When the RIE bit is cleared to 0 and the REIE bit is set to 1 in SCSCR, the ERI or BRI request can be generated without generating the RXI request. Note that the TXI indicates that writing the transmit data is enabled, while the RXI indicates that the receive data is in SCFRDR. Rev. 1.00 Dec. 27, 2005 Page 582 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.6 The SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Note: * Description DMAC Activation Priority on Reset Release High Interrupt initiated by receive error (ER) Not possible Interrupt initiated by receive FIFO data Possible full (RDF) or data ready (DR)* Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by transmit FIFO data empty (TDFE) Not possible Possible Low The RXI by the DR is enabled only in asynchronous mode. See section 4, Exception Handling, for priorities and the relationship with non-the SCIF interrupts. 16.6 Usage Notes Note the following when using the SCIF. SCFTDR Writing and TDFE Flag: The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in SCFCR. After the TDFE flag is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from bits 12 to 8 in SCFDR. SCFRDR Reading and RDF Flag: The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. After the RDF flag is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is still equal to or greater than the trigger number after a read, the RDF flag will be set to 1 again if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after all receive data has been read. The number of receive data bytes in SCFRDR can be found from bits 4 to 0 in SCFDR. Rev. 1.00 Dec. 27, 2005 Page 583 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.19. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = 0.5 - 1 2N - (L - 0.5)F - D - 0.5 N (1 + F) x 100% ..................... (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency Rev. 1.00 Dec. 27, 2005 Page 584 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% ........................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Notes on DMAC Usage: To use an external clock source for a synchronous clock, the external clock should be input after SCFTDR has been updated by the DMAC and then five cycles or more of a peripheral operating clock has passed. If a transmit clock is input within four cycles after SCFTDR has updated, erroneous operation may occur (figure 16.20). SCIFnCK t TDFE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: To operate on an external clock, specify t as 4 cycles or more of a peripheral operating clock. Figure 16.20 Sample Transfer of Synchronous Clock by DMAC Rev. 1.00 Dec. 27, 2005 Page 585 of 932 REJ09B0269-0100 Section 16 Serial Communication Interface with FIFO (SCIF) Rev. 1.00 Dec. 27, 2005 Page 586 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Section 17 Serial I/O with FIFO (SIOF) This LSI includes a two-channel clocked synchronous serial I/O module with FIFO (SIOF) which can be directly connected to the audio CODEC. The functions of the SIOF0 and SIOF1 are common. 17.1 Features The features of the SIOF are described below. * Serial transfer Sixteen-stage 32-bit FIFOs (transmission/reception independently) Supports 8-bit data/16-bit data/16-bit stereo audio input/output MSB or LSB first for data transmission/reception Supports a maximum of 48-kHz sampling rate Synchronization by either frame synchronization pulse or left/right channel switch Supports CODEC control data interface Connectable to every A-Law or -Law CODEC linear audio chip manufactured by any company Supports both master and slave modes * Serial clock An external pin input or internal clock (P_CLK) can be selected as the clock source. * Interrupts Following four interrupts can be requested independently. Transmission interrupt Reception interrupt Error interrupt Control interrupt * DMA transfer Supports DMA transfer by a transfer request for transmission/reception SCIS3F0C_000020020900 Rev. 1.00 Dec. 27, 2005 Page 587 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the SIOF. 32 PP-BUS CCI RXI P_CLK ERI TXI Bus I/F 32 16 32 32 32 32 Control register Transmit FIFO (32 bits x 16 stages) Receive FIFO (32 bits x 16 stages) Transmit control data Receive control data Baud rate generator 1/nMCLK Timing control P/S S/P SIOMCLK SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Figure 17.1 Block Diagram of SIOF Rev. 1.00 Dec. 27, 2005 Page 588 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.2 Input/Output Pins The pin configuration of the SIOF0/1 is shown in table 17.1. Table 17.1 Pin Configuration Channel 0 Name Clock input pin Communication clock pin Frame synchronous pin Abbreviation SIOMCLK0 SCK_SIO0 SIOFSYNC0 I/O Input Input/ output Input/ output Output Input Input Input/ output Input/ output Output Input Function Master clock input Serial clock (common to transmission/reception) Frame synchronous signal (common to transmission/reception) Transmit data Receive data Master clock input Serial clock (common to transmission/reception) Frame synchronous signal (common to transmission/reception) Transmit data Receive data Transmit data pin TXD_SIO0 Receive data pin RXD_ SIO0 1 Clock input pin Communication clock pin Frame synchronous pin SIOMCLK1 SCK_SIO1 SIOFSYNC1 Transmit data pin TXD_SIO1 Receive data pin RXD_SIO1 Rev. 1.00 Dec. 27, 2005 Page 589 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3 Register Descriptions The SIOF has the following registers. For the addresses and access size of these registers, refer to section 23, List of Registers. 1. * * * * * * * * * * * * * 2. * * * * * * * * * * * * * Channel 0 SIOF mode register_0 (SIMDR_0) Serial clock select register_0 (SISCR_0) Serial transmit data assign register_0 (SITDAR_0) Serial receive data assign register_0 (SIRDAR_0) Serial control data assign register_0 (SICDAR_0) SIOF control register_0 (SICTR_0) SIOF FIFO control register_0 (SIFCTR_0) SIOF status register_0 (SISTR_0) SIOF interrupt enable register_0 (SIIER_0) Serial transmit data register_0 (SITDR_0) Serial receive data register_0 (SIRDR_0) Serial transmit control data register_0 (SITCR_0) Serial receive control data register_0 (SIRCR_0) Channel 1 SIOF mode register_1 (SIMDR_1) Serial clock select register_1 (SISCR_1) Serial transmit data assign register_1 (SITDAR_1) Serial receive data assign register_1 (SIRDAR_1) Serial control data assign register_1 (SICDAR_1) SIOF control register_1 (SICTR_1) SIOF FIFO control register_1 (SIFCTR_1) SIOF status register_1 (SISTR_1) SIOF interrupt enable register_1 (SIIER_1) Serial transmit data register_1 (SITDR_1) Serial receive data register_1 (SIRDR_1) Serial transmit control data register_1 (SITCR_1) Serial receive control data register_1 (SIRCR_1) Rev. 1.00 Dec. 27, 2005 Page 590 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.1 SIOF Mode Register (SIMDR) SIMDR is a register that sets the SIOF0/1 operating mode. SIMDR is initialized by a power-on reset or manual reset. Bit 15 14 Initial Bit Name Value TRMD1 TRMD0 0 0 R/W R/W R/W Description Transfer Mode Selects transfer mode. 00: Slave mode 1 01: Slave mode 2 10: Master mode 1 11: Master mode 2 Note: For the operation in each mode, see section 17.4.3, Transfer Data Format. 13 0 R Reserved This bit is always read as 0. The write value should always be 0. 12 REDG 0 R/W Receive Data Sampling Edge The TXD_SIO signal is transmitted at the opposite edge where the RXD_SIO signal is sampled (see figure 17.4). 0: RXD_SIO is sampled at the falling edge of SCK_SIO 1: RXD_SIO is sampled at the rising edge of SCK_SIO Note: This bit is valid in master mode 1 and master mode 2. Rev. 1.00 Dec. 27, 2005 Page 591 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 11 10 9 8 Initial Bit Name Value FL3 FL2 FL1 FL0 0 0 0 0 R/W R/W R/W R/W R/W Description Frame Length 00xx: Slot length is 8 bits and frame length is 8 bits 0100: Slot length is 8 bits and frame length is 16 bits 0101: Slot length is 8 bits and frame length is 32 bits 0110: Slot length is 8 bits and frame length is 64 bits 0111: Slot length is 8 bits and frame length is 128 bits 10xx: Slot length is 16 bits and frame length is 16 bits 1100: Slot length is 16 bits and frame length is 32 bits 1101: Slot length is 16 bits and frame length is 64 bits 1110: Slot length is 16 bits and frame length is 128 bits 1111: Slot length is 16 bits and frame length is 256 bits Notes: 1. When slot length is specified as 8 bits, control data cannot be transmitted or received. 2. When LSB is first transmitted or received, control data cannot be transmitted or received. x: Don't care 7 TXDIZ 0 R/W High-Impedance Output when Transmission is Invalid Specifies high-impedance output when transmission is invalid. 0: High output (1 output) when invalid 1: High-impedance output when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 LSBF 0 R/W LSB-First Transmission/Reception Selects the bit order of a transmit/receive frame. 0: MSB-first 1: LSB-first 5 RCIM 0 R/W Receive Control Data Interrupt Mode Selects the set timing of the RCRDY bit in SISTR. 0: Sets the RCRDY bit in SISTR when the contents of SIRCR change. 1: Sets the RCRDY bit in SISTR each time when SIRCR receives control data. Rev. 1.00 Dec. 27, 2005 Page 592 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 4 to 0 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 17.3.2 Serial Clock Select Register (SISCR) SISCR is used to set the baud rate generator operation. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified as B10 or B11. SISCR is initialized by a power-on reset or software reset. Bit 15 Bit Name MSSEL Initial Value R/W 1 R/W Description Master Clock Source Selection The master clock is the clock input to the baud rate generator. 0: Uses the SIOMCLK pin input signal as the master clock 1: Uses PCLK as the master clock 14 MSIMM 1 R/W Master Clock Direct Selection 0: Uses the baud rate generator output clock as the clock source 1: Uses the master clock itself as the clock source 13 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 12 11 10 9 8 7 to 3 BRPS4 BRPS3 BRPS2 BRPS1 BRPS0 -- 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R Baud Rate Generator's Prescalar Setting (BRPS) Set the master clock division ratio BRPS. 00000: (x 1/32) 00001: (x 1/1) 00010: (x 1/2) 11111: (x 1/31) Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 593 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 2 1 0 Bit Name BRDV2 BRDV1 BRDV0 Initial Value R/W 0 0 0 R/W R/W R/W Description Baud Rate Generator's Division Ratio Setting (BRDV) Set the frequency division ratio BRDV for the output stage of the baud rate generator. The final frequency division ratio of the baud rate generator is determined by BRPS x BRDV (maximum 1/1024). 000: Prescalar output x 1/2 001: Prescalar output x 1/4 010: Prescalar output x 1/8 011: Prescalar output x 1/16 100: Prescalar output x 1/32 Note: Other than above is reserved (setting prohibited). 17.3.3 Serial Transmit Data Assign Register (SITDAR) SITDAR is used to specify the position of the transmit data in a frame (slot number). SITDAR is initialized by a power-on reset and software reset. Bit 15 Initial Bit Name Value TDLE 0 R/W R/W Description Transmit Left Channel Data Enable 0: Disables left channel data transmission 1: Enables left channel data transmission 14 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 10 9 8 TDLA3 TDLA2 TDLA1 TDLA0 0 0 0 0 R/W R/W R/W R/W Transmit Left Channel Data Assigns Specify the position of left-channel data in transmit frame as B0000 to B1110. Transmit data for the left channel is specified in bits SITDL15 to SITDL0 in SITDR. Note: If the TDLA3 to TDLA0 bits are set to B1111, operation is not guaranteed. Transmit Right Channel Data Enable 0: Disables right channel data transmission 1: Enables right channel data transmission 7 TDRE 0 R/W Rev. 1.00 Dec. 27, 2005 Page 594 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 6 Initial Bit Name Value TLREP 0 R/W R/W Description Transmit Left Channel Repeat This bit setting is valid when the TDRE bit is set to 1. When this bit is set to 1, settings of bits SITDR15 to SITDR0 in SITDR are ignored. 0: Transmits data specified in the SITDR bit in SITDR as right channel data. 1: Repeatedly transmits data specified in the SITDL bit in SITDR as right channel data 5 4 3 2 1 0 -- -- TDRA3 TDRA2 TDRA1 TDRA0 0 0 0 0 0 0 R R R/W R/W R/W R/W Reserved These bits are always read as 0. The write value should always be 0. Transmit Right Channel Data Assigns Specify the position of right-channel data in transmit frame as B0000 to B1110. Transmit data for the right channel is specified in bits SITDR15 to SITDR0 in SITDR. Note: If the TDRA3 to TDRA0 bits are set to B1111, operation is not guaranteed. 17.3.4 Serial Receive Data Assign Register (SIRDAR) SIRDAR is used to specify the position of the receive data in a frame. SIRDAR is initialized by a power-on reset or software reset. Bit 15 Bit Name RDLE Initial Value 0 R/W R/W Description Receive Left Channel Data Enable 0: Disables left channel data reception 1: Enables left channel data reception 14 to 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 595 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 11 10 9 8 Initial Bit Name Value RDLA3 RDLA2 RDLA1 RDLA0 0 0 0 0 R/W R/W R/W R/W R/W Description Receive Left Channel Data Assigns 3 to 0 Specify the position of left-channel data in a receive frame as B0000 to B1110. Receive data for the left channel is stored in bits SIRDL15 to SIRDL0 in SIRDR. Note: If the RDLA3 to RDLA0 bits are set to B1111, operation is not guaranteed. Receive Right Channel Data Enable 0: Disables right channel data reception 1: Enables right channel data reception 7 RDRE 0 R/W 6 to 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 RDRA3 RDRA2 RDRA1 RDRA0 0 0 0 0 R/W R/W R/W R/W Receive Right Channel Data Assigns 3 to 0 Specify the position of right-channel data in a receive frame as B0000 to B1110. Receive data for the right channel is stored in bits SIRDR15 to SIRDR0 in SIRDR. Note: If the RDRA3 to RDRA0 bits are set to B1111, operation is not guaranteed. 17.3.5 Serial Control Data Assign Register (SICDAR) SICDAR is used to specify the position of the control data in a frame. SICDAR can be specified only when the FL3 to FL0 bits in SIMDR are specified as 1xxx. SICDAR is initialized by a power-on reset or software reset. Bit 15 Bit Name CD0E Initial Value 0 R/W R/W Description Control Channel 0 Data Enable 0: Disables transmission and reception of control channel 0 data 1: Enables transmission and reception of control channel 0 data 14 to 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 596 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 11 10 9 8 Initial Bit Name Value CD0A3 CD0A2 CD0A1 CD0A0 0 0 0 0 R/W R/W R/W R/W R/W Description Control Channel 0 Data Assigns 3 to 0 Specify the position of control channel 0 data in a receive or transmit frame as B0000 to B1110. Transmit data for the control channel 0 data is specified in bits SITC015 to SITC00 in SITCR. Receive data for the control channel 0 data is stored in bits SIRC015 to SIRC00 in SIRCR. Note: If the CD0A3 to CD0A0 bits are set to B1111, operation is not guaranteed. 7 CD1E 0 R/W Control Channel 1 Data Enable 0: Disables transmission and reception of control channel 1 data 1: Enables transmission and reception of control channel 1 data 6 to 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 CD1A3 CD1A2 CD1A1 CD1A0 0 0 0 0 R/W R/W R/W R/W Control Channel 1 Data Assigns 3 to 0 Specify the position of control channel 1 data in a receive or transmit frame as B0000 to B1110. Transmit data for the control channel 1 data is specified in bits SITC115 to SITC10 in SITCR. Receive data for the control channel 1 data is stored in bits SIRC115 to SIRC10 in SIRCR. Note: If the CD1A3 to CD1A0 bits are set to B1111, operation is not guaranteed. Rev. 1.00 Dec. 27, 2005 Page 597 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.6 SIOF Control Register (SICTR) SICTR is used to set the SIOF operating state. SICTR is initialized by a power-on reset or software reset. Bit 15 Bit Name SCKE Initial Value 0 R/W R/W Description Serial Clock Output Enable This bit is valid in master mode. If this bit is set to 1, the SIOF initializes the baud rate generator and initiates the operation. At the same time, the SIOF outputs the clock generated in the baud rate generator to the SCK_SIO pin. 0: Disables the SCK_SIO output (outputs 0) 1: Enables the SCK_SIO output 14 FSE 0 R/W Frame Synchronous Signal Output Enable This bit is valid in master mode. If this bit is set to 1, the SIOF initializes the frame counter and initiates the operation. 0: Disables the SIOFSYNC output (outputs 0) 1: Enables the SIOFSYNC output 13 to 10 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 TXE 0 R/W Transmission Enable This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal) and when valid data is stored in the transmit FIFO. When the 1 setting for this bit becomes valid, the SIOF issues a transmission transfer request according to the setting of the TFWM bit in SIFCTR. When transmit data is stored in the transmit FIFO, transmission of data from the TXD_SIO pin begins. This bit is initialized by a transmit reset. 0: Disables data transmission from TXD_SIO (outputs 1) 1: Enables data transmission from TXD_SIO Rev. 1.00 Dec. 27, 2005 Page 598 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 8 Initial Bit Name Value RXE 0 R/W R/W Description Reception Enable This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, the SIOF begins the reception of data from the RXD_SIO pin. When receive data is stored in receive FIFO, the SIOF issues a reception transfer request according to the setting of the RFWM bit in SIFCTR. This bit is initialized by a receive reset. 0: Disables data reception from RXD_SIO 1: Enables data reception from RXD_SIO 7 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TXRST 0 R/W Transmission Reset This bit setting becomes valid immediately. When the 1 setting for this bit becomes valid, the SIOF immediately sets transmit data from the TXD_SIO pin to 1, and initializes the transmission data register and transmissionrelated status register. The following are initialized. * * * * SITDR Transmit FIFO write/read pointer TCRDY, TFEMP, and TDREQ bits in SISTR TXE bit As the SIOF is cleared automatically at the completion of reset operation, this bit is always read as 0. 0: Transmission operation is not reset 1: Resets transmission operation Rev. 1.00 Dec. 27, 2005 Page 599 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 0 Initial Bit Name Value RXRST 0 R/W R/W Description Reception Reset This bit setting becomes valid immediately. When the 1 setting for this bit becomes valid, the SIOF immediately disables reception from the RXD_SIO pin, and initializes the reception data register and reception-related status register. The following are initialized. * * * * SIRDR Receive FIFO write/read pointer RCRDY, RFFUL, and RDREQ bits in SISTR RXE bit As the SIOF is cleared automatically at the completion of reset operation, this bit is always read as 0. 0: Reception operation is not reset 1: Resets reception operation Rev. 1.00 Dec. 27, 2005 Page 600 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.7 SIOF FIFO Control Register (SIFCTR) SIFCTR is used to indicate the area available for the transmit/receive FIFO transfer. SIFCTR is initialized by a power-on reset or software reset. Bit 15 14 13 Initial Bit Name Value TFWM2 TFWM1 TFWM0 0 0 0 R/W R/W R/W R/W Description Transmit FIFO Watermark A transfer request to the transmit FIFO is issued by the TDREQ bit in SISTR. The transmit FIFO is always used as 16 stages of FIFO regardless of these bit settings. 000: Issue a transfer request when 16 stages of transmit FIFO are empty. 001: Reserved (setting prohibited) 010: Reserved (setting prohibited) 011: Reserved (setting prohibited) 100: Issue a transfer request when 12 or more stages of transmit FIFO are empty. 101: Issue a transfer request when 8 or more stages of transmit FIFO are empty. 110: Issue a transfer request when 4 or more stages of transmit FIFO are empty. 111: Issue a transfer request when 1 or more stages of transmit FIFO are empty. 12 11 10 9 8 TFUA4 TFUA3 TFUA2 TFUA1 TFUA0 1 0 0 0 0 R R R R R Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B00000 to B10000. Rev. 1.00 Dec. 27, 2005 Page 601 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 7 6 5 Initial Bit Name Value RFWM2 RFWM1 RFWM0 0 0 0 R/W R/W R/W R/W Description Receive FIFO Watermark A transfer request to the receive FIFO is issued by the RDREQ bit in SISTR. The receive FIFO is always used as 16 stages of FIFO regardless of these bit settings. 000: Issue a transfer request when 1 stage or more of receive FIFO are valid. 001: Reserved (setting prohibited) 010: Reserved (setting prohibited) 011: Reserved (setting prohibited) 100: Issue a transfer request when 4 or more stages of receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of receive FIFO are valid. 110: Issue a transfer request when 12 or more stages of receive FIFO are valid. 111: Issue a transfer request when 16 stages of receive FIFO are valid. 4 3 2 1 0 RFUA4 RFUA3 RFUA2 RFUA1 RFUA0 0 0 0 0 0 R R R R R Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B00000 to B10000. Rev. 1.00 Dec. 27, 2005 Page 602 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.8 SIOF Status Register (SISTR) SISTR shows the SIOF state. Each of the bits of this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1. SISTR is initialized by a power-on reset or software reset. Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 TCRDY 0 R Transmit Control Data Ready This bit indicates a state of the SIOF. If SITCR is written, the SIOF clears this bit. This bit is valid when the TXE bit in SICTR is set to 1. If the issue of interrupts by this bit is enabled, the SIOF issues a control interrupt. If SITCR is written when this bit is cleared to 0, SITCR is over-written and the previous contents of SITCR are not output from the TXD_SIO pin. 0: Indicates that a write to SITCR is disabled 1: Indicates that a write to SITCR is enabled Note: When using this bit, see 2 in section 17.5, Usage Notes. 13 TFEMP 0 R Transmit FIFO Empty This bit indicates a state; if SITDR is written, the SIOF clears this bit. This bit is valid when the TXE bit in SICTR is 1. If the issue of interrupts by this bit is enabled, the SIOF issues a control interrupt. 0: Indicates that transmit FIFO is not empty 1: Indicates that transmit FIFO is empty 12 TDREQ 0 R Transmit Data Transfer Request A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state of the SIOF. If the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, the SIOF issues a transmit interrupt. 0: No transfer request 1: Transfer request Rev. 1.00 Dec. 27, 2005 Page 603 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 11 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10 RCRDY 0 R Receive Control Data Ready This bit indicates a state of the SIOF. If SIRCR is read, the SIOF clears this bit. This bit is valid when the RXE bit in SICTR is set to 1. If the issue of interrupts by this bit is enabled, the SIOF issues a control interrupt. If SIRCR is written when this bit is set to 1, SIRCR is modified by the latest data. 0: Indicates that SIRCR stores no valid data 1: Indicates that SIRCR stores valid data 9 RFFUL 0 R Receive FIFO Full This bit indicates a state. If SIRDR is read, the SIOF clears this bit. This bit is valid when the RXE bit in SICTR is 1. If the issue of interrupts by this bit is enabled, the SIOF issues a control interrupt. 0: Receive FIFO not full 1: Receive FIFO full 8 RDREQ 0 R Receive Data Transfer Request A receive data transfer request is issued when the valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state the SIOF. If the size of valid space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, the SIOF issues a receive interrupt. 0: Indicates that the size of valid space in the receive FIFO does not exceed the size specified by the RFWM bit in SIFCTR. 1: Indicates that the size of valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. 7 to 5 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 604 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 4 Initial Bit Name Value FSERR 0 R/W R/W Description Frame Synchronization Error A frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. If a frame synchronization error occurs, the SIOF performs transmission or reception for slots that can be transferred. This bit is valid when the TXE or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, the SIOF issues an error interrupt. 0: Indicates that no frame synchronization error occurs 1: Indicates that a frame synchronization error occurs 3 TFOVR 0 R/W Transmit FIFO Overrun Transmit FIFO overrun means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit overrun occurs, written data is ignored. This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, the SIOF issues an error interrupt. 0: No transmit FIFO overrun 1: Transmit FIFO overrun 2 TFUDR 0 R/W Transmit FIFO Underrun Transmit FIFO underrun means that loading for transmission has occurred when the transmit FIFO is empty. When a transmit underrun occurs, the SIOF repeatedly sends the previous transmit data. This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, the SIOF issues an error interrupt. 0: No transmit FIFO underrun 1: Transmit FIFO underrun Rev. 1.00 Dec. 27, 2005 Page 605 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 1 Bit Name RFUDR Initial Value 0 R/W R/W Description Receive FIFO Underrun Receive FIFO underrun means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive underrun occurs, the value of data read from SIRDR is not guaranteed. This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, the SIOF issues an error interrupt. 0: No receive FIFO underrun 1: Receive FIFO underrun 0 RFOVR 0 R/W Receive FIFO Overrun Receive FIFO overrun means that writing has occurred when the receive FIFO is full. When a receive overrun occurs, the SIOF indicates the overrun, and receive data is lost. This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, the SIOF issues an error interrupt. 0: No receive FIFO overrun 1: Receive FIFO overrun Rev. 1.00 Dec. 27, 2005 Page 606 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.9 SIOF Interrupt Enable Register (SIIER) SIIER is a used to enable the issue of SIOF interrupts. When each of the bits of this register is set to 1, and the corresponding bit of the SISTR is set to 1, the SIOF issues an interrupt. SIIER is initialized by a power-on reset or software reset. Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 TCRDYE 0 R/W Transmit Control Data Ready Enable 0: Disables interrupts due to transmit control data ready 1: Enables interrupts due to transmit control data ready (control interrupt) 13 TFEMPE 0 R/W Transmit FIFO Empty Enable 0: Disables interrupts due to transmit FIFO empty 1: Enables interrupts due to transmit FIFO empty (control interrupt) 12 TDREQE 0 R/W Transmit Data Transfer Request Enable 0: Disables interrupts due to transmit data transfer requests 1: Enables interrupts due to transmit data transfer requests (transmit interrupt) 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 RCRDYE 0 R/W Receive Control Data Ready Enable 0: Disables interrupts due to receive control data ready 1: Enables interrupts due to receive control data ready (control interrupt) 9 RFFULE 0 R/W Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full (control interrupt) Rev. 1.00 Dec. 27, 2005 Page 607 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Bit 8 Bit Name RDREQE Initial Value 0 R/W R/W Description Receive Data Transfer Request Enable 0: Disables interrupts due to receive data transfer requests 1: Enables interrupts due to receive data transfer requests (receive interrupt) 7 to 5 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 FSERRE 0 R/W Frame Synchronization Error Enable 0: Disables interrupts due to frame synchronization error 1: Enables interrupts due to frame synchronization error (error interrupt) 3 TFOVRE 0 R/W Transmit FIFO Overrun Enable 0: Disables interrupts due to transmit FIFO overrun 1: Enables interrupts due to transmit FIFO overrun (error interrupt) 2 TFUDRE 0 R/W Transmit FIFO Underrun Enable 0: Disables interrupts due to transmit FIFO underrun 1: Enables interrupts due to transmit FIFO underrun (error interrupt) 1 RFUDRE 0 R/W Receive FIFO Underrun Enable 0: Disables interrupts due to receive FIFO underrun 1: Enables interrupts due to receive FIFO underrun (error interrupt) 0 RFOVRE 0 R/W Receive FIFO Overrun Enable 0: Disables interrupts due to receive FIFO overrun 1: Enables interrupts due to receive FIFO overrun (error interrupt) Rev. 1.00 Dec. 27, 2005 Page 608 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.10 Serial Transmit Data Register (SITDR) SITDR is used to specify the SIOF transmit data. The setting data for this register is stored in the transmit FIFO. SITDR is initialized by a power-on reset, software reset, or transmit reset. Bit 31 to 16 Bit Name Initial Value R/W W Description Left Channel Transmit Data Specify data to be output from the TXD_SIO pin as left channel data. The position of the left channel data in the transmission frame is specified by the TDLA bit in SITDAR. These bits are valid only when the TDLE bit in SITDAR is set to 1. 15 to 0 SITDR15 to All 0 SITDR0 SITDL15 to All 0 SITDL0 W Right Channel Transmit Data Specify data to be output from the TXD_SIO pin as right channel data. The position of the right channel data in the transmission frame is specified by the TDRA bit in SITDAR. These bits are valid only when the TDLE bit and TLREP bit in SITDAR are set to 1 and cleared to 0, respectively. Rev. 1.00 Dec. 27, 2005 Page 609 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.11 Serial Receive Data Register (SIRDR) SIRDR is used to read receive data of the SIOF. SIRDR stores data in the receive FIFO. SIRDR is initialized by a power-on reset, software reset, or receive reset. Bit 31 to 16 Bit Name SIRDL15 to SIRDL0 Initial Value All 0 R/W R Description Left Channel Receive Data Store data received from the RXD_SIO pin as left channel data. The position of the left channel data in a receive frame is specified by the RDLA bit in SIRDAR. These bits are valid only when the RDLE bit in SIRDAR is set to 1. 15 to 0 SIRDR15 to All 0 SIRDR0 R Right Channel Receive Data Store data received from the RXD_SIO pin as right channel data. The position of the right channel data in the reception frame is specified by the RDRA bit in SIRDAR. These bits are valid only when the RDRE bit in SIRDAR is set to 1. Rev. 1.00 Dec. 27, 2005 Page 610 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.12 Serial Transmit Control Data Register (SITCR) SITCR is used to specify the SIOF transmit control data. SITCR can be specified only when the FL3 to EL0 bits in SIMDR are specified as 1xxx. SITCR is initialized by a power-on reset, software reset, or transmit reset. Bit 31 to 16 Bit Name Initial Value R/W W Description Control Channel 0 Transmit Data Specify data to be output from the TXD_SIO pin as control channel 0 transmit data. The position of the control channel 0 data in the transmission or reception frame is specified by the CD0A bit in SICDAR. These bits are valid only when the CD0E bit in SICDAR is set to 1. 15 to 0 SITC115 to All 0 SITC10 SITC015 to All 0 SITC00 W Control Channel 1 Transmit Data Specify data to be output from the TXD_SIO pin as control channel 1 transmit data. The position of the control channel 1 data in the transmission or reception frame is specified by the CD1A bit in SICDAR. These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 1.00 Dec. 27, 2005 Page 611 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.3.13 Serial Receive Control Data Register (SIRCR) SIRCR is used to store the SIOF receive control data. SIRCR can be specified only when the FL3 to FL0 bits in SIMDR are specified as 1xxx. SIRCR is initialized by a power-on reset, software reset, or receive reset. Bit 31 to 16 Bit Name Initial Value R/W R Description Control Channel 0 Receive Data Store data received from the RXD_SIO pin as control channel 0 receive data. The position of the control channel 0 data in the transmission or reception frame is specified by the CD0A bit in SICDAR. These bits are valid only when the CD0E bit in SICDAR is set to 1. 15 to 0 SIRC115 to All 0 SIRC10 SIRC015 to All 0 SIRC00 R Control Channel 1 Receive Data Store data received from the RXD_SIO pin as control channel 1 receive data. The position of the control channel 1 data in the transmission or reception frame is specified by the CD1A bit in SICDAR. These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 1.00 Dec. 27, 2005 Page 612 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.4 17.4.1 Operation Serial Clocks Master/Slave Modes: The following modes are available as the SIOF clock mode. * Slave mode: SCK_SIO*, SIOFSYNC input * Master mode: SCK_SIO*, SIOFSYNC output Note: * In master mode, the SCK_SIO signal is kept output even if there is data or not. Baud Rate Generator (BRG): In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The division ratio is from 1/2 to 1/1024. Figure 17.2 shows connections for supply of the serial clock. 1/2 to 1/1024MCLK BRG E SIOMCLK P_CLK Timing control Master OE SCK_SIO Figure 17.2 Serial Clock Supply Rev. 1.00 Dec. 27, 2005 Page 613 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.2 shows an example of serial clock frequency. Table 17.2 SIOF Serial Clock Frequency Sampling Rate Frame Length 32 bits 64 bits 128 bits 256 bits 8 kHz 256 kHz 512 kHz 1.024 MHz 2.048 MHz 44.1 kHz 1.4112 MHz 2.8224 MHz 5.6648 MHz 11.2896 MHz 48 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.288 MHz 96 kHz 3.072 MHz 17.4.2 Serial Timing SIOFSYNC: The SIOFSYNC is a frame synchronous signal. Depending on the transfer mode, it has the following two functions. * Synchronous pulse: 1-bit-width pulse indicating the start of the frame * L/R: 1/2-frame-width pulse indicating the left channel stereo data (L) in high level and the right channel stereo data (R) in low level Figure 17.3 shows the SIOFSYNC synchronization timing. The timing of master mode 1, slave mode 1, and slave mode 2 is shown in (a) in figure 17.3. The timing of master mode 2 is shown in (b) in figure 17.3. Rev. 1.00 Dec. 27, 2005 Page 614 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) (a) Synchronous pulse 1 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO First bit data (MSB) 1-bit delay (b) L/R 1 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO First bit of left channel data (MSB) First bit of right channel data (MSB) 1/2 frame length No delay 1/2 frame length Figure 17.3 Serial Data Synchronization Timing Transmit/Receive Timing: The TXD_SIO transmission timing and RXD_SIO reception timing relative to the SCK_SIO signal can be set as the sampling timing in the following two ways. The transmit/receive timing is set using the REDG bit in SIMDR. In slave mode 1 and slave mode 2, only falling-edge sampling is available. * Falling-edge sampling * Rising-edge sampling Figure 17.4 shows the transmit/receive timing. Rev. 1.00 Dec. 27, 2005 Page 615 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) (a) Falling-edge sampling (a) Rising-edge sampling SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Reception timing Transmission timing Reception timing Transmission timing SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Figure 17.4 SIOF Transmit/Receive Timing 17.4.3 Transfer Data Format The SIOF performs the following transfer. * Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data * Control data: Transfer of 16-bit data (uses the specific register as interface) Transfer Mode: The SIOF supports the following four transfer modes as listed in table 17.3. The transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR. Table 17.3 Serial Transfer Modes Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 SIOFSYNC Synchronous pulse Synchronous pulse Synchronous pulse L/R Bit Delay One bit One bit One bit No Control Data Slot position Secondary FS Slot position Not supported Frame Length: The length of the frame to be transferred by the SIOF is specified by the FL3 to FL0 bits in SIMDR. Table 17.4 shows the relationship between the settings of the FL3 to FL0 bits and frame length. Rev. 1.00 Dec. 27, 2005 Page 616 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.4 Frame Length FL3 to FL0 00xx 0100 0101 0110 0111 10xx 1100 1101 1110 1111 Slot Length 8 8 8 8 8 16 16 16 16 16 Number of Bits in a Frame 8 16 32 64 128 16 32 64 128 256 Transfer Data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 16-bit monaural data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data [Legend] x: Don't care. Slot Position: The SIOF can specify the position of transmit data, receive data, and control data (common to transmission and reception) by slot numbers. The slot number of each data is specified by the following registers. * Transmit data: SITDAR * Receive data: SIRDAR * Control data: SICDAR Only 16-bit slot leugth is valid for control register. In addition, control data is always assigned to the same slot number both in transmission and reception. 17.4.4 Register Allocation of Transfer Data Transmit/Receive Data: Writing and reading of transmit or receive data are performed for the following registers. * Transmit data writing: SITDR (32-bit access) * Receive data reading: SIRDR (32-bit access) Rev. 1.00 Dec. 27, 2005 Page 617 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Figure 17.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment. (a) 16-bit stereo data 31 24 23 Lch.data 16 15 87 Rch.data 0 (b) 16-bit monaural data 31 24 23 Data 16 15 87 0 (c) 8-bit monaural data 31 24 23 Data 16 15 87 0 (d) 16-bit stereo data (left and right same audio output) data 31 24 23 16 15 87 Data 0 Figure 17.5 Transmit/Receive Data Bit Alignment Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in unshaded areas is not transmitted or received. Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR. Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR. To achieve left and right same audio output while stereo is specified for the transmit data, specify the TLREP bit in SITDAR. Tables 17.5 and 17.6 show the audio mode specification for transmit data and that for receive data, respectively. To execute 8-bit monaural transmission or reception, use the left channel. Rev. 1.00 Dec. 27, 2005 Page 618 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.5 Audio Mode Specification for Transmit Data Bit Mode Monaural Stereo left and right same audio output Note: x: Don't care TDLE 1 1 1 TDRE 0 1 1 TLREP x 0 1 Table 17.6 Audio Mode Specification for Receive Data Bit Mode Monaural Stereo RDLE 1 1 RDRE 0 1 Note: Left and right same audio mode is not supported in receive data. Control Data: Control data is written to or read from by the following registers. * Transmit control data write: SITCR (32-bit access) * Receive control data read: SIRCR (32-bit access) Figure 17.6 shows the control data and bit alignment in SITCR and SIRCR. (a) Control data: one channel 31 24 23 Control data (channel 0) 16 15 87 0 (b) Control data: two channel 31 24 23 Control data (channel 0) 16 15 87 Control data (channel 1) 0 Figure 17.6 Control Data Bit Alignment The number of channels in control data is specified by CD0E and CD1E bits in SICDAR. Table 17.7 shows the relationship between the number of channels in control data and bit settings. To use only one channel in control data, use channel 0. Rev. 1.00 Dec. 27, 2005 Page 619 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.7 Setting for Number of Control Data Channels Bit Number of Channels 1 2 CD0E 1 1 CD1E 0 1 17.4.5 Control Data Interface Control data performs control command output to the CODEC and status input from the CODEC. The SIOF supports the following two control data interface methods. * Control by slot position * Control by secondary FS Control data is valid only when slot length is specified as 16 bits and MSB-first transmission/reception is selected. Control by Slot Position (Master Mode 1): Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data. This method can be used in both SIOF master and slave modes. Figure 17.7 shows an example of control data interface timing by slot position control. Note: When using this control method, use PCLK as the master clock (master clock selection (MSSEL) = 1). 1 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Lch.DATA Slot No.0 Control channel 0 Control channel 0 Rch.DATA Slot No.2 Slot No.1 Slot No.3 FL = 1110 (Frame length: 128 bits), TDRA3 to TDRA0 = 0010, TDRE = 1, RDRA3 to RDRA0 = 0010, RDRE = 1, CD1A3 to CD1A0 = 0011 CD1E = 1, Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0001, Figure 17.7 Control Data Interface (Slot Position) Rev. 1.00 Dec. 27, 2005 Page 620 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Control by Secondary FS (Slave Mode 2): The CODEC normally outputs SIOFSYNC as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data. This method is valid for SIOF slave mode. The following summarizes the control data interface procedure by secondary FS. * Transmit normal transmit data of LSB = 0 (The SIOF forcibly clears 0) * To execute control data transmission, send transmit data of LSB = 1 (The SIOF forcibly set to 1 by writing SITCR) * The CODEC outputs the secondary FS. * The SIOF transmits control data (data specified by SITCR) or receives control data (stores in SIRCR) synchronously with the secondary FT. Figure 17.8 shows an example of control data interface timing by secondary FS. 1 frame 1/2 frame 1/2 frame SCK_SIO SIOFSYNC Normal FS Secondary FS Normal FS TXD_SIO Lch.DATA RXD_SIO Slot No.0 Control channel 0 Slot LSB = 1 (Secondary FS request) No.0 Setting: TRMD = 01, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1110 (Frame length: 128 bits), TDRA3 to TDRA0 = 0000, TDRE = 0, RDRA3 to RDRA0 = 0000, RDRE =0, CD1A3 to CD1A0 = 0000 CD1E = 0, Figure 17.8 Control Data Interface (Secondary FS) 17.4.6 FIFO Overview: The transmit and receive FIFOs of the SIOF have the following features. * Sixteen-stage 32-bit FIFOs for transmission and reception * The FIFO pointer can be modified in one read or write cycle regardless of access size of the CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) * Regardless of access size, the number of access cycles is always two cycles of the P-bus cycle. Transfer Request: The SIOF indicates a transfer request of the FIFO in the following two bits of SISTR. Rev. 1.00 Dec. 27, 2005 Page 621 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) * FIFO transmit request: TDREQ (transmit interrupt source) * FIFO receive request: RDREQ (receive interrupt source) The request conditions for FIFO transmit or receive can be specified individually. The request conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 17.8 and 17.9 summarize the conditions specified by SIFCTR. Table 17.8 Conditions to Issue Transmit Request TFWM2 to TFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Transmit Request Empty area is 16 stages Empty area is 12 stages or more Empty area is 8 stages or more Empty area is 4 stages or more Empty area is 1 stage or more Largest Used Areas Smallest Table 17.9 Conditions to Issue Receive Request RFWM2 to RFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Receive Request Valid data is 1 stage or more Valid data is 4 stages or more Valid data is 8 stages or more Valid data is 12 stages or more Valid data is 16 stages Largest Used Areas Smallest The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the above stage number. Accordingly, an overrun error or underrun error occurs if data area or empty area exceeds sixteen FIFO stages. FIFO transmission or reception request is cancelled when the above condition is not satisfied even if the FIFO is not empty or full. Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by the following register. * Transmit FIFO: The number of empty FIFO stages are indicated by the TFUA4 to TFUA0 bits in SIFCTR. Rev. 1.00 Dec. 27, 2005 Page 622 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) * Receive FIFO: The number of valid data stages that can be transferred by the CPU or DMAC are indicated by the RFUA4 to RFUA0 bits in SIFCTR. The above contents show the number of data which CPU or DMAC can transfer. 17.4.7 Transmission and Reception Procedures Transmission in Master Mode: Figure 17.9 shows an example of settings and operation for master mode transmission. Rev. 1.00 Dec. 27, 2005 Page 623 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of FIFO request Set operation start for baud rate generator 2 Set SCKE bit in SICTR to 1 3 Start SCK_SIO clock transmission Output serial clock 4 Set FSE bit in SICTR to 1 Set the start for frame synchronous signal Set to enable transmission Transmit frame synchronous signal Submit transmission request 5 Set TXE bit in SICTR to 1 6 TDREQ=1? Yes No 7 Set SITDR Set transmit data 8 Output SITDR contents from TXD_SIO synchronously with SIOFSYNC Transmit Transfer ended? 9 Yes No Set to disable transmission End transmission Clear TXE bit in SICTR to 0 End Figure 17.9 Example of Transmission Operation in Master Mode Reception in Master Mode: Figure 17.10 shows an example of settings and operation for master mode reception. Rev. 1.00 Dec. 27, 2005 Page 624 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of FIFO request Set operation start for baud rate generator 2 Set SCKE bit in SICTR to 1 3 Start SCK_SIO clock transmission Transmit serial clock Set the start for frame synchronous signal Set to enable reception Transmit frame synchronous signal 4 Set FSE bit in SICTR to 1 5 Set RXE bit in SICTR to 1 6 Store receive data from RXD_SIO in SIRDR synchronously with SIOFSYNC Submit reception request according to the receive FIFO threshold value 7 RDREQ=1? Yes No Reception 8 Read SIRDR Read receive data 9 Receive ended? Yes No Set to disable reception End reception Clear RXE bit in SICTR to 0 End Figure 17.10 Example of Reception Operation in Master Mode Transmission in Slave Mode: Figure 17.11 shows an example of settings and operation for slave mode transmission. Rev. 1.00 Dec. 27, 2005 Page 625 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of FIFO request Submit transmission request to disable transmission when frame synchronous signal is transmitted 2 Set TXE bit in SICTR to 1 Set to enable transmission 3 TDREQ=1? Yes No 4 Set SITDR Set transmit data 5 Output SITDR contents from TXD_SIO synchronously with SIOFSYNC Transmit Transfer ended? Yes 6 No Set to disable transmission End transmission Clear TXE bit in SICTR to 0 End Figure 17.11 Example of Transmission Operation in Slave Mode Reception in Slave Mode: Figure 17.12 shows an example of settings and operation for slave mode reception. Rev. 1.00 Dec. 27, 2005 Page 626 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and the upper limit value of FIFO request Set to enable reception Enable reception when the frame synchronous signal is input Submit reception request according to the limit value of receive FIFO 2 Set RXE bit in SICTR register to 1 3 Store receive data from RXD_SIO in SIRDR synchronously with SIOFSYNC 4 RDREQ=1? Yes No Reception 5 Read SIRDR Read receive data Transfer ended? 6 Yes No Set to disable reception End reception Clear RXE bit in SICTR to 0 End Figure 17.12 Example of Reception Operation in Slave Mode Transmission/Reception Reset: The SIOF can separately reset the transmission and reception units by setting the following bits to 1. * Transmission reset: TXRST bit in SICTR * Reception reset: RXRST bit in SICTR Rev. 1.00 Dec. 27, 2005 Page 627 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.10 shows the details of initialization upon transmission or reception reset. Table 17.10 Transmission and Reception Reset Type Transmission reset Objects Initialized SITDR Transmit FIFO write pointer, transmit FIFO read pointer TCRDY bit, TFEMP bit, TDREQ bit in SISTR TXE bit in SICTR Reception reset SIRDR Receive FIFO write pointer, receive FIFO read pointer RCRDY bit, RFFUL bit, RDREQ bit in SISTR RXE bit in SICTR Module Stop: In the module stop state, the SIOF stops transmit/receive operation with contents of all registers retained. If transmit/receive operation is not performed immediately after the module stop state is cleared, issue a transmit/receive reset. 17.4.8 Interrupts The SIOF has four types of interrupts listed below. This classification is reflected to the IRR7 (SIOF0) and IRR8 (SIOF1) of the interrupt controller (INTC). * * * * Transmit interrupt (TXI) Receive interrupt (RXI) Control interrupt (CCI) Error interrupt (ERI) Interrupt Sources: Interrupts can each be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 17.11 lists the SIOF interrupt sources. Rev. 1.00 Dec. 27, 2005 Page 628 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.11 SIOF Interrupt Sources No. 1 Classification Transmission (TXI) Bit Name TDREQ Function name Description Transmit data transfer The number of transmit FIFO data request is equal to or less than the specified value by transmit operation. Receive data transfer The receive FIFO stores data of request specified value or more. Transmit control data The transmit control data register is ready ready to be written. Receive control data ready The receive control data register stores valid data. 2 3 4 5 6 7 Reception (RXI) RDREQ Control (CCI) TCRDY RCRDY TFEMP RFFUL Error (ERI) TFUDR Transmit FIFO empty The transmit FIFO is empty. Receive FIFO full Transmit FIFO underrun Transmit FIFO overrun Receive FIFO overrun Receive FIFO underrun The receive FIFO is full. Serial data transmission timing has arrived while the transmit FIFO is empty. Write to the transmit FIFO is performed while the transmit FIFO is full. Serial data is received while the receive FIFO is full. The receive FIFO is read while the receive FIFO is empty. 8 TFOVR 9 10 11 RFOVR RFUDR FSERR Frame A synchronous signal is input synchronization error before the specified bit time has been passed (in slave mode). Whether an interrupt is issued or not as the result of an interrupt source is determined by the SIIER settings. If an interrupt source is set to 1, and the corresponding bit in SIIER is set to 1, the SIOF issues each interrupt. Transmit/Receive Interrupt Flag: Transmit and receive interrupts are sent to the INTC or DMAC by this interrupt flag based on the values of bits TDREQ and RDREQ in SISTR. Table17.12 shows the setting condition of the transmit/receive interrupt flag. Rev. 1.00 Dec. 27, 2005 Page 629 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag Setting Condition Transmit interrupt flag Receive interrupt flag TDREQ bit in SISTR is set to 1 RDREQ bit in SISTR is set to 1 Reset Condition TDREQ bit in SISTR is cleared to 0 Acknowledge from DMAC RDREQ bit in SISTR is cleared to 0 Acknowledge from DMAC Processing when Errors Occur: On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the following operations. * Transmit FIFO underrun (TFUDR) The immediately preceding transmit data is again transmitted. * Transmit FIFO overrun (TFOVR) The contents of the transmit FIFO are protected, and the write operation causing the overrun is ignored. * Receive FIFO overrun (RFOVR) Data causing the overrun is discarded and lost. * Receive FIFO underrun (RFUDR) The latest read data is output on the bus (undefined value as specification). * Frame synchronization error (FSERR) The internal counter is reset according to the FSYN signal in which an error occurs. 17.4.9 Transmission and Reception Timing Examples of the SIOF serial transmission and reception are shown in figure 17.13 through figure 17.19. 8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, frame length = 8 bits Rev. 1.00 Dec. 27, 2005 Page 630 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 1 frame SCK_SIO SIOFSYNC TXD_SIO Lch.DATA RXD_SIO Slot No.0 1-bit delay Setting: TRMD = 00or10, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 0000 (frame legth: 8 bits) TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 17.13 Transmission and Reception Timings (8-Bit Monaural Data (1)) 8-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, frame length = 16 bits 1 frame SCK_SIO SIOFSYNC TXD_SIO Lch.DATA RXD_SIO Slot No.0 1-bit delay Setting: TRMD = 00or10, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 0100 (frame length: 16 bits) TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Slot No.1 Figure 17.14 Transmission and Reception Timings (8-Bit Monaural Data (2)) 16-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, frame length = 64 bits Rev. 1.00 Dec. 27, 2005 Page 631 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 1 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Lch.DATA Slot No.0 No bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1101 (frame length: 64 bits) TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Slot No.1 Slot No.2 Slot No.3 Figure 17.15 Transmission and Reception Timings (16-Bit Monaural Data (1)) 16-bit Stereo Data (1): L/R method, rising edge sampling, slot No.0 used for left channel data, slot No.1 used for right channel data, frame length = 32 bits 1 frame SCK_SIO SIOFSYNC TXD_SIO Lch.DATA RXD_SIO No bit delay Rch.DATA Slot No.1 Slot No.0 Setting: TRMD = 11, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 1, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1100 (frame length: 32 bits) TDRE = 1, TDRA3 to TDRA0 = 0001, RDRE = 1, RDRA3 to RDRA0 = 0001, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 17.16 Transmission and Reception Timings (16-Bit Stereo Data (1)) 16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left channel transmit data, slot No.1 used for left channel receive data, slot No.2 used for right channel transmit data, slot No.3 used for right channel receive data, frame length = 64 bits Rev. 1.00 Dec. 27, 2005 Page 632 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 1 frame SCK_SIO SIOFSYNC TXD_SIO Lch.DATA Rch.DATA RXD_SIO Slot No.0 No bit delay Setting: TRMD = 01, TDLE = 1, RDLE = 1, CD0E = 0, Lch.DATA Slot No.1 Slot No.2 Rch.DATA Slot No.3 REDG = 1, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0001, CD0A3 to CD0A0 = 0000, FL = 1101 (frame length: 64 bits), TDRE = 1, TDRA3 to TDRA0 = 0010, RDRE = 1, RDRA3 to RDRA0 = 0011, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 17.17 Transmission and Reception Timings (16-Bit Stereo Data (2)) 16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for left channel data, slot No.2 used for right channel data, slot No.1 used for control channel 0 data, slot No.3 used for control channel 1 data, frame length = 128 bits 1 frame SCK_SIO SIOFSYNC TXD_SIO Lch.DATA RXD_SIO Slot No.0 Control ch.0 Slot No.1 Rch.DATA Slot No.2 Control ch.1 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0001, FL = 1110 (frame length: 128 bits), TDRA3 to TDRA0 = 0010, TDRE = 1, RDRE = 1, RDRA3 to RDRA0 = 0010, CD1A3 to CD1A0 = 0011 CD1E = 1, Figure 17.18 Transmission and Reception Timings (16-Bit Stereo Data (3)) 16-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, request for secondary FS, slot No.0 used for left channel data, slot No.0 used for control channel 0 data, frame length = 128 bits Rev. 1.00 Dec. 27, 2005 Page 633 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) (a) When control channel is not transferred 1 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Lch.DATA Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 LSB = 0 (Secoundary FS request) 1bit delay (b) When control channel is transferred 1 frame 1/2 frame SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Normal FS Lch.DATA Slot No.0 1bit delay Setting: TRMD = 01 TDLE = 1, RDLE = 1, CD0E = 1, 1/2 frame Secondary FS Control channel 0 Slot No.1 Slot No.2 Slot No.3 Slot No.0 Slot No.1 Slot No.2 Slot No.3 Normal FS LSB = 1 (Secoundary FS request) REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1110 (frame length: 128 bits), TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 17.19 Transmission and Reception Timings (16-Bit Monaural Data (2)) Rev. 1.00 Dec. 27, 2005 Page 634 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) 17.5 Usage Notes Note the following when using the SIOF. 1. Using the transmit function in slave mode If transmission is enabled when data has already been written to the transmit FIFO, one or two of the first data bytes may be lost. Therefore, data should not be written to the transmit FIFO before enabling transmission. 2. Using control data transmission/reception consecutively on control data interface (secondary FS position) The TCRDY value may become 1 before transmit control data is sent, and if the next control data is written to the control data register at this point, the control data waiting to be sent will be overwritten and erased. At this time, also, the control sequence is disrupted and the SIOF switches around the primary FS and secondary FS, with the result that transmission/reception of data and control data can no longer be performed normally. The control data register should therefore be written to after transmit control data has been sent. Example: Check RCRDY, and write to the control data register when RCRDY is 1. After transmit control data has been written to, it is essential to read the receive control register (SIRCR) and clear RCRDY. 3. DMA transfer Do not use 16-byte DMA transfer. (See section 13.4.4, DMA Transfer Types.) 4. Access from the CPU When performing access from the CPU, do not access the SIOF's transmit/receive FIFO consecutively, but instead insert an access to somewhere else between SIOF transmit/receive FIFO accesses. 5. Transmit/receive FIFO underflow If the transmit/receive FIFO underflows during a transmit/receive operation, control of the SIOF's transmit/receive FIFO may fail and data may be lost. To prevent this, either set a watermark so that an underflow does not occur, or execute a transmit reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated. 6. Transmit/receive reset execution When using the SIOF again after a transmit/receive operation ends, or after erroneous operation occurs, first execute a transmit reset (TXRST) or receive reset (RXRST). Rev. 1.00 Dec. 27, 2005 Page 635 of 932 REJ09B0269-0100 Section 17 Serial I/O with FIFO (SIOF) Rev. 1.00 Dec. 27, 2005 Page 636 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Section 18 Ethernet Controller (EtherC) This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI) complying with this standard enables the Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. The LSI has two MAC layer interface ports (hereafter referred to as port 0 and port 1), both of which can be made to perform transmission and reception independently. This Ethernet controller also has an on-chip TSU (Transfer Switching Unit) which controls transferring, allowing mutual transfer of data between MAC layer controllers of ports 0 and 1. This TSU has a 32-entry CAM (Content Addressable Memory) and two external CAM interface input pins for determining whether to receive or transfer packets input to both Ethernet controllers. The TSU also has a total 6-kbyte transfer FIFO for retaining packets to be transferred, allowing allocation of transfer FIFO capacity to be set freely for the transfer conditions of port 0 to 1 and port 1 to 0. The Ethernet controller is connected to the Ethernet Direct Memory Access Controller (E-DMAC) for Ethernet controller inside the LSI, and carries out high-speed data transfer to and from the memory. Figure 18.1 shows a configuration of the EtherC. 18.1 * * * * * * * Features Transmission and reception of Ethernet/IEEE802.3 frames Supports 10/100 Mbps receive/transfer Supports full-duplex and half-duplex modes Conforms to IEEE802.3u standard MII (Media Independent Interface) Magic Packet detection and Wake-On-LAN (WOL) signal output Ethernet frame relay function by the TSU Qtag addition and deletion functions conforming to IEEE802.1Q specifications (when frame relay is performed by the TSU) * MAC address filtering function by the multicast (group) address * Ethernet frame receive and transfer control functions by the CAM (Content Addressable Memory) interface signals input externally ISFETH01B_000020020900 Rev. 1.00 Dec. 27, 2005 Page 637 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) E-DMAC0 E-DMAC1 EtherC TSU CAM control Address storage register (32 entries x 48 bits) TSU FIFO control TSU FIFO (0 to 1) TSU FIFO (1 to 0) MAC-0 (port 0) Receive controller Transmit controller MAC-1 (port 1) Receive controller Transmit controller Command status interface Command status interface MII MII PHY-0 PHY-1 Figure 18.1 Configuration of EtherC Rev. 1.00 Dec. 27, 2005 Page 638 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.2 Input/Output Pins Table 18.1 lists the pin configuration of the EtherC. Table 18.1 Pin Configuration Name Transmit clock Receive clock Transmit enable Transmit data Transmit error Receive data valid Receive data Receive error Carrier detection Collision detection Management data clock Management data I/O Link status General-purpose external output Wake-On-LAN Transmit clock Receive clock Port 0 0 0 0 0 0 0 0 0 0 0 0 Abbreviation I/O TX-CLK0* 1 Function TX-EN, ETXD3 to ETXD0, TX-ER timing reference signal RX-DV, ERXD3 to ERXD0, RX-ER timing reference signal Indicates that transmit data is ready on ETXD3 to ETXD0 4-bit transmit data Notifies PHY_LSI of error during transmission Indicates that valid receive data is on ERXD3 to ERXD0 4-bit receive data Identifies error state occurred during data reception Carrier detection signal Collision detection signal Reference clock signal for information transfer via MDIO Bidirectional signal for exchange of management information between this LSI and PHY Inputs link status from PHY Signal indicating value of register-bit (ECMR0-ELB) Signal indicating reception of Magic Packet TX-EN, ETXD3 to ETXD0, TX-ER timing reference signal RX-DV, ERXD3 to ERXD0, RX-ER timing reference signal I I O O O I I I I I O I/O RX-CLK0*1 TX-EN0*1 ETXD03 to 1 ETXD00* TX-ER0*1 RX-DV0*1 ERXD03 to ERXD00*1 RX-ER0*1 CRS0*1 COL0* 1 MDC0*1 MDIO0*1 0 0 0 1 1 LNKSTA0 EXOUT0 WOL0 TX-CLK1* 1 I O O I I RX-CLK1*1 Rev. 1.00 Dec. 27, 2005 Page 639 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Name Transmit enable Transmit data Transmit error Receive data valid Receive data Receive error Carrier detection Collision detection Management data clock Management data I/O Link status General-purpose external output Wake-On-LAN CAM input 0 CAM input 1 Port 1 1 1 1 1 1 1 1 1 1 Abbreviation I/O TX-EN1* 1 Function Indicates that transmit data is ready on ETXD3 to ETXD0 4-bit transmit data Notifies PHY-LSI of error during transmission Indicates that valid receive data is on ERXD3 to ERXD0 4-bit receive data Identifies error state occurred during data reception Carrier detection signal Collision detection signal Reference clock signal for information transfer via MDIO Bidirectional signal for exchange of management information between this LSI and PHY Inputs link status from PHY Signal indicating value of register-bit (ECMR1-ELB) Signal indicating reception of Magic Packet CAM interface signal input 0 CAM interface signal input 1 Signal indicating bus release request when the threshold value set for the data volume in the receive FIFO has been exceeded O O O I I I I I O I/O ETXD13 to ETXD10*1 TX-ER1*1 RX-DV1*1 ERXD13 to ERXD10*1 RX-ER1*1 CRS1*1 COL1* 1 1 MDC1* MDIO1*1 1 1 1 LKNSTA1 EXOUT1 WOL1 CAMSEN0* CAMSEN1* ARBUSY* 3 2 2 I O O I I O Bus release request Notes: 1. MII signal conforming to IEEE802.3u 2. The CAM input signal function is set by the CAMSEL03 to CAMSEL00 and CAMSEL13 to CAMSEL10 in the TSU_FWSLC register. 3. Refer to section 19, Ethernet Controller Direct Memory Access Controller (E-DMAC) and section 19.2.18, Overflow Alert FIFO Threshold Register (FCFTR). Rev. 1.00 Dec. 27, 2005 Page 640 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3 Register Descriptions The EtherC has the following registers. The last number of the abbreviation of the MAC layer interface control register corresponds to the number of the two MAC layer interfaces (MAC-0 or MAC-1). Some numbers have been omitted in the text. For details on addresses and access sizes of registers, see section 23, List of Registers. Reset Register: * Software reset register (ARSTR) MAC Layer Interface Control Registers: Port 0 * EtherC mode register (ECMR0) * EtherC status register (ECSR0) * EtherC interrupt permission register (ECSIPR0) * PHY interface register (PIR0) * MAC address high register (MAHR0) * MAC address low register (MALR0) * Receive frame length register (RFLR0) * PHY status register (PSR0) * Transmit retry over counter register (TROCR0) * Delayed collision detect counter register (CDCR0) * Lost carrier counter register (LCCR0) * Carrier not detect counter register (CNDCR0) * CRC error frame receive counter register (CEFCR0) * Frame receive error counter register (FRECR0) * Too-short frame receive counter register (TSFRCR0) * Too-long frame receive counter register (TLFRCR0) * Residual-bit frame receive counter register (RFCR0) * Multicast address frame receive counter register (MAFCR0) * IPG register (IPGR0) Rev. 1.00 Dec. 27, 2005 Page 641 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Port 1 * EtherC mode register (ECMR1) * EtherC status register (ECSR1) * EtherC interrupt permission register (ECSIPR1) * PHY interface register (PIR1) * MAC address high register (MAHR1) * MAC address low register (MALR1) * Receive frame length register (RFLR1) * PHY status register (PSR1) * Transmit retry over counter register (TROCR1) * Delayed collision detect counter register (CDCR1) * Lost carrier counter register (LCCR1) * Carrier not detect counter register (CNDCR1) * CRC error frame receive counter register (CEFCR1) * Frame receive error counter register (FRECR1) * Too-short frame receive counter register (TSFRCR1) * Too-long frame receive counter register (TLFRCR1) * Residual-bit frame receive counter register (RFCR1) * Multicast address frame receive counter register (MAFCR1) * IPG register (IPGR1) TSU Control Registers: * TSU counter reset register (TSU_CTRST) * Relay enable register (Port 0 to 1) (TSU_FWEN0) * Relay enable register (Port 1 to 0) (TSU_FWEN1) * Relay FIFO size select register (TSU_FCM) * Relay FIFO overflow alert set register (port 0) (TSU_BSYSL0) * Relay FIFO overflow alert set register (port 1) (TSU_BSYSL1) * Transmit/relay priority control mode register (port 0) (TSU_PRISL0) * Transmit/relay priority control mode register (port 1) (TSU_PRISL1) * Receive/relay function set register (port 0 to 1) (TSU_FWSL0) * Receive/relay function set register (port 1 to 0) (TSU_FWSL1) * Relay function set register (common) (TSU_FWSLC) * Qtag addition/deletion set register (port 0 to 1) (TSU_QTAGM0) * Qtag addition/deletion set register (port 1 to 0) (TSU_QTAGM1) Rev. 1.00 Dec. 27, 2005 Page 642 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) * * * * * * * * * * * * * * * * * * * * * Relay status register (TSU_FWSR) Relay status interrupt mask register (TSU_FWINMK) Added Qtag value set register (port 0 to 1) (TSU_ADQT0) Added Qtag value set register (port 1 to 0) (TSU_ADQT1) CAM entry table busy register (TSU_ADSBSY) CAM entry table enable register (TSU_TEN) CAM entry table POST1 to POST4 registers (TSU_POST1 to TSU_POST4) CAM entry table 0 to 31 H registers (TSU_ADRH0 to TSU_ADRH31) CAM entry table 0 to 31 L registers (TSU_ADRL0 to TSU_ADRL31) Transmit frame counter register (port 0) (normal transmission only) (TXNLCR0) Transmit frame counter register (port 0) (normal and error transmission) (TXALCR0) Receive frame counter register (port 0) (normal reception only) (RXNLCR0) Receive frame counter register (port 0) (normal and error reception) (RXALCR0) Relay frame counter register (port 1 to 0) (normal relay only) (FWNLCR0) Relay frame counter register (port 1 to 0) (normal and error relay) (FWALCR0) Transmit frame counter register (port 1) (normal transmission only) (TXNLCR1) Transmit frame counter register (port 1) (normal and error transmission) (TXALCR1) Receive frame counter register (port 1) (normal reception only) (RXNLCR1) Receive frame counter register (port 1) (normal and error reception) (RXALCR1) Relay frame counter register (port 0 to 1) (normal relay only) (FWNLCR1) Relay frame counter register (port 0 to 1) (normal and error relay) (FWALCR1) Rev. 1.00 Dec. 27, 2005 Page 643 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.1 Software Reset Register (ARSTR) ARSTR resets all modules (EtherC and E-DMAC) related to the Ethernet. By writing 1 to the ARST bit in ARSTR, a software reset is issued to all modules related to the Ethernet (for 64 cycles at external bus clock B). The ARST bit is always read as 0. While a software reset is issued, register access to all modules related to the Ethernet is prohibited. Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ARST 0 R/W Software Reset When written with 1, a software reset is issued to all modules related to the Ethernet (for 64 cycles at external bus clock B). Writing 0 does not affect this bit. This bit is always read as 0. While a software reset is issued, register access to all modules related to the Ethernet is prohibited. The following registers are not initialized by a software reset. TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0, TXALCR1, RXNLCR0, RXNLCR1, RXALCR0, RXALCR1, FWNLCR0, FWNLCR1, FWALCR0, FWALCR1 Rev. 1.00 Dec. 27, 2005 Page 644 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.2 EtherC Mode Register (ECMR) ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet controller. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit 31 to 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 MCT 0 R/W Multicast Address Frame Receive Mode 0: Frames other than the multicast address set by the CAM entry table 0 to 31 (H/L) registers are received. However, if the on-chip CAM entry table reference is disabled, all multicast address frames are received. 1: Only the multicast address set by the CAM entry table 0 to 31 (H/L) registers is received. 12 PRCEF 0 R/W CRC Error Frame Reception Enable 0: A receive frame including a CRC error is received as a frame with an error. 1: A receive frame including a CRC error is received as a frame without an error. When this bit is cleared to 0, the CRC error is reflected in ECSR of the E-DMAC and the status of the receive descriptor. When this bit is set to 1, a frame is received as a normal frame. 11 10 0 0 R R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 645 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 9 Bit Name MPDE Initial Value 0 R/W R/W Description Magic Packet Detection Enable Enables or disables Magic Packet detection by hardware to allow activation from the Ethernet. 0: Magic Packet detection is not enabled 1: Magic Packet detection is enabled 8 7 6 RE 0 0 0 R R R/W Reserved These bits are always read as 0. The write value should always be 0. Reception Enable If a switch is made from receive function enabled (RE = 1) to disabled (RE = 0) while a frame is being received, the receive function will be enabled until reception of the corresponding frame is completed. 0: Receive function is disabled 1: Receive function is enabled 5 TE 0 R/W Transmission Enable If a switch is made from transmit function enabled (TE = 1) to disabled (TE = 0) while a frame is being transmitted, the transmit function will be enabled until transmission of the corresponding frame is completed. 0: Transmit function is disabled 1: Transmit function is enabled 4 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 ILB 0 R/W Internal Loop Back Mode Specifies loopback mode in the EtherC. 0: Normal data transmission/reception is performed. 1: Data loopback is performed inside the MAC in the EtherC. Rev. 1.00 Dec. 27, 2005 Page 646 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 2 Bit Name ELB Initial Value 0 R/W R/W Description External Loop Back Mode This bit value is output directly to this LSI's generalpurpose external output pin (EXOUT). This bit is used for loopback mode directives, etc., in the PHYLSI, using the EXOUT pin. In order for PHY-LSI loopback to be implemented using this function, the PHY-LSI must have a pin corresponding to the EXOUT pin. 0: Low-level output from the EXOUT pin 1: High-level output from the EXOUT pin 1 DM 0 R/W Duplex Mode Specifies the EtherC transfer method. 0: Half-duplex transfer is specified 1: Full-duplex transfer is specified 0 PRM 0 R/W Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: EtherC performs normal operation 1: EtherC performs promiscuous mode operation Rev. 1.00 Dec. 27, 2005 Page 647 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.3 EtherC Status Register (ECSR) ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can be notified to the CPU by interrupts. When 1 is written to the BRCRX, PSRTO, LCHNG, MPD, and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR. The interrupts generated due to this status register are indicated in each ECI bit in EESR of the EDMAC0 derived from port0 and the E-DMAC1 derived from port1. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 LCHNG 0 R/W Link Signal Change Indicates that the LNKSTA signal input from the PHYLSI has changed from high to low or low to high. However, signal changes may be detected at the timing at which the LNKSTA function was selected using PACR of PFC. To check the current Link state, refer to the LMON bit in the PHY status register (PSR). 0: Change in the LNKSTA signal has not been detected 1: Change in the LNKSTA signal has been detected (high to low or low to high) 1 MPD 0 R/W Magic Packet Detection Indicates that a Magic Packet has been detected on the line. 0: Magic Packet has not been detected 1: Magic Packet has been detected 31 to 3 Rev. 1.00 Dec. 27, 2005 Page 648 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 0 Bit Name ICD Initial Value 0 R/W R/W Description Illegal Carrier Detection Indicates that the PHY-LSI has detected an illegal carrier on the line. If a change in the signal input from the PHY-LSI occurs before the software recognition period, the correct information may not be obtained. Refer to the timing specification for the PHY-LSI used. 0: PHY-LSI has not detected an illegal carrier on the line 1: PHY-LSI has detected an illegal carrier on the line 18.3.4 EtherC Interrupt Permission Register (ECSIPR) ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 LCHNGIP 0 R/W LINK Signal Changed Interrupt Enable 0: Interrupt notification by the LCHNG bit is disabled 1: Interrupt notification by the LCHNG bit is enabled 1 MPDIP 0 R/W Magic Packet Detection Interrupt Enable 0: Interrupt notification by the MPD bit is disabled 1: Interrupt notification by the MPD bit is enabled 0 ICDIP 0 R/W Illegal Carrier Detection Interrupt Enable 0: Interrupt notification by the ICD bit is disabled 1: Interrupt notification by the ICD bit is enabled 31 to 3 Rev. 1.00 Dec. 27, 2005 Page 649 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.5 PHY Interface Register (PIR) PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI registers via the MII. Bit 31 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 2 MDI MDO Undefined 0 R R/W MII Management Data-In Indicates the level of the MDIO pin. MII Management Data-Out Outputs the value set to this bit from the MDIO pin, when the MMD bit is 1. 1 MMD 0 R/W MII Management Mode Specifies the data read/write direction with respect to the MII. 0: Read direction is indicated 1: Write direction is indicated 0 MDC 0 R/W MII Management Data Clock Outputs the value set to this bit from the MDC pin and supplies the MII with the management data clock. For the method of accessing the MII registers, see section 18.4.6, Accessing MII Registers. Rev. 1.00 Dec. 27, 2005 Page 650 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.6 MAC Address High Register (MAHR) MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit Bit Name Initial Value All 0 R/W R/W Description MAC Address Bits These bits are used to set the upper 32 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'01234567. 31 to 0 MA47 to MA16 18.3.7 MAC Address Low Register (MALR) MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit 31 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MA15 to MA0 All 0 R/W MAC Address Bits 15 to 0 These bits are used to set the lower 16 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'000089AB. Rev. 1.00 Dec. 27, 2005 Page 651 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.8 Receive Frame Length Register (RFLR) RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled. Bit 31 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 RFL11 to RFL0 All 0 R/W Receive Frame Length 11 to 0 The frame length described here refers to all fields from the destination address up to the CRC data. Frame contents from the destination address up to the data are actually transferred to memory. CRC data is not included in the transfer. When data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. H'000 to H'5EE: 1,518 bytes H'5EF: 1,519 bytes H'5F0: 1,520 bytes : : : : H'7FF: 2,047 bytes H'800 to H'FFF: 2,048 bytes Rev. 1.00 Dec. 27, 2005 Page 652 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.9 PHY Status Register (PSR) PSR is a read-only register that can read interface signals from the PHY-LSI. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 LMON 0 R LNKSTA Pin Status The Link status can be read by connecting the Link signal output from the PHY-LSI to the LNKSTA pin. For the polarity, refer to the PHY-LSI specifications to be connected. 31 to 1 18.3.10 Transmit Retry Over Counter Register (TROCR) TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. 31 to 0 TROC31 to All 0 TROC0 Rev. 1.00 Dec. 27, 2005 Page 653 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.11 Delayed Collision Detect Counter Register (CDCR) CDCR is a 32-bit counter that indicates the number of all delayed collisions that accured on the line after the start of data transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Delayed Collision Detect Count These bits indicate the number of all delayed collisions after the start of data transmission. 31 to 0 COSDC31 All 0 to COSDC0 18.3.12 Lost Carrier Counter Register (LCCR) LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by writing to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Lost Carrier Count These bits indicate the number of times the carrier was lost during data transmission. 31 to 0 LCC31 to LCC0 18.3.13 Carrier Not Detect Counter Register (CNDCR) CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Carrier Not Detect Count These bits indicate the number of times the carrier was not detected. 31 to 0 CNDC31 All 0 to CNDC0 Rev. 1.00 Dec. 27, 2005 Page 654 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.14 CRC Error Frame Receive Counter Register (CEFCR) CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description CRC Error Frame Count These bits indicate the count of CRC error frames received. 31 to 0 CEFC31 to All 0 CEFC0 18.3.15 Frame Receive Error Counter Register (FRECR) FRECR is a 32-bit counter that indicates the number of frames for which a receive error was indicated by the RX-ER input pin from the PHY-LSI. FRECR is incremented each time the RXER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Frame Receive Error Count These bits indicate the count of errors during frame reception. 31 to 0 FREC31 to All 0 FREC0 18.3.16 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Too-Short Frame Receive Count These bits indicate the count of frames received with a length of less than 64 bytes. 31 to 0 TSFC31 to All 0 TSFC0 Rev. 1.00 Dec. 27, 2005 Page 655 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.17 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing residual bits is received. In this case, the reception of the frame is indicated in the residual-bit frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Too-Long Frame Receive Count These bits indicate the count of frames received with a length exceeding the value in RFLR. 31 to 0 TLFC31 to All 0 TLFC0 18.3.18 Residual-Bit Frame Receive Counter Register (RFCR) RFCR is a 32-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Residual-Bit Frame Count These bits indicate the count of frames received containing residual bits. 31 to 0 RFC31 to RFC0 Rev. 1.00 Dec. 27, 2005 Page 656 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.19 Multicast Address Frame Receive Counter Register (MAFCR) MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value R/W R/W Description Multicast Address Frame Count These bits indicate the count of multicast frames received. 31 to 0 MAFC31 to All 0 MAFC0 18.3.20 IPG Register (IPGR) IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to section 18.4.8, Operation by IPG Setting.) Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IPG4 to IPG0 H13 R/W Inter Packet Gap Sets the IPG value every 4-bit time. H00: 20-bit time H01: 24-bit time : : : : H13: 96-bit time (Default) H1F: 144-bit time 31 to 5 Rev. 1.00 Dec. 27, 2005 Page 657 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.21 TSU Counter Reset Register (TSU_CTRST) TSU_CTRST clears the transmit, receive, and transfer frame counters to 0. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 8 CTRST 0 R/W TSU Counter Reset When 1 is written to this bit, the values of registers TXNCR0/1, TXALCR0/1, RXNLCR0/1, RXALCR0/1, FWNLCR0/1, and FWALCR0/1 are cleared to 0. Writing 0 does not affect this bit. These bits are always read as 0. 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 31 to 9 18.3.22 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) TSU_FWEN0 enables or disables relay operations from the MAC-0 to MAC-1 (writing to the relay FIFO). Bit 31 Bit Name FWEN0 Initial Value 0 R/W R/W Description Port 0 to 1 Relay Operation Enable 0: Port 0 to 1 relay is disabled 1: Port 0 to 1 relay is enabled When the value of the FCM2 to FCM0 in the TSU FIFO size select register TSU_FCM is set to H4, setting this bit to 1 is prohibited. 30 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 658 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.23 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) TSU_FWEN1 enables or disables relay operations from the MAC-1 to MAC-0 (writing to the relay FIFO). Bit 31 Bit Name FWEN1 Initial Value 0 R/W R/W Description Port 1 to 0 Relay Operation Enable 0: Port 1 to 0 relay is disabled 1: Port 1 to 0 relay is enabled When the value of the FCM2 to FCM0 in the TSU FIFO size select register TSU_FCM is set to H3, setting this bit to 1 is prohibited. 30 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 659 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.24 Relay FIFO Size Select Register (TSU_FCM) TSU_FCM selects the size of the TSU FIFO, used for relay operations between the MAC-0 and MAC-1. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 FCM2 to FCM0 All 0 R/W TSU FIFO Size H0: Port 0 to 1: 3 kbytes H1: Port 0 to 1: 4 kbytes H3: Port 0 to 1: 6 kbytes H5: Port 0 to 1: 1 kbyte H6: Port 0 to 1: 2 kbytes H7: Setting prohibited Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Port 1 to 0: 3 kbytes Port 1 to 0: 2 kbytes Port 1 to 0: Not used Port 1 to 0: 5 kbytes Port 1 to 0: 4 kbytes 31 to 3 H2: Port 0 to 1 : 5 kbytes Port 1 to 0: 1 kbyte H4: Port 0 to 1: Not used Port 1 to 0: 6 kbytes Rev. 1.00 Dec. 27, 2005 Page 660 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) The TSU has an alert function, which informs the MAC-0 and MAC-1 that writing to the TSU FIFO will be disabled when the data volume written in the TSU FIFO during relay operations exceeds a certain threshold. TSU_BSYSL0 sets the threshold of the TSU FIFO when the TSU alerts the MAC-0 that writing to the TSU FIFO will be disabled during relay operations. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 BSYSL05 to All 1 BSYSL00 R/W Sets the threshold of the port 0 to 1 TSU FIFO capacity in 256-byte units when the TSU alerts the MAC-0 that writing in the TSU FIFO will be disabled during relay operations. H00: 0 byte H01: 256 bytes H02: 512 bytes : : H16: 5632 bytes H17: 5888 bytes Settings are disabled for H18 to H3F. (Alert is not always carried out.) When H00 is set, the TSU always alerts the MAC-0 that writing to the TSU FIFO will be disabled. When the value set is above the port 0 to 1 transfer FIFO capacity set by the FCM2 to FCM0 in TSU_FCM, the TSU does not alert the MAC-0 that writing to the TSU FIFO will be disabled. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). When the enable bit of relay operations (the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1) is cleared to 0, the TSU stops alerting the MAC-0 that writing to the TSU FIFO will be disabled. 31 to 6 Rev. 1.00 Dec. 27, 2005 Page 661 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.26 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) The TSU has an alert function, which informs the MAC-0 and MAC-1 that writing to the TSU FIFO will be disabled when the data volume written in the TSU FIFO during relay operations exceeds a certain threshold. TSU_BSYSL1 sets the threshold of the TSU FIFO when the TSU alerts the MAC-1 to writing to the TSU FIFO will be disabled during relay operations. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 BSYSL15 to All 1 BSYSL10 R/W Sets the threshold of the port 1 to 0 TSU FIFO capacity in 256-byte units when the TSU alerts the MAC-1 that writing in the TSU FIFO will be disabled during relay operations. H00: 0 byte H01: 256 bytes H02: 512 bytes : : H16: 5632 bytes H17: 5888 bytes Settings are disabled for H18 to H3F. (Alert is not always carried out.) When H00 is set, the TSU always alerts the MAC-1 that writing to the transfer FIFO will be disabled. When the value set is above the port 1 to 0 TSU FIFO capacity set by the FCM2 to FCM0 in TSU_FCM, the TSU does not alert the MAC-1 to writing that the TSU FIFO will be disabled. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). When the enable bit of relay operations (the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1) is cleared to 0, the TSU stops alerting the MAC-1 to writing to the TSU FIFO will be disabled. 31 to 6 Rev. 1.00 Dec. 27, 2005 Page 662 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.27 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0) TSU_PRISL0 sets the priority control mode when the transmission request from the E-DMAC to MAC-0 come into collision with port 1 to 0 relay operations. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14 to 12 PRIMD02 to All 0 PRIMD00 R/W Sets the priority control mode of MAC-0 transmission and port 1 to 0 relay operations. H0: Round robin H1: Transmission priority H2: Relay priority H4: Round robin, however switched to relay priority when TSU FIFO use amount exceeds the set value of PRISL07 to PRISL00 H5: Transmission priority, however switched to relay priority when TSU FIFO use amount exceeds the set value of PRISL07 to PRISL00 Others: Setting prohibited 11 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 31 to 15 Rev. 1.00 Dec. 27, 2005 Page 663 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 7 to 0 Bit Name PRISL07 to PRISL00 Initial Value All 0 R/W R/W Description Sets the threshold of the port 1 to 0 TSU FIFO capacity in 64-byte units in the event switching to relay priority when PRIMD02 to PRIMD00 are set to H4 or H5. H00: 0 byte H01: 64 bytes H02: 128 bytes : : H5E: 6016 bytes H5F: 6080 bytes Settings are disabled for H60 to HFF. When set to H00, relay always takes priority. When the value set is above the port 1 to 0 TSU FIFO capacity set by the FCM2 to FCM0 in TSU_FCM, if the PRIMD02 to PRIMD00 are H4, round robin will always be set. If the PRIMD02 to PRIMD00 are H5, transmission always takes priority. 18.3.28 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1) TSU_PRISL1 sets the priority control mode when the transmission request from the E-DMAC to MAC-1 come into collision with port 0 to 1 relay operations. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 15 Rev. 1.00 Dec. 27, 2005 Page 664 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit Bit Name Initial Value R/W R/W Description Sets the priority control mode of MAC-1 transmission and port 0 to 1 relay operations. H0: Round robin H1: Transmission priority H2: Relay priority H4: Round robin, however switched to relay priority when TSU FIFO use amount exceeds the set value of PRISL17 to PRISL10 H5: Transmission priority, however switched to relay priority when TSU FIFO use amount exceeds the set value of PRISL17 to PRISL10 Others: Setting prohibited 14 to 12 PRIMD12 to All 0 PRIMD10 11 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 PRISL17 to PRISL10 All 0 R/W Sets the threshold value of the port 0 to 1 TSU FIFO capacity in 64-byte units in the event switching to relay priority when PRIMD12 to PRIMD10 are set to H4 or H5. H00: 0 byte H01: 64 bytes H02: 128 bytes : : H5E: 6016 bytes H5F: 6080 bytes Settings are disabled for H60 to HFF. When set to H00, relay always takes priority. When the value set is above the port 0 to 1 TSU FIFO capacity set by the FCM2 to FCM0 in TSU_FCM, if the PRIMD12 to PRIMD10 are H4, round robin will always be set. If the PRIMD12 to PRIMD10 are H5, transmission always takes priority. Rev. 1.00 Dec. 27, 2005 Page 665 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.29 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0) TSU_FWSL0 sets the processing method of each frame in port 0 reception and port 0 to 1 relay operations. In receiving a frame, the processing method can be determined by referring to the CAM evaluation results when the multicast frame and the destination are other than this LSI. (For details, refer to section 18.4.4, CAM Function.) Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 FW40 0 R/W Sets the processing method when frames from port 0 are addressed to this LSI 0: Frames are not relayed 1: Frames are relayed to port 1 10 FW30 0 R/W Sets the processing method when frames from port 0 are Broadcast. 0: Frames are not relayed 1: Frames are relayed to port 1 9 FW20 0 R/W Sets the processing method when frames from port 0 are multicast. 0: CAM hit: Frames are relayed to port 1 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 1 8 FW10 0 R/W Sets the processing method when frames from port 0 are addressed to other than this LSI. 0: CAM hit: Frames are relayed to port 1 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 1 31 to 12 Rev. 1.00 Dec. 27, 2005 Page 666 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18.3.30 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1) TSU_FWSL1 sets the processing method of each frame in port 1 reception and port 1 to 0 relay operations. In receiving a frame, the processing method can be determined by referring to the CAM evaluation results when the multicast frame and the destination are other than this LSI. (For details, refer to section 18.4.4, CAM Function.) Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 FW41 0 R/W Sets the processing method when frames from port 1 are addressed to this LSI 0: Frames are not relayed 1: Frames are relayed to port 0 10 FW31 0 R/W Sets the processing method when frames from port 1 are Broadcast. 0: Frames are not relayed 1: Frames are relayed to port 0 9 FW21 0 R/W Sets the processing method when frames from port 1 are multicast. 0: CAM hit: Frames are relayed to port 0 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 0 31 to 12 Rev. 1.00 Dec. 27, 2005 Page 667 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 8 Bit Name FW11 Initial Value 0 R/W R/W Description Sets the processing method when frames from port 1 are addressed to other than this LSI. 0: CAM hit: Frames are relayed to port 0 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 0 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 668 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.31 Relay Function Set Register (Common) (TSU_FWSLC) When the CAM is used, the referred area in the CAM entry table (partially or wholly) can be specified by the TSU_POST1 to TSU_POST4 registers. When the CAM is installed outside this LSI, the evaluation results of the external CAM can be referred by input on the CAMSEN0 and CAMSEN1 pins. (For details, refer to section 18.4.4, CAM Function.) TSU_FWSLC enables settings by the TSU_POST1 to TSU_POST4 registers and conditions for referring signals on the CAMSEN0 and CAMSEN1 pins. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 POSTENU 0 R/W Enables the settings of the POST field of CAM entry tables 0 to 15 (settings by the TSU_POST1 and TSU_POST2 registers). 0: Disables the settings of the POST field. (The CAM entry table is referred only in port 0 reception.) 1: Enables the settings of the POST field. (The CAM entry table reference conditions follow the POST field settings.) 12 POSTENL 0 R/W Enables the settings of the POST field of CAM entry tables 16 to 31 (settings by the TSU_POST3 and TSU_POST4 registers). 0: Disables the settings of the POST field. (The CAM entry table is referred only in port 1 reception.) 1: Enables the settings of the POST field. (The CAM entry table reference conditions follow the POST field settings.) 11 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 31 to 14 Rev. 1.00 Dec. 27, 2005 Page 669 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 7 6 5 4 Bit Name Initial Value R/W R/W R/W R/W R/W Description These bits set the conditions for referring signals on the CAMSEN0 pin. By setting multiple bits to 1, multiple conditions can be selected. CAMSEL03: Refers signals on the CAMSEN0 pin in port 0 reception CAMSEL02: Refers signals on the CAMSEN0 pin in port 0 to 1 relay CAMSEL01: Refers signals on the CAMSEN0 pin in port 1 reception CAMSEL00: Refers signals on the CAMSEN0 pin in port 1 to 0 relay CAMSEL03 1 CAMSEL02 0 CAMSEL01 0 CAMSEL00 0 3 2 1 0 CAMSEL13 0 CAMSEL12 0 CAMSEL11 1 CAMSEL10 0 R/W R/W R/W R/W These bits set the conditions for referring signals on the CAMSEN1 pin. By setting multiple bits to 1, multiple conditions can be selected. CAMSEL13: Refers signals on the CAMSEN1 pin in port 0 reception CAMSEL12: Refers signals on the CAMSEN1 pin in port 0 to 1 relay CAMSEL11: Refers signals on the CAMSEN1 pin in port 1 reception CAMSEL10: Refers signals on the CAMSEN1 pin in port 1 to 0 relay Rev. 1.00 Dec. 27, 2005 Page 670 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.32 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAGM0) TSU_QTAGM0 sets the functions adding Qtag from the normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) and deleting Qtags from IEEE802.1Q frames (with Qtag) to normal Ethernet frames (no Qtag) during port 0 to 1 relay operations. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1,0 QTAGM01, All 0 QTAGM00 R/W These bits set Qtag adding and deleting functions during port 0 to 1 relay operations. H0: No Qtag adding and deleting functions H1: No Qtag adding and deleting functions (same as H0) H2: Deletes Qtag from frames with Qtag H3: Adds Qtag to frames with no Qtag Writing to this register is prohibited, after transfer operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). 31 to 2 Rev. 1.00 Dec. 27, 2005 Page 671 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.33 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAGM1) TSU_QTAGM1 sets the functions adding Qtag from the normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) and deleting Qtags from IEEE802.1Q frames (with Qtag) to normal Ethernet frames (no Qtag) during port 1 to 0 relay operations. Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 QTAGM11, All 0 QTAGM10 R/W These bits set Qtag adding and deleting functions during port 1 to 0 relay operations. H0: No Qtag adding and deleting functions H1: No Qtag adding and deleting functions (same as H0) H2: Deletes Qtag from frames with Qtag H3: Adds Qtag to frames with no Qtag Writing to this register is prohibited, after transfer operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). 31 to 2 Rev. 1.00 Dec. 27, 2005 Page 672 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.34 Relay Status Register (TSU_FWSR) TSU_FWSR is a 32-bit readable/writable register that indicates the status during relay operations. By setting the TSU status interrupt mask register (TSU_FWINMK), this status can be notified to the CPU as an interrupt source. The status bit set to 1 will be cleared to 0 by writing 1 to corresponding bit. (The status bit retains the value until it is cleared to 0.) Interrupts generated due to this status register is EINT2. For details on the priority order of interrupts, refer to section 8.3.5, Interrupt Exception Handling and Priority in section 8, Interrupt Controller (INTC). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 27 TINT40 0 R/W MAC-0 Carrier Not Detect Set to 1 when a carrier not detect has occured in the MAC-0 26 TINT30 0 R/W MAC-0 Carrier Lost Set to 1 when a carrier is lost during data transmission in the MAC-0 25 TINT20 0 R/W MAC-0 Collision Detect Set to 1 when a collision of frames is detected in the MAC-0 24 TINT10 0 R/W MAC-0 Transmission Time Out Set to 1 when frames were unable to be transmitted in 16 transmission attempts including the retransfer in the MAC-0 23 OVF0 0 R/W Port 0 to 1 TSU FIFO Overflow Detect Set to 1 when a port 0 to 1 TSU FIFO overflow has occured 22 RBSY0 0 R/W MAC-0 Overflow Alert Signal Output Set to 1 when the threshold of TSU_BSYSL0 is valid and exceeded 21 0 R Reserved This bit is always read as 0. The write value should always be 0. 31 to 28 Rev. 1.00 Dec. 27, 2005 Page 673 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 20 Bit Name RINT50 Initial Value 0 R/W R/W Description MAC-0 Residual Bit Frame Receive Set to 1 when frames containing residual bits (less than an 8-bit unit) are received in the MAC-0 19 RINT40 0 R/W MAC-0 Exceeding Byte Frame Receive Set to 1 when frames exceeding the value set by RFLR0 are received in the MAC-0 18 RINT30 0 R/W MAC-0 Less 64-Byte Frame Receive Set to 1 when frames with a length of less than 64 bytes are received in the MAC-0 17 RINT20 0 R/W MAC-0 Frame Receive Error Set to 1 when a receive error is detected on the RX-ER pin input from the PHY in the MAC-0 16 RINT10 0 R/W MAC-0 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the MAC-0 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 TINT41 0 R/W MAC-1 Carrier Not Detect Set to 1 when a carrier not detect has occured in the MAC-1 10 TINT31 0 R/W MAC-1 Carrier Lost Set to 1 when a carrier is lost during data transmission in the MAC-1 9 TINT21 0 R/W MAC-1 Collision Detect Set to 1 when a collision of frames is detected in the MAC-1 8 TINT11 0 R/W MAC-1 Transmission Time Out Set to 1 when frames were unable to be transmitted in 16 transmission attempts including the retransfer in the MAC-1 7 OVF1 0 R/W Port 1 to 0 TSU FIFO Overflow Detect Set to 1 when a port 1 to 0 TSU FIFO overflow has occured Rev. 1.00 Dec. 27, 2005 Page 674 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 6 Bit Name RBSY1 Initial Value 0 R/W R/W Description MAC-1 Overflow Alert Signal Output Set to 1 when the threshold of TSU_BSYSL1 is valid and exceeded 5 0 R Reserved This bit is always read as 0. The write value should always be 0. 4 RINT51 0 R/W MAC-1 Residual Bit Frame Receive Set to 1 when frames containing residual bits (less than an 8-bit unit) are received in the MAC-1 3 RINT41 0 R/W MAC-1 Exceeding Byte Frame Receive Set to 1 when frames exceeding the value set by RFLR1 are received in the MAC-1 2 RINT31 0 R/W MAC-1 Less 64-Byte Frame Receive Set to 1 when frames with a length of less than 64 bytes are received in the MAC-1 1 RINT21 0 R/W MAC-1 Frame Receive Error Set to 1 when a receive error is detected on the RX-ER pin input from the PHY in the MAC-1 0 RINT11 0 R/W MAC-1 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the MAC-1 18.3.35 Relay Status Interrupt Mask Register (TSU_FWINMK) TSU_FWINMK is a 32-bit readable/writable register that sets the interrupt mask for status bits in TSU_FWSR. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 27 TINTM40 0 R/W MAC-0 Carrier Not Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 31 to 28 Rev. 1.00 Dec. 27, 2005 Page 675 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 26 Bit Name TINTM30 Initial Value 0 R/W R/W Description MAC-0 Carrier Lost Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 25 TINTM20 0 R/W MAC-0 Collision Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 24 TINTM10 0 R/W MAC-0 Transmission Time Out Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 23 OVFM0 0 R/W Port 0 to 1 TSU FIFO Overflow Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 22 RBSYM0 0 R/W MAC-0 Overflow Alert Signal Output Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 21 0 R Reserved This bit is always read as 0. The write value should always be 0. 20 RINTM50 0 R/W MAC-0 Residual Bit Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 19 RINTM40 0 R/W MAC-0 Exceeding Byte Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 18 RINTM30 0 R/W MAC-0 Less 64-Byte Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 17 RINTM20 0 R/W MAC-0 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled Rev. 1.00 Dec. 27, 2005 Page 676 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 16 Bit Name RINTM10 Initial Value 0 R/W R/W Description MAC-0 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 TINTM41 0 R/W MAC-1 Carrier Not Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 10 TINTM31 0 R/W MAC-1 Carrier Lost Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 9 TINTM21 0 R/W MAC-1 Collision Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 8 TINTM11 0 R/W MAC-1 Transmission Time Out Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 7 OVFM1 0 R/W Port 1 to 0 TSU FIFO Overflow Detect Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 6 RBSYM1 0 R/W MAC-1 Overflow Alert Signal Output Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 5 0 R Reserved This bit is always read as 0. The write value should always be 0. 4 RINTM51 0 R/W MAC-1 Residual Bit Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled Rev. 1.00 Dec. 27, 2005 Page 677 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 3 Bit Name RINTM41 Initial Value 0 R/W R/W Description MAC-1 Exceeding Byte Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 2 RINTM31 0 R/W MAC-1 Less 64-Byte Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 1 RINTM21 0 R/W MAC-1 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled 0 RINTM11 0 R/W MAC-1 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled Rev. 1.00 Dec. 27, 2005 Page 678 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.36 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0) TSU_ADQT0 sets Qtag data to be added in the conversion of normal Ethernet frames (without Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (when setting the QTAGM01 to QTAGM00 bits in TSU_QTAGM0 to H3 in the use of the Qtag addition function). Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value R/W R/W Description Be sure to set the value of the upper 16 bits (QTAG031 to QTAG016) as H8100 (indicates that it is the Qtag extension frame format). The value read is H8100. Priority Setting (PRT) These bits set the processing priority of frames with Qtag. For details on the settings, refer to the specifications on Qtag control specified in IEEE802.1Q. R Reserved This bit is always read as 0. The write value should always be 0. 11 to 0 QTAG011 to H000 QTAG000 R/W V-LAN ID Setting (VID) These bits set the flames with Qtag to be used in the systems supporting V-LAN. For details on settings, refer to the specifications on Qtag control specified in IEEE802.1Q. 31 to 16 QTAG031 to H8100 QTAG016 15 to 13 QTAG015 to H0 QTAG013 R/W 12 0 Rev. 1.00 Dec. 27, 2005 Page 679 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.37 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1) TSU_ADQT1 sets Qtag data to be added in the conversion of normal Ethernet frames (without Qtag) to IEEE802.1Q frames (with Qtag) in port 1 to 0 relay operations (when setting the QTAGM11 to QTAGM10 bits in TSU_QTAGM1 to H3 in the use of the Qtag addition function). Writing to this register is prohibited, after relay operations have been enabled once (after the FWEN0 in TSU_FWEN0 or the FWEN1 in TSU_FWEN1 is set to 1). Bit Bit Name Initial Value R/W R/W Description Be sure to set the value of the upper 16 bits (QTAG131 to QTAG116) as H8100 (indicates that it is the Qtag extension frame format). The value read is H8100. Priority Setting (PRT) These bits set the processing priority of frames with Qtag. For details on the settings, refer to the specifications on Qtag control specified in IEEE802.1Q. R Reserved This bit is always read as 0. The write value should always be 0. 11 to 0 QTAG111 to H000 QTAG100 R/W V-LAN ID Setting (VID) These bits set the flames with Qtag to be used in the systems supporting V-LAN. For details on settings, refer to the specifications on Qtag control specified in IEEE802.1Q. 31 to 16 QTAG131 to H8100 QTAG116 15 to 13 QTAG115 to H0 QTAG113 R/W 12 0 Rev. 1.00 Dec. 27, 2005 Page 680 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.38 CAM Entry Table Busy Register (TSU_ADSBSY) When CAM entry table registers (TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to TSU_ADRL31) are set by register writing, the ADSBSY bit in this register is set to 1 (when the process of reflecting the contents of the CAM entry table register in the CAM controller is completed inside the TSU, the ADSBSY bit is automatically restored to 0). Accessing to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited, while the ADSBSY bit in this register is set to 1. This register is a read-only status register, and writing to this register is prohibited. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ADSBSY 0 R CAM Entry Table Setting Busy When TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 are set by register writing, the ADSBSY bit is set to 1. When the process of reflecting the contents of the CAM entry table register in the CAM controller is completed inside the TSU, the ADSBSY bit is automatically restored to 0. Accessing to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited, while this bit is set to 1. Writing to this register is also prohibited. 31 to 1 Rev. 1.00 Dec. 27, 2005 Page 681 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.39 CAM Entry Table Enable Register (TSU_TEN) TSU_TEN enables or disables to refer CAM Entry Table registers (TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31). Bit 31 Bit Name TEN0 Initial Value 0 R/W R/W Description CAM Entry Table 0 (TSU_ADRH0 and TSU_ADRL0) Setting 0: Disabled 1: Enabled 30 TEN1 0 R/W CAM Entry Table 1 (TSU_ADRH1 and TSU_ADRL1) Setting 0: Disabled 1: Enabled 29 TEN2 0 R/W CAM Entry Table 2 (TSU_ADRH2 and TSU_ADRL2) Setting 0: Disabled 1: Enabled 28 TEN3 0 R/W CAM Entry Table 3 (TSU_ADRH3 and TSU_ADRL3) Setting 0: Disabled 1: Enabled 27 TEN4 0 R/W CAM Entry Table 4 (TSU_ADRH4 and TSU_ADRL4) Setting 0: Disabled 1: Enabled 26 TEN5 0 R/W CAM Entry Table 5 (TSU_ADRH5 and TSU_ADRL5) Setting 0: Disabled 1: Enabled 25 TEN6 0 R/W CAM Entry Table 6 (TSU_ADRH6 and TSU_ADRL6) Setting 0: Disabled 1: Enabled Rev. 1.00 Dec. 27, 2005 Page 682 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 24 Bit Name TEN7 Initial Value 0 R/W R/W Description CAM Entry Table 7 (TSU_ADRH7 and TSU_ADRL7) Setting 0: Disabled 1: Enabled 23 TEN8 0 R/W CAM Entry Table 8 (TSU_ADRH8 and TSU_ADRL8) Setting 0: Disabled 1: Enabled 22 TEN9 0 R/W CAM Entry Table 9 (TSU_ADRH9 and TSU_ADRL9) Setting 0: Disabled 1: Enabled 21 TEN10 0 R/W CAM Entry Table 10 (TSU_ADRH10 and TSU_ADRL10) Setting 0: Disabled 1: Enabled 20 TEN11 0 R/W CAM Entry Table 11 (TSU_ADRH11 and TSU_ADRL11) Setting 0: Disabled 1: Enabled 19 TEN12 0 R/W CAM Entry Table 12 (TSU_ADRH12 and TSU_ADRL12) Setting 0: Disabled 1: Enabled 18 TEN13 0 R/W CAM Entry Table 13 (TSU_ADRH13 and TSU_ADRL13) Setting 0: Disabled 1: Enabled 17 TEN14 0 R/W CAM Entry Table 14 (TSU_ADRH14and TSU_ADRL14) Setting 0: Disabled 1: Enabled Rev. 1.00 Dec. 27, 2005 Page 683 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 16 Bit Name TEN15 Initial Value 0 R/W R/W Description CAM Entry Table 15 (TSU_ADRH10 and TSU_ADRL15) Setting 0: Disabled 1: Enabled 15 TEN16 0 R/W CAM Entry Table 16 (TSU_ADRH16 and TSU_ADRL16) Setting 0: Disabled 1: Enabled 14 TEN17 0 R/W CAM Entry Table 17 (TSU_ADRH17 and TSU_ADRL17) Setting 0: Disabled 1: Enabled 13 TEN18 0 R/W CAM Entry Table 18 (TSU_ADRH18 and TSU_ADRL18) Setting 0: Disabled 1: Enabled 12 TEN19 0 R/W CAM Entry Table 19 (TSU_ADRH19 and TSU_ADRL19) Setting 0: Disabled 1: Enabled 11 TEN20 0 R/W CAM Entry Table 20 (TSU_ADRH20 and TSU_ADRL20) Setting 0: Disabled 1: Enabled 10 TEN21 0 R/W CAM Entry Table 21 (TSU_ADRH21 and TSU_ADRL21) Setting 0: Disabled 1: Enabled 9 TEN22 0 R/W CAM Entry Table 22 (TSU_ADRH22 and TSU_ADRL22) Setting 0: Disabled 1: Enabled Rev. 1.00 Dec. 27, 2005 Page 684 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 8 Bit Name TEN23 Initial Value 0 R/W R/W Description CAM Entry Table 23 (TSU_ADRH23 and TSU_ADRL23) Setting 0: Disabled 1: Enabled 7 TEN24 0 R/W CAM Entry Table 24 (TSU_ADRH24 and TSU_ADRL24) Setting 0: Disabled 1: Enabled 6 TEN25 0 R/W CAM Entry Table 25 (TSU_ADRH20 and TSU_ADRL25) Setting 0: Disabled 1: Enabled 5 TEN26 0 R/W CAM Entry Table 26 (TSU_ADRH20 and TSU_ADRL26) Setting 0: Disabled 1: Enabled 4 TEN27 0 R/W CAM Entry Table 27 (TSU_ADRH27 and TSU_ADRL27) Setting 0: Disabled 1: Enabled 3 TEN28 0 R/W CAM Entry Table 28 (TSU_ADRH28 and TSU_ADRL28) Setting 0: Disabled 1: Enabled 2 TEN29 0 R/W CAM Entry Table 29 (TSU_ADRH29 and TSU_ADRL29) Setting 0: Disabled 1: Enabled 1 TEN30 0 R/W CAM Entry Table 30 (TSU_ADRH30 and TSU_ADRL30) Setting 0: Disabled 1: Enabled Rev. 1.00 Dec. 27, 2005 Page 685 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 0 Bit Name TEN31 Initial Value 0 R/W R/W Description CAM Entry Table 31 (TSU_ADRH31 and TSU_ADRL31) Setting 0: Disabled 1: Enabled 18.3.40 CAM Entry Table POST1 Register (TSU_POST1) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST1 specifies the conditions for referring to TSU_ADRH0 to TSU_ADRH7 and TSU_ADRL0 to TSU_ADRL7. The settings of this register are valid when the POSENU bit in TSU_FWSLC is set to 1. Bit 31 to 28 Bit Name POST03 to POST00 Initial Value All 0 R/W R/W Description These bits set the conditions for referring to the CAM entry table 0. By setting multiple bits to 1, multiple conditions can be selected. POST03: The CAM entry table 0 is referred in port 0 reception. POST02: The CAM entry table 0 is referred in port 0 to 1 relay. POST01: The CAM entry table 0 is referred in port 1 reception. POST00: The CAM entry table 0 is referred in port 1 to 0 relay. 27 to 24 POST13 to POST10 All 0 R/W These bits set the conditions for referring to the CAM entry table 1. By setting multiple bits to 1, multiple conditions can be selected. POST13: The CAM entry table 1 is referred in port 0 reception. POST12: The CAM entry table 1 is referred in port 0 to 1 relay. POST11: The CAM entry table 1 is referred in port 1 reception. POST10: The CAM entry table 1 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 686 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit Bit Name Initial Value All 0 R/W R/W Description These bits set the conditions for referring to the CAM entry table 2. By setting multiple bits to 1, multiple conditions can be selected. POST23: The CAM entry table 2 is referred in port 0 reception. POST22: The CAM entry table 2 is referred in port 0 to 1 relay. POST21: The CAM entry table 2 is referred in port 1 reception. POST20: The CAM entry table 2 is referred in port 1 to 0 relay. 23 to 20 POST23 to POST20 19 to 16 POST33 to POST30 All 0 R/W These bits set the conditions for referring to the CAM entry table 3. By setting multiple bits to 1, multiple conditions can be selected. POST33: The CAM entry table 3 is referred in port 0 reception. POST32: The CAM entry table 3 is referred in port 0 to 1 relay. POST31: The CAM entry table 3 is referred in port 1 reception. POST30: The CAM entry table 3 is referred in port 1 to 0 relay. 15 to 12 POST43 to POST40 All 0 R/W These bits set the conditions for referring to the CAM entry table 4. By setting multiple bits to 1, multiple conditions can be selected. POST43: The CAM entry table 4 is referred in port 0 reception. POST42: The CAM entry table 4 is referred in port 0 to 1 relay. POST41: The CAM entry table 4 is referred in port 1 reception. POST40: The CAM entry table 4 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 687 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 11 to 8 Bit Name POST53 to POST50 Initial Value All 0 R/W R/W Description These bits set the conditions for referring to the CAM entry table 5. By setting multiple bits to 1, multiple conditions can be selected. POST53: The CAM entry table 5 is referred in port 0 reception. POST52: The CAM entry table 5 is referred in port 0 to 1 relay. POST51: The CAM entry table 5 is referred in port 1 reception. POST50: The CAM entry table 5 is referred in port 1 to 0 relay. 7 to 4 POST63 to POST60 All 0 R/W These bits set the conditions for referring to the CAM entry table 6. By setting multiple bits to 1, multiple conditions can be selected. POST63: The CAM entry table 6 is referred in port 0 reception. POST62: The CAM entry table 6 is referred in port 0 to 1 relay. POST61: The CAM entry table 6 is referred in port 1 reception. POST60: The CAM entry table 6 is referred in port 1 to 0 relay. 3 to 0 POST73 to POST70 All 0 R/W These bits set the conditions for referring to the CAM entry table 7. By setting multiple bits to 1, multiple conditions can be selected. POST73: The CAM entry table 7 is referred in port 0 reception. POST72: The CAM entry table 7 is referred in port 0 to 1 relay. POST71: The CAM entry table 7 is referred in port 1 reception. POST70: The CAM entry table 7 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 688 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.41 CAM Entry Table POST2 Register (TSU_POST2) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST2 specifies the conditions for referring to TSU_ADRH8 to TSU_ADRH15 and TSU_ADRL8 to TSU_ADRL15. The settings of this register are valid when the POSENU bit in TSU_FWSLC is set to 1. Bit 31 to 28 Bit Name POST83 to POST80 Initial Value All 0 R/W R/W Description These bits set the conditions for referring to the CAM entry table 8. By setting multiple bits to 1, multiple conditions can be selected. POST83: The CAM entry table 8 is referred in port 0 reception. POST82: The CAM entry table 8 is referred in port 0 to 1 relay. POST81: The CAM entry table 8 is referred in port 1 reception. POST80: The CAM entry table 8 is referred in port 1 to 0 relay. 27 to 24 POST93 to POST90 All 0 R/W These bits set the conditions for referring to the CAM entry table 9. By setting multiple bits to 1, multiple conditions can be selected. POST93: The CAM entry table 9 is referred in port 0 reception. POST92: The CAM entry table 9 is referred in port 0 to 1 relay. POST91: The CAM entry table 9 is referred in port 1 reception. POST90: The CAM entry table 9 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 689 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 23 to 20 Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 10. By setting multiple bits to 1, multiple conditions can be selected. POST103: The CAM entry table 10 is referred in port 0 reception. POST102: The CAM entry table 10 is referred in port 0 to 1 relay. POST101: The CAM entry table 10 is referred in port 1 reception. POST100: The CAM entry table 10 is referred in port 1 to 0 relay. POST103 to All 0 POST100 19 to 16 POST113 to All 0 POST110 R/W These bits set the conditions for referring to the CAM entry table 11. By setting multiple bits to 1, multiple conditions can be selected. POST113: The CAM entry table 11 is referred in port 0 reception. POST112: The CAM entry table 11 is referred in port 0 to 1 relay. POST111: The CAM entry table 11 is referred in port 1 reception. POST110: The CAM entry table 11 is referred in port 1 to 0 relay. 15 to 12 POST123 to All 0 POST120 R/W These bits set the conditions for referring to the CAM entry table 12. By setting multiple bits to 1, multiple conditions can be selected. POST123: The CAM entry table 12 is referred in port 0 reception. POST122: The CAM entry table 12 is referred in port 0 to 1 relay. POST121: The CAM entry table 12 is referred in port 1 reception. POST120: The CAM entry table 12 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 690 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 11 to 8 Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 13. By setting multiple bits to 1, multiple conditions can be selected. POST133: The CAM entry table 13 is referred in port 0 reception. POST132: The CAM entry table 13 is referred in port 0 to 1 relay. POST131: The CAM entry table 13 is referred in port 1 reception. POST130: The CAM entry table 13 is referred in port 1 to 0 relay. POST133 to All 0 POST130 7 to 4 POST143 to All 0 POST140 R/W These bits set the conditions for referring to the CAM entry table 14. By setting multiple bits to 1, multiple conditions can be selected. POST143: The CAM entry table 14 is referred in port 0 reception. POST142: The CAM entry table 14 is referred in port 0 to 1 relay. POST141: The CAM entry table 14 is referred in port 1 reception. POST140: The CAM entry table 14 is referred in port 1 to 0 relay. 3 to 0 POST153 to All 0 POST150 R/W These bits set the conditions for referring to the CAM entry table 15. By setting multiple bits to 1, multiple conditions can be selected. POST153: The CAM entry table 15 is referred in port 0 reception. POST152: The CAM entry table 15 is referred in port 0 to 1 relay. POST151: The CAM entry table 15 is referred in port 1 reception. POST150: The CAM entry table 15 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 691 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.42 CAM Entry Table POST3 Register (TSU_POST3) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST3 specifies the conditions for referring to TSU_ADRH16 to TSU_ADRH23 and TSU_ADRL16 to TSU_ADRL23. The settings of this register are valid when the POSENU bit in TSU_FWSLC is set to 1. Bit Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 16. By setting multiple bits to 1, multiple conditions can be selected. POST163: The CAM entry table 16 is referred in port 0 reception. POST162: The CAM entry table 16 is referred in port 0 to 1 relay. POST161: The CAM entry table 16 is referred in port 1 reception. POST160: The CAM entry table 16 is referred in port 1 to 0 relay. 27 to 24 POST173 to All 0 POST170 R/W These bits set the conditions for referring to the CAM entry table 17. By setting multiple bits to 1, multiple conditions can be selected. POST173: The CAM entry table 17 is referred in port 0 reception. POST172: The CAM entry table 17 is referred in port 0 to 1 relay. POST171: The CAM entry table 17 is referred in port 1 reception. POST170: The CAM entry table 17 is referred in port 1 to 0 relay. 31 to 28 POST163 to All 0 POST160 Rev. 1.00 Dec. 27, 2005 Page 692 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 18. By setting multiple bits to 1, multiple conditions can be selected. POST183: The CAM entry table 18 is referred in port 0 reception. POST182: The CAM entry table 18 is referred in port 0 to 1 relay. POST181: The CAM entry table 18 is referred in port 1 reception. POST180: The CAM entry table 18 is referred in port 1 to 0 relay. 23 to 20 POST183 to All 0 POST180 19 to 16 POST193 to All 0 POST190 R/W These bits set the conditions for referring to the CAM entry table 19. By setting multiple bits to 1, multiple conditions can be selected. POST193: The CAM entry table 19 is referred in port 0 reception. POST192: The CAM entry table 19 is referred in port 0 to 1 relay. POST191: The CAM entry table 19 is referred in port 1 reception. POST190: The CAM entry table 19 is referred in port 1 to 0 relay. 15 to 12 POST203 to All 0 POST200 R/W These bits set the conditions for referring to the CAM entry table 20. By setting multiple bits to 1, multiple conditions can be selected. POST203: The CAM entry table 20 is referred in port 0 reception. POST202: The CAM entry table 20 is referred in port 0 to 1 relay. POST201: The CAM entry table 20 is referred in port 1 reception. POST200: The CAM entry table 20 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 693 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 11 to 8 Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 21. By setting multiple bits to 1, multiple conditions can be selected. POST213: The CAM entry table 21 is referred in port 0 reception. POST212: The CAM entry table 21 is referred in port 0 to 1 relay. POST211: The CAM entry table 21 is referred in port 1 reception. POST210: The CAM entry table 21 is referred in port 1 to 0 relay. POST213 to All 0 POST210 7 to 4 POST223 to All 0 POST220 R/W These bits set the conditions for referring to the CAM entry table 22. By setting multiple bits to 1, multiple conditions can be selected. POST223: The CAM entry table 22 is referred in port 0 reception. POST222: The CAM entry table 22 is referred in port 0 to 1 relay. POST221: The CAM entry table 22 is referred in port 1 reception. POST220: The CAM entry table 22 is referred in port 1 to 0 relay. 3 to 0 POST233 to All 0 POST230 R/W These bits set the conditions for referring to the CAM entry table 23. By setting multiple bits to 1, multiple conditions can be selected. POST233: The CAM entry table 23 is referred in port 0 reception. POST232: The CAM entry table 23 is referred in port 0 to 1 relay. POST231: The CAM entry table 23 is referred in port 1 reception. POST230: The CAM entry table 23 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 694 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.43 CAM Entry Table POST4 Register (TSU_POST4) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST4 specifies the conditions for referring to TSU_ADRH24 to TSU_ADRH31 and TSU_ADRL24 to TSU_ADRL31. The settings of this register are valid when the POSENU bit in TSU_FWSLC is set to 1. Bit Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 24. By setting multiple bits to 1, multiple conditions can be selected. POST243: The CAM entry table 24 is referred in port 0 reception. POST242: The CAM entry table 24 is referred in port 0 to 1 relay. POST241: The CAM entry table 24 is referred in port 1 reception. POST240: The CAM entry table 24 is referred in port 1 to 0 relay. 27 to 24 POST253 to All 0 POST250 R/W These bits set the conditions for referring to the CAM entry table 25. By setting multiple bits to 1, multiple conditions can be selected. POST253: The CAM entry table 25 is referred in port 0 reception. POST252: The CAM entry table 25 is referred in port 0 to 1 relay. POST251: The CAM entry table 25 is referred in port 1 reception. POST250: The CAM entry table 25 is referred in port 1 to 0 relay. 31 to 28 POST243 to All 0 POST240 Rev. 1.00 Dec. 27, 2005 Page 695 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 26. By setting multiple bits to 1, multiple conditions can be selected. POST263: The CAM entry table 26 is referred in port 0 reception. POST262: The CAM entry table 26 is referred in port 0 to 1 relay. POST261: The CAM entry table 26 is referred in port 1 reception. POST260: The CAM entry table 26 is referred in port 1 to 0 relay. 23 to 20 POST263 to All 0 POST260 19 to 16 POST273 to All 0 POST270 R/W These bits set the conditions for referring to the CAM entry table 27. By setting multiple bits to 1, multiple conditions can be selected. POST273: The CAM entry table 27 is referred in port 0 reception. POST272: The CAM entry table 27 is referred in port 0 to 1 relay. POST271: The CAM entry table 27 is referred in port 1 reception. POST270: The CAM entry table 27 is referred in port 1 to 0 relay. 15 to 12 POST283 to All 0 POST280 R/W These bits set the conditions for referring to the CAM entry table 28. By setting multiple bits to 1, multiple conditions can be selected. POST283: The CAM entry table 28 is referred in port 0 reception. POST282: The CAM entry table 28 is referred in port 0 to 1 relay. POST281: The CAM entry table 28 is referred in port 1 reception. POST280: The CAM entry table 28 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 696 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Bit 11 to 8 Bit Name Initial Value R/W R/W Description These bits set the conditions for referring to the CAM entry table 29. By setting multiple bits to 1, multiple conditions can be selected. POST293: The CAM entry table 29 is referred in port 0 reception. POST292: The CAM entry table 29 is referred in port 0 to 1 relay. POST291: The CAM entry table 29 is referred in port 1 reception. POST290: The CAM entry table 29 is referred in port 1 to 0 relay. POST293 to All 0 POST290 7 to 4 POST303 to All 0 POST300 R/W These bits set the conditions for referring to the CAM entry table 30. By setting multiple bits to 1, multiple conditions can be selected. POST303: The CAM entry table 30 is referred in port 0 reception. POST302: The CAM entry table 30 is referred in port 0 to 1 relay. POST301: The CAM entry table 30 is referred in port 1 reception. POST300: The CAM entry table 30 is referred in port 1 to 0 relay. 3 to 0 POST313 to All 0 POST310 R/W These bits set the conditions for referring to the CAM entry table 31. By setting multiple bits to 1, multiple conditions can be selected. POST313: The CAM entry table 31 is referred in port 0 reception. POST312: The CAM entry table 31 is referred in port 0 to 1 relay. POST311: The CAM entry table 31 is referred in port 1 reception. POST310: The CAM entry table 31 is referred in port 1 to 0 relay. Rev. 1.00 Dec. 27, 2005 Page 697 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.44 CAM Entry Table 0 to 31 H Registers (TSU_ADRH0 to TSU_ADRH31) TSU_ADRH0 to TSU_ADRH31 are entry tables referred by the CAM in reception and relay. This register sets the upper 32 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered. To refer to input signals on the CAMSEN0 and CAMSEN 1 pins, do not set the same MAC address set by this register to the entry tables of the external CAM. Bit Bit Name Initial Value R/W R/W Description MAC Address Bit These bits set the upper 32 bits of the MAC address. When the MAC address is 01-23-45-67-89-AB (displayed in hexadecimal), H01234567 is set to this register. 31 to 0 ADRHn31 to All 0 ADRHn0 (n: 0 to 31) Notes: Set the CAM entry table as follows: 1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0. 2. Set the upper 32 bits of the MAC address by TSU_ADRH0 to TSU_ADRH31. 3. Set the lower 16 bits of the MAC address by TSU_ADRL0 to TSU_ADRL31. Rev. 1.00 Dec. 27, 2005 Page 698 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.45 CAM Entry Table 0 to 31 L Registers (TSU_ADRL0 to TSU_ADRL31) TSU_ADRL0 to TSU_ADRL31 are entry tables referred by the CAM in reception and relay. This register sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered. To refer to input signals on the CAMSEN0 and CAMSEN 1 pins, do not set the same MAC address set by this register to the entry tables of the external CAM. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 ADRLn15 to All 0 ADRLn0 (n: 0 to 31) R/W MAC Address Bit These bits set the lower 16 bits of the MAC address. When the MAC address is 01-23-45-67-89-AB (displayed in hexadecimal), H000089AB is set to this register. 31 to 16 Notes: Set the CAM entry table as follows: 1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0. 2. Set the upper 32 bits of the MAC address by TSU_ADRH0 to TSU_ADRH31. 3. Set the lower 16 bits of the MAC address by TSU_ADRL0 to TSU_ADRL31. 18.3.46 Transmit Frame Counter Register (Port 0) (Normal Transmission Only) (TXNLCR0) TXNLCR0 is a 32-bit counter indicating the number of frames successfully transmitted in MAC0. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 0 Transmit Frame Counter Bit These bits indicate the number of frames successfully transmitted. 31 to 0 NTC031 to All 0 NTC000 Rev. 1.00 Dec. 27, 2005 Page 699 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.47 Transmit Frame Counter Register (Port 0) (Normal and Error Transmission) (TXALCR0) TXALCR0 is a 32-bit counter indicating the number of frames successfully transmitted and frames transmitted with error in MAC-0. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 0 Transmit Frame Counter Bit These bits indicate the number of frames successfully transmitted and frames transmitted with error. 31 to 0 TC031 to TC000 18.3.48 Receive Frame Counter Register (Port 0) (Normal Reception Only) (RXNLCR0) RXNLCR0 is a 32-bit counter indicating the number of frames successfully received in MAC-0. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 0 Receive Frame Counter Bit These bits indicate the number of frames successfully received. 31 to 0 NRC031 to All 0 NRC000 Rev. 1.00 Dec. 27, 2005 Page 700 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.49 Receive Frame Counter Register (Port 0) (Normal and Error Reception) (RXALCR0) RXALCR0 is a 32-bit counter indicating the number of frames successfully received and frames received with error in MAC-0. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 0 Receive Frame Counter Bit These bits indicate the number of frames successfully received and frames received with error. 31 to 0 RC031 to RC000 18.3.50 Relay Frame Counter Register (Port 1 to 0) (Normal Relay Only) (FWNLCR0) FWNLCR0 is a 32-bit counter indicating the number of frames successfully relayed in port 1 to 0 relay operations. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 1 to 0 Relay Frame Counter Bit These bits indicate the number of frames successfully relayed. 31 to 0 NFC031 to All 0 NFC000 Rev. 1.00 Dec. 27, 2005 Page 701 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.51 Relay Frame Counter Register (Port 1 to 0) (Normal and Error Relay) (FWALCR0) FWALCR0 is a 32-bit counter indicating the number of frames successfully relayed and frames relayed with error in port 1 to 0 relay operations. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 1 to 0 Relay Frame Counter Bit These bits indicate the number of frames successfully relayed and frames relayed with error. 31 to 0 FC031 to FC000 18.3.52 Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (TXNLCR1) TXNLCR1 is a 32-bit counter indicating the number of frames successfully transmitted in MAC1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 1 Transmit Frame Counter Bit These bits indicate the number of frames successfully transmitted. 31 to 0 NTC131 to All 0 NTC100 Rev. 1.00 Dec. 27, 2005 Page 702 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.53 Transmit Frame Counter Register (Port 1) (Normal and Error Transmission) (TXALCR1) TXALCR1 is a 32-bit counter indicating the number of frames successfully transmitted and frames transmitted with error in MAC-1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 1 Transmit Frame Counter Bit These bits indicate the number of frames successfully transmitted and frames transmitted with error. 31 to 0 TC131 to TC100 18.3.54 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1) RXNLCR1 is a 32-bit counter indicating the number of frames successfully received in MAC-1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 1 Receive Frame Counter Bit These bits indicate the number of frames successfully received. 31 to 0 NRC131 to All 0 NRC100 Rev. 1.00 Dec. 27, 2005 Page 703 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.55 Receive Frame Counter Register (Port 1) (Normal and Error Reception) (RXALCR1) RXALCR1 is a 32-bit counter indicating the number of frames successfully received and frames received with error in MAC-1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 1 Receive Frame Counter Bit These bits indicate the number of frames successfully received and frames received with error. 31 to 0 RC131 to RC100 18.3.56 Relay Frame Counter Register (Port 0 to 1) (Normal Relay Only) (FWNLCR1) FWNLCR1 is a 32-bit counter indicating the number of frames successfully relayed in port 0 to 1 relay operations. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value R/W R Description Port 0 to 1 Relay Frame Counter Bit These bits indicate the number of frames successfully relayed. 31 to 0 NFC131 to All 0 NFC100 Rev. 1.00 Dec. 27, 2005 Page 704 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.3.57 Relay Frame Counter Register (Port 0 to 1) (Normal and Error Relay) (FWALCR1) FWALCR1 is a 32-bit counter indicating the number of frames successfully relayed and frames relayed with error in port 0 to 1 relay operations. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Port 0 to 1 Relay Frame Counter Bit These bits indicate the number of frames successfully relayed and frames relayed with error. 31 to 0 FC131 to FC100 Rev. 1.00 Dec. 27, 2005 Page 705 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.4 Operation The following outlines the operations of the Ethernet controller (EtherC). Automatic Ethernet Frame Transfer Function by Hardware: Each MAC controller can transmit and receive independently using two ports of MAC controllers. Furthermore, relay between the two MAC controllers can be performed by hardware using the on-chip TSU of the EtherC. TSU selects one of the following processes depending on the MAC address of the destination of the Ethernet frame input to the MAC controller according to on the settings of the CAM and registers TSU_FWSL0/1, and TSU_FWSLC; 1) reception, 2) relay, 3) reception and relay, and 4) discard. This setting can be performed independently for each port at the receive and relay sides by means of registers TSU_TEN and TSU_POST1 to TSU_POST4. It also has a 6kbyte TSU FIFO for temporarily retaining the frames relayed. This TSU FIFO can vary capacity allotment with port 0 to 1 transfer and port 1 to 0 transfer using the TSU FIFO size select register (TSU_FCM). TSU FIFO Overflow Prevention Function: By supporting relay operations, the MAC controller needs to transmit relay frames other than transmit frames requested by the E-DMAC normally. Arbitration is carried out between these two frames. The procedure of arbitration is specified by registers TSU_PRISL0 and TSU_PRISL1. It has a function which relays frames of the TSU FIFO with priority when the using rate of the TSU FIFO exceeds the value set by registers TSU_PRISL0 and TSU_PRISL1, thus preventing frame losses by TSU FIFO overflow. QoS (IEEE802.1Q) Frame Transmit/Receive, Relay Function: QoS frames can be transmitted and received. At the using relay function, if the Ethernet device connected to one of the MAC controllers cannot transmit/receive QoS frames, this LSI can convert to the normal IEEE802.3 frames and relay it. Figure 18.2 shows the data path and outline of various settings. Rev. 1.00 Dec. 27, 2005 Page 706 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) EDMAC-0 CAMSEN pin EDMAC-1 EtherC TSU CAM reference CAM control CAM entry table (32 entries x 48 bits) External CAM I/F CAM reference Relay enable TSU_FWEN1 CAM reference (Reference setting: TSU_TEN and TSU_FWSLC) Determination of priority TSU_PRISL0 CAM reference TSU FIFO (1 to 0) TSU FIFO (0 to 1) Determination of priority TSU_PRISL1 Relay enable TSU_FWEN0 Transmission enable TE (ECMR0) = 1 Reception enable RE (ECMR0) = 1 Reception enable RE (ECMR1) = 1 Transmission enable TE (ECMR1) = 1 MAC-0 MAC-1 PHY-0 PHY-1 Figure 18.2 EtherC Data Path and Various Settings 18.4.1 Transmission The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines by PHY-LSI. Figure 18.3 shows the status change of the Ether-C transmitter. This operation is the same between ports 0 and 1. The priority of the process when transmit frame from E-DMAC and relay frame transmission collide can be set by the Transmit/Relay Priority Control Mode register (TSU_PRISL0/1). Rev. 1.00 Dec. 27, 2005 Page 707 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) TE set Idle FDPX Start of transmission (preamble transmission) Carrier non-detection Retransfer initiation Collision Carrier detection HDPX FDPX Transmission halted HDPX TE reset Carrier detection Carrier detection Reset Retransfer processing*1 Failure of 15 retransfer attempts or collision after 512-bit time Carrier non-detection Collision Carrier detection SFD transmission Error Collision*2 Error detection Error notification Error Data transmission Collision*2 Error Normal transmission CRC transmission Legend FDPX: Full-duplex HDPX: Half-duplex Notes: 1. Transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. Transmission is retried only when data of 512 bits or less (including the preamble and SFD)is transmitted. When a collision is detected during the transmission of data greater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried. Figure 18.3 EtherC Transmitter State Transitions 1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state. 2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble after a transmission delay equivalent to the frame interval time. If full-duplex transfer is Rev. 1.00 Dec. 27, 2005 Page 708 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the E-DMAC. 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting. 18.4.2 Reception The EtherC receiver separates the frame from the MII into preamble, SFD, data and CRC, and the fields from DA (destination address) to the CRC data are transferred to the receive E-DMAC. Figure 18.4 shows the state transitions of the EtherC receiver. These operations are the same for ports 0 and 1. In frame processing during reception, CAM evaluation can be referenced. (When using the CAM function, refer to section 18.4.4, CAM Function.) Rev. 1.00 Dec. 27, 2005 Page 709 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Illegal carrier detection RX-DV negation Idle RE set Preamble detection Start of frame reception Wait for SFD reception SFD reception Destination address reception Own destination address or broadcast or multicast or promiscuous Data reception End of reception CRC reception Reception halted RE reset Promiscuous and other station destination address Reset Error notification* Error detection Receivce error detection Receivce error detection Normal reception Legend SFD: Start frame delimiter Note: The error frame also transmits data to the buffer. Figure 18.4 EtherC Receiver State Transmissions 1. When the receive enable (RE) bit is set, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. Discards a frame with an invalid pattern. 3. In normal mode, if the destination address matches the receiver's own address, or if broadcast or multicast transmission or promiscuous mode is specified, the receiver starts data reception. 4. Following data reception from the MII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to memory. Reports an error status in the case of an abnormality. 5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode register, the receiver prepares to receive the next frame. Rev. 1.00 Dec. 27, 2005 Page 710 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.4.3 Relay EtherC has a function to relay frames received from the MII of either MAC-0 or MAC-1 to the other MAC. When relay is enabled, frames input from the MII are sent to both the TSU FIFO and receive E-DMAC, and determined independently whether to receive or not by the receive EDMAC and whether to relay or not by the TSU. (Refer to figure 18.2.) To execute relay, specify both MAC controllers as promiscuous mode, and the same MAC address in both MAC controllers (hereafter this MAC address is referred to as MAC address of this LSI). The setting of the transfer frame processing (relayed/discarded) is carried by the TSU_FWSL0 and TSU_FWSL1. Frames passing the TSU FIFO during relaying are sent to the PHY_LSI from MAC-1 in MAC-0 to MAC1 relay, from MAC-0 in MAC1 to MAC0 relay via the MII. At this time, collision with the relay frames from the E-DMAC may occur. The priority of the process when collision occurs can be set by TSU_PRISL0/1. For multicast frames and frames their destinations are other than this LSI, the CAM evaluation in frame relay processing can be referenced (for details on the CAM function, refer to section 18.4.4, CAM Function). Table 18.2 shows the settings of the relay frame processing (without CAM). Table 18.2 Transfer Frame Processing (Without CAM) Name Frame for this LSI TSU-FWSL FW40/1 = 0 FW40/1 = 1 Broadcast frame FW30/1 = 0 FW30/1 = 1 Multicast frame FW20/1 = 0 FW20/1 = 1 Frames to destinations other than this LSI FW10/1 = 0 FW10/1 = 1 Frame Processing Discarded Relayed Discarded Relayed Discarded Relayed Discarded Relayed 18.4.4 CAM Function Frames input to the MAC are grouped into the following four types; unicast for this LSI, broadcast, multicast, and unicast to other destinations. Of this, the MAC addresses of unicast for this LSI and broadcast are fixed, and determination is carried out only by register settings. Consequently, only multicast and unicast to other destinations determine whether to receive or not and whether to relay or not by using the CAM (unicast frames whose destination MAC addresses match this LSI are called unicast frames to this LSI, and those that do not are called unicast frames to other destinations). Rev. 1.00 Dec. 27, 2005 Page 711 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Furthermore, with the EtherC, the evaluation of receive and relay of unicast to other destinations and multicast frames by using CAM are performed by referencing the registered MAC addresses of the CAM entry table in the EtherC and the CAM logic connected externally via the CAMSEN0 and CAMSEN1 pins. By using this function, receive FIFO overflow can be prevented caused by accumulation of frame data not required for reception, and CPU processing for determining receive can be reduced. The POST table is composed of 4 bits, and each bit corresponds to port 0 reception, port 1 reception, port 0 to 1 relay, and port 1 to 0 relay. When the corresponding bit is set to 1, the CAM evaluation results are used for determining receive and relay. In other words, when the corresponding bit of the POST table is cleared to 0, receive and relay evaluation will be the same as when CAM is not used shown in table 18.2. The difference between the on-chip CAM entry table and externally connected CAM logic lies in how the POST table is set. In the internal CAM entry table, there are 32 POST tables (same as the number of entries) and the POST table can be set for each entry. The internal CAM entry table has 32 entries and 32 POST tables, and the POST table can be specified in each entry. The external connection CAM logic configuration is based on pins because POST tables (total of 2) are allocated to the CAMSEN0 and CAMSEN1 pins. When On-Chip CAM Entry Table is Used: The on-chip CAM has entry tables which can register the MAC address of 32 entries, the details of which can be set by TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31. The setting to enable/disable referencing of the on-chip CAM entry table is carried out by the CAM entry table enable setting register which sets whether to perform CAM evaluation or not, and the CAM entry table POST setting register for setting whether to use the CAM determination results for determining receive or relay. When on-chip CAM entry table referencing during receive is enabled, the destination address in the frame and MAC address registered in the CAM entry table are compared, and it is determined whether to transfer the frames input to the MAC to E-DMAC (have E-DMAC receive the frames) or discard the frames. When relaying and CAM entry table referencing during relay are both enabled, whether to transfer or discard multicast frames and frames for destinations other than this LSI can be determined by comparing the destination address in the frame and MAC address registered in the CAM entry table. Table 18.3 shows the processing method of frames (receive or discard) in MAC0 to E-DMAC0 and MAC1 to E-DMAC1 reception, while table 18.4 shows the processing for frames in MAC0 to MAC1 and MAC1 to MAC0 relay (relay or discard). Rev. 1.00 Dec. 27, 2005 Page 712 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Table 18.3 Reception Frame Process Normal Mode CAM Entry Table Referencing Results Frame CAM hit (when addresses match) Frame to this LSI Broadcast frame Multicast frame Frames to destinations other than this LSI CAM mishit (when addresses do not match) Frames to this LSI Broadcast frame Multicast frame Frames to destinations other than this LSI MCT = 0 Discarded Discarded Discarded Received Received MCT = 1 Promiscuous Mode MCT = 0 Discarded Discarded Discarded Discarded Received MCT = 1 Received Received Received Discarded Discarded Received Received Received Received Discarded [Legend] MCT (Bit 13 in ECMR): Multicast receive mode (0: Receive when CAM mishit/ 1: Receive when CAM hit) Table 18.4 Relay Frame Process (With CAM) Frame Multicast frame Relay Function Setting Register Bit FW40/1 = 0 FW40/1 = 1 Frames to destinations other than this LSI FW40/1 = 0 FW40/1 = 1 CAM Hit Relayed Discarded Relayed Discarded CAM Mishit Discarded Relayed Discarded Relayed Note: CAM can be referenced only for multicast frames and frames to destinations other than this LSI. The processing of frames to this LSI and broadcast frames conforms to the values of the relay function setting register regardless of CAM reference. When External CAM Logic is Used: In addition to the on-chip CAM entry table, use of the CAMSEN0 and CAMSEN1 pins allows referencing of evaluation results of the external CAM logic connected externally to this LSI for frame processing evaluation. This function externally connects the CAM logic for comparing the destination address in receive frames, and receives the results of comparing destination addresses corresponding to the signals (RXD3 to RXD0) input from the MII to determine whether to receive or discard the corresponding frame. Figure 18.5 Rev. 1.00 Dec. 27, 2005 Page 713 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) shows the connection example of the external CAM logic while figure 18.6 shows the timing conditions of the external CAM signal. MII (RX-DV, RXD3 to RXD0) This LSI EtherC PHY-LSI CAMSEN0 or CAMSEN1 pin External memory External CAM logic Descriptor Figure 18.5 Example of External CAM Connection The setting on whether to enable or disable the referencing of external CAM logic evaluation results by the CAMSEN0 and CAMSEN1 pins is carried out by the transfer function setting register (common) (TSU_FWSLC). When referencing of the CAMSEN0 and CAMSEN1 pins is enabled during receive, it is determined whether to send or discard the frames input from to MAC0/1 to E-DMAC0/1 (have E-DMAC receive the frames) according to the value of the CAMSEN0 or CAMSEN1 pin. When relaying and CAMSEN0/1 pin referencing are enabled at the same time, the transfer or discard of multicast frames and frames to destinations other than this LSI can be determined by the value of the CAMSEN0 and CAMSEN1 pins. Table 18.5 shows the processing method (receive or discard) for frames in MAC0 to E-DMAC0 or MAC1 to E-DMAC1 reception, while Table 18.6 shows the processing method (receive or discard) for frames in MAC0 to MAC1 or MAC1 to MAC relay. The external CAM logic is memorized with MAC addresses different from the CAM entry table in this LSI. When the MAC address received from the PHY matches the destination address memorized in the external CAM logic, the CAMSEN0 or CAMSEN1 pin is asserted*. EtherC receives or discards the frames when CAMSEN0/1 was asserted according to the settings in table 18.5. Figure 18.6 shows the valid range of CAMSEN0/1 assertion for the corresponding receive frames. Rev. 1.00 Dec. 27, 2005 Page 714 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) With EtherC, before storage of receive frames in the FIFO of E-DMAC/TSU is started, there is a need to determine receive frame processing. The time limit for determining this processing is within 52 clocks from RX_DV assertion. Note: * Do not memorize MAC addresses overlapping with the internal CAM entry table of this LSI during external CAM logic. If the CAMSEN0 or CAMSEN1 pin is asserted at the same time as CAM hit occurs for the internal CAM entry table, evaluation may not performed correctly. Table 18.5 Receive Frame Process (When External CAM Logic is Used) CAMSEN0 or CAMSEN1 Pin Assertion (when addresses match) Normal Mode Frame Frame to this LSI Broadcast frame Multicast frame Frames to destinations other than this LSI Negation Frames to this LSI MCT = 0 Discarded Discarded Discarded Received Received MCT = 1 Promiscuous Mode MCT = 0 Discarded Discarded Discarded Discarded Received MCT = 1 Received Received Received Discarded Discarded Received Received Received Received Discarded (when addresses do Broadcast frame not match) Multicast frame Frames to destinations other than this LSI [Legend] MCT (Bit 13 in ECMR): Multicast receive mode (0: Received when CAM mishit/ 1: Received when CAM hit) Rev. 1.00 Dec. 27, 2005 Page 715 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Table 18.6 Relay Frame Process (When External CAM Logic is Used) Relay Function Setting Register bit FW40/1 = 0 FW40/1 = 1 Frames to destinations other than this LSI FW40/1 = 0 FW40/1 = 1 CAMSEN0 or CAMSEN1 Pin Assertion Relayed Discarded Relayed Discarded CAMSEN0 or CAMSEN1 Pin Negation Discarded Relayed Discarded Relayed Frame Multicast frame Note: CAM can be referenced only for multicast frames and frames to destinations other than this LSI. The processing of frames to this LSI and broadcast frames conforms to the values of the relay function setting register regardless of CAM reference. CAMSEN signal valid range RX-CLK RX-DV RXD3 to RXD0 CAMSEN* Preamble SFD Destination address 1 2 3 7 8 9 10 11 12 13 50 51 52 53 Assertion above 1 clock Note: * Outside the valid range of the CAMSEN signal, always set the CAMSEN signal to low. Figure 18.6 External CAM Signal Timing Rev. 1.00 Dec. 27, 2005 Page 716 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.4.5 MII Frame Timing Each MII Frame timing is shown in figure 18.7. TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL Preamble SFD Data CRC Figure 18.7 (1) MII Frame Transmit Timing (Normal Transmission) TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL Preamble JAM Figure 18.7 (2) MII Frame Transmit Timing (Collision) Rev. 1.00 Dec. 27, 2005 Page 717 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL Preamble SFD Data Figure 18.7 (3) MII Frame Transmit Timing (Transmit Error) RX-CLK RX-DV RXD3 to RXD0 RX-ER Preamble SFD Data CRC Figure 18.7 (4) MII Frame Receive Timing (Normal Reception) RX-CLK RX-DV RXD3 to RXD0 RX-ER Preamble SFD Data XXXX Figure 18.7 (5) MII Frame Receive Timing (Reception Error (1)) RX-CLK RX-DV RXD3 to RXD0 RX-ER XXXX 1110 XXXX Figure 18.7 (6) MII Fame Receive Timing (Reception Error (2)) Rev. 1.00 Dec. 27, 2005 Page 718 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.4.6 Accessing MII Registers MII registers in the PHY-LSI are accessed via this LSI's PHY interface register (PIR). Connection is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u. MII Management Frame Format: The format of an MII management frame is shown in figure 18.8. To access an MII register, a management frame is implemented by the program in accordance with the procedures shown in MII Register Access Procedure. Access Type Item Number of bits Read Write [Legend] PRE: ST: OP: PHYAD: PRE 32 1..1 1..1 ST 2 01 01 OP 2 10 01 MII Management Frame PHYAD 5 00001 00001 REGAD 5 RRRRR RRRRR TA 2 Z0 10 DATA 16 D..D D..D X IDLE 32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY-LSI address. REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY-LSI register address. TA: Time for switching data transmission source on MII interface (a) Write: 10 written (b) Read: Bus release (notation: Z0) performed DATA: 16-bit data. Sequential write or read from MSB (a) Write: 16-bit data write (b) Read: 16-bit data read IDLE: Wait time until next MII management format input (a) Write: Independent bus release (notation: X) performed (b) Read: Bus already released in TA; control unnecessary Figure 18.8 MII Management Frame Format Rev. 1.00 Dec. 27, 2005 Page 719 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) MII Register Access Procedure: The program accesses MII registers via the PHY interface register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figure 18.9 shows the MII register access timing. The timing will differ depending on the PHY-LSI type. (1) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 MDC MDO (2) Write to PHY interface register MMD = 1 MDO = write data MDC = 1 (1) (2) (3) 1-bit data write timing relationship (3) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 Figure 18.9 (1) 1-Bit Data Write Flowchart Rev. 1.00 Dec. 27, 2005 Page 720 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (2) Write to PHY interface register (1) (2) MMD = 0 MDC = 1 (3) Bus release timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 18.9 (2) Bus Release Flowchart (TA in Read in Figure 18.8) (1) Write to PHY interface register MMD = 0 MDC = 1 MDC MDI (2) Read from PHY interface register MMD = 0 MMC = 1 MDI is read data (1) (2) (3) 1-bit data read timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 18.9 (3) 1-Bit Data Read Flowchart Rev. 1.00 Dec. 27, 2005 Page 721 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (1) Independent bus release timing relationship Figure 18.9 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 18.8) 18.4.7 Magic Packet Detection The EtherC has a Magic Packet detection function. This function provides a Wake-On-LAN (WOL) facility that activates various peripheral devices connected to a LAN from the host device or other source. This makes it possible to construct a system in which a peripheral device receives a Magic Packet sent from the host device or other source, and activates itself. When the Magic Packet is detected, data is stored in the FIFO of the E-DMAC by the broadcast packet that has received data previously and the EtherC is notified of the receiving status. To return to normal operation from the interrupt processing, initialize the EtherC and E-DMAC by using ARST bit in the software reset register (ARSTR). With a Magic Packet, reception is performed regardless of the destination address. As a result, this function is valid, and the WOL pin enabled, only in the case of a match with the destination address specified by the format in the Magic Packet. Further information on Magic Packets can be found in the technical documentation published by AMD Corporation. The procedure for using the WOL function with this LSI is as follows. 1. Disable interrupt source output by means of the various interrupt enable/mask registers. 2. Set the Magic Packet detection enable bit (MPDE) in the EtherC mode register (ECMR). 3. Set the Magic Packet detection interrupt enable bit (MPDIP) in the EtherC interrupt enable register (ECSIPR) to the enable setting. 4. If necessary, set the CPU operating mode to sleep mode or set peripheral modules to module standby mode. 5. When a Magic Packet is detected, an interrupt is sent to the CPU. The WOL pin notifies peripheral LSIs that the Magic Packet has been detected. Rev. 1.00 Dec. 27, 2005 Page 722 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.4.8 Operation by IPG Setting The EtherC has a function to change the non-transmission period IPG (Inter Packet Gap) between transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission efficiency can be raised and lowered from the standard value. IPG settings are prescribed in IEEE802.3 standards. When changing settings, adequately check that the respective devices can operate smoothly on the same network. Case A (short IPG) [1] [2] [3] [4] [5] ...... Packet Case B (long IPG) IPG* [1] [2] [3] [4] ...... Note: * IPG may be longer than the set value, depending on the state of the line and the system bus. Figure 18.10 Changing IPG and Transmission Efficiency 18.4.9 Direction for IEEE802.1Q Qtag The EtherC supports IEEE802.1Q frame processing. It can add or delete Qtags to or from frames processed in relay. This function can also transmit and receive QoS frames. During relaying, if the Ethernet device connected to one MAC controller cannot transmit or receive QoS frames, it can be converted to the normal IEEE802.3 frames and relayed in this LSI. Whether to add or delete Qtags is determined by the added Qtag value set register (TSU_ADQT0/1). Figure 18.11 shows an outline of the Qtag add function while figure 18.12 shows the comparison between the normal Ethernet frames and IEEE802.1Q frames (with Qtag). For details on setting Qtag, refer to the specifications on Qtag control specified in IEEE802.1Q. Rev. 1.00 Dec. 27, 2005 Page 723 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) This LSI EtherC TSU Frame conversion mechanism Qtag deleting Qtag adding 802.1Q supporting network MAC-0 802.1Q conforming frame (With Qtag) MAC-1 802.1Q unsupporting network Normal frame (Without Qtag) Figure 18.11 Diagram of Qtag Additional Functions Normal Ethernet frame 7 oct PR (Without Qtag) 1 oct SFD 6 oct 6 oct 2 oct 46 to 1500 oct 4 oct FCS DA SA L/T Data 802.1Q conforming frame 7 oct PR (With Qtag) 6 oct SA 1oct SFD 6 oct 4 oct Qtag 2 oct L/T 42 to 1500 oct Data 4 oct FCS DA 8 bit 8 bit 3 bit 1 bit CFI 12 bit H '81 H'00 PRT VID Extension code Legend: (Fixed) PR: PReamble SFD: Start Frame Delimiter DA: Destination Address SA: Source Address L/T: Length or Type FCS: Frame Check Sequence Qtag setting (TSU_ADQT0/1) PRT: Priority level setting CFI: Fixed at 0 VID: V-LAN ID setting Figure 18.12 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag) Rev. 1.00 Dec. 27, 2005 Page 724 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) 18.5 Connection to LSI Figure 18.13 shows the example of connection to a DP83847 (National Semiconductor Corporation). MII (Media Independent Interface) This LSI TX-ER ETXD3 ETXD2 ETXD1 ETXD0 TX-EN TX-CLK MDC MDIO ERXD3 ERXD2 ERXD1 ERXD0 RX-CLK CRS COL RX-DV RX-ER DP83847 TX_ER TXD[3] TXD[2] TXD[1] TXD[0] TX_EN TX_CLK MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER Figure 18.13 Example of Connection to DP83847 Rev. 1.00 Dec. 27, 2005 Page 725 of 932 REJ09B0269-0100 Section 18 Ethernet Controller (EtherC) Rev. 1.00 Dec. 27, 2005 Page 726 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) This LSI has an on-chip two-channel direct memory access controller (E-DMAC0/1) directly connected to the Ethernet controller (EtherC). By using the DMAC contained in the E-DMAC, the E-DMAC transfers transmit/receive data between the transmit/receive FIFO in the E-DMAC and a user-specified data storage destination (buffer) by DMA transfer. At DMA transfer, information referenced by the E-DMAC is referred to as a transmit/receive descriptor, and the user places this descriptor in memory. This function reduces the load on the CPU and enables efficient data transfer control to be achieved. The E-DMAC0 and E-DMAC1 control the data transmission/reception from the MAC-0 and MAC-1 of EtherC respectively. (Hereafter the channel controlled by the E-DMAC0 is channel 0. The channel controlled by the E-DMAC1 is channel 1.) Figure 19.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive buffers in memory. 19.1 Features The E-DMAC has the following features: * * * * Contains two-channel independent transmit/receive DMAC The load on the CPU is reduced by means of a descriptor management system Transmit/receive frame status information is indicated in descriptors Achieves efficient system bus utilization through the use of DMA block transfer (16-byte units) * Supports single-frame/single-descriptor operation and single-frame/multi-frame (multi-buffer) operation Note: The E-DMAC cannot access peripheral modules. EDMAS20B_000020020900 Rev. 1.00 Dec. 27, 2005 Page 727 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) This LSI Transmit buffer 1 Transmit descriptor 1 Internal bus E-DMAC1 Descriptor Information Internal bus interface Transmit DMAC Transmit FIFO Receive buffer 1 Receive descriptor 1 External bus interface E-DMAC0 Descriptor Information Receive DMAC Receive FIFO Transmit buffer 0 Transmit descriptor 0 Internal bus interface Receive buffer 0 Receive descriptor 0 Transmit FIFO EtherC Descriptor Information Transmit DMAC Receive FIFO Descriptor Information Receive DMAC External memory Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers 19.2 Register Descriptions The E-DMAC has the following registers. The number at the end of the register abbreviation represents the number of corresponding E-DMAC (E-DMAC0 or E-DMAC1). In this section, some numbers are not mentioned. For addresses and access sizes of these registers, see section 23, List of Registers. Channel 0: * * * * * * * * E-DMAC mode register (EDMR0) E-DMAC transmit request register (EDTRR0) E-DMAC receive request register (EDRRR0) Transmit descriptor list address register (TDLAR0) Receive descriptor list address register (RDLAR0) EtherC/E-DMAC status register (EESR0) EtherC/E-DMAC status interrupt permission register (EESIPR0) Transmit/receive status copy enable register (TRSCER0) Rev. 1.00 Dec. 27, 2005 Page 728 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) * * * * * * * * * * * Receive missed-frame counter register (RMFCR0) Transmit FIFO threshold register (TFTR0) FIFO depth register (FDR0) Receiving method control register (RMCR0) E-DMAC operation control register (EDOCR0) Receive buffer write address register (RBWAR0) Receive descriptor fetch address register (RDFAR0) Transmit buffer read address register (TBRAR0) Transmit descriptor fetch address register (TDFAR0) Overflow alert FIFO threshold register (FCFTR0) Transmit interrupt register (TRIMD0) Channel 1: * * * * * * * * * * * * * * * * * * * E-DMAC mode register (EDMR1) E-DMAC transmit request register (EDTRR1) E-DMAC receive request register (EDRRR1) Transmit descriptor list address register (TDLAR1) Receive descriptor list address register (RDLAR1) EtherC/E-DMAC status register (EESR1) EtherC/E-DMAC status interrupt permission register (EESIPR1) Transmit/receive status copy enable register (TRSCER1) Receive missed-frame counter register (RMFCR1) Transmit FIFO threshold register (TFTR1) FIFO depth register (FDR1) Receiving method control register (RMCR1) E-DMAC operation control register (EDOCR1) Receive buffer write address register (RBWAR1) Receive descriptor fetch address register (RDFAR1) Transmit buffer read address register (TBRAR1) Transmit descriptor fetch address register (TDFAR1) Overflow alert FIFO threshold register (FCFTR1) Transmit interrupt register (TRIMD1) Rev. 1.00 Dec. 27, 2005 Page 729 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.1 E-DMAC Mode Register (EDMR) EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and transmit/receive descriptor length. This register is to be set before the TR bit in EDTRR or the RR bit in EDRRR is set to 1. If a software reset is executed with this register during data transmission, abnormal data may be transmitted on the line. Execute a software reset with this register before specifying transmit/receive descriptor length and modifying the settings of TDLAR, RDLAR, and so forth, the setting of ECMR (EtherC mode register), and the settings of registers related to E-DMAC and EtherC operation. The time required for completion of EtherC and E-DMAC initialization from a software reset with this register is 64 cycles of the internal bus clock B. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock B has elapsed. Bit 31 to 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 DL1 DL0 0 0 R/W R/W Descriptor Length These bits specify the descriptor length. (See section 19.3.1, Descriptors and Descriptor List.) 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: Reserved (setting prohibited) 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 730 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 0 Bit Name SWR Initial Value 0 R/W R/W Description Software Reset By writing 1 to this bit, the registers of the E-DMAC other than TDLAR, RDLAR, and RMFCR and the registers of EtherC other than TSU-related registers can be initialized. (The registers whose names start with TSU_ are not initialized.) The SWR bit in EDMR0 initializes the EDMAC0 and MAC-0 registers in the EtherC. The SWR bit in EDMR1 initializes EDMAC1 and MAC-1 registers in the EtherC. When transfer operation is enabled by specifying the relay enable register (Port 0 to 1) (TSU_FWEN0) and the relay enable register (Port 1 to 0) (TSU_FWEN1) in the EtherC, software reset should not be performed by using this bit. While a software reset is issued (64 cycles of the internal bus clock B), accesses to the all Ethernet-related registers are prohibited. Software reset period (example): When B = 100 MHz: 0.64 S When B = 66 MHz: 0.97 S When B = 50 MHz: 1.28 S When B = 33 MHz: 1.94 S This bit is always read as 0. 1: EtherC and E-DMAC are reset (when writing) 19.2.2 E-DMAC Transmit Request Register (EDTRR) EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After writing 1 to the TR bit in this register, the E-DMAC reads the transmit descriptor at the address specified by TDLAR. If the TACT bit of this descriptor is set to 1 (valid), transmit DMA transfer by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is completed, the E-DMAC reads the next transmit descriptor. If the TACT bit of that descriptor is set to 1 (valid), the E-DMAC continues transmit DMA operation. If the TACT bit of a transmit descriptor is cleared to 0 (invalid), the E-DMAC clears the TR bit and stops transmit DMAC operation. For details of writing to the TR bit, see section 19.4.1, Using of EDTRR and EDRRR. Rev. 1.00 Dec. 27, 2005 Page 731 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TR 0 R/W Transmit Request 0: Transmission-halted state. Writing 0 does not stop transmission. Termination of transmission is controlled by the TACT bit of the transmit descriptor. 1: Transmit DMA operation being performed by the EDMAC. After writing 1 to this bit, the E-DMAC starts reading a transmit descriptor. 19.2.3 E-DMAC Receive Request Register (EDRRR) EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address specified by RDLAR. If the RACT bit of this descriptor is set to 1 (valid), and the receive FIFO holds a receive frame, the E-DMAC starts receive DMA transfer. When DMA transfer based on the first receive descriptor is completed, the E-DMAC reads the next receive descriptor. If the RACT bit of that descriptor is set to 1 (valid), the E-DMAC continues receive DMA operation. However, if the receive FIFO holds no receive data, the E-DMAC places receive DMA operation in the standby state. If the RACT bit of the receive descriptor is cleared to 0 (invalid), the EDMAC clears the RR bit and stops receive DMAC operation. For details of writing to the RR bit, see section 19.4.1, Using of EDTRR and EDRRR. Rev. 1.00 Dec. 27, 2005 Page 732 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RR 0 R/W Receive Request 0: The receive function is disabled* 1: A receive descriptor is read, and the E-DMAC is ready to receive Note: * If the receive function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC can not operate successfully. In this case, to make the E-DMAC reception enabled again, execute a software reset by the SWR bit in EDMR0 (EDMR1). To make the E-DMAC reception disabled without executing a software reset, specify the RE bit in ECMR0 (ECMR1). Next, after the E_DMAC has completed the reception and write-back to the receive descriptor has been confirmed, disable the receive function of this register. 19.2.4 Transmit Descriptor List Address Register (TDLAR) TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during transmission. Modifications to this register should only be made while transmission is disabled by the TR bit (= 0) in the E-DMAC transmit request register (EDTRR). Bit 31 to 0 Bit Name TDLA31 to TDLA0 Initial Value All 0 R/W R/W Description Transmit Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: TDLA3 and TDLA0 = 0000 32-byte boundary: TDLA4 and TDLA0 = 00000 64-byte boundary: TDLA5 and TDLA0 = 000000 Rev. 1.00 Dec. 27, 2005 Page 733 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.5 Receive Descriptor List Address Register (RDLAR) RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during reception. Modifications to this register should only be made while reception is disabled by the RR bit (= 0) in the E-DMAC Receive Request Register (EDRRR). Bit 31 to 0 Bit Name RDLA31 to RDLA0 Initial Value All 0 R/W R/W Description Receive Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: RDLA3 and RDLA0 = 0000 32-byte boundary: RDLA4 and RDLA0 = 00000 64-byte boundary: RDLA5 and RDLA0 = 000000 19.2.6 EtherC/E-DMAC Status Register (EESR) EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the EtherC. The information in this register is reported in the form of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission register (EESIPR). The interrupts generated by this register are EINT0 for channel 0 and EINT1 for channel 1. For interrupt priorities, see section 8, Interrupt Controller (INTC) and section 8.3.5, Interrupt Exception Handling and Priority. The EINT2 is an interrupt generated by the TSU_FNSR in the EtherC. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 734 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30 Bit Name TWB Initial Value 0 R/W R/W Description Write-Back Complete Indicates that write-back from the E-DMAC to the corresponding descriptor has completed. This operation is enabled when the TIS bit in TRIMD is set to 1. 0: Write-back has not completed, or no transmission directive 1: Write-back has completed 29 to 27 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 TABT 0 R/W Transmit Abort Detection Indicates that the EtherC aborts transmitting a frame because of failures during transmitting the frame. 0: Frame transmission has not been aborted or no transmit directive 1: Frame transmit has been aborted 25 RABT 0 R/W Receive Abort Detection Indicates that the EtherC aborts receiving a frame because of failures during receiving the frame. 0: Frame reception has not been aborted or no receive directive 1: Frame receive has been aborted 24 RFCOF 0 R/W Receive Frame Counter Overflow Indicates that the receive FIFO frame counter has overflowed. 0: Receive frame counter has not overflowed 1: Receive frame counter overflows Rev. 1.00 Dec. 27, 2005 Page 735 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 23 Bit Name ADE Initial Value 0 R/W R/W Description Address Error Indicates that the memory address that the E-DMAC tried to transfer is found illegal. 0: Illegal memory address not detected (normal operation) 1: Illegal memory address detected Note: When an address error is detected, the E-DMAC halts transmitting/receiving. To resume the operation, execute a software reset with the SWR bit in EDMR. 22 ECI 0 R EtherC Status Register Interrupt Source This bit is a read-only bit. When the source of an ECSR interrupt in the EtherC is cleared, this bit is also cleared. 0: EtherC status interrupt source has not been detected 1: EtherC status interrupt source has been detected 21 TC 0 R/W Frame Transmit Complete Indicates that all the data specified by the transmit descriptor has been transmitted from the EtherC. This bit is set to 1, assuming the completion of transmission, when transmission of one frame is completed in single-frame/single-descriptor operation or when the last data of a frame has been transmitted and the transmit descriptor valid bit (TACT) of the next descriptor is not set in for the processing of multi-buffer frame based on single-frame/multidescriptor operation. After frame transmission, the EDMAC writes the transmission status back to the relevant descriptor. 0: Transfer not complete, or no transfer directive 1: Transfer complete Rev. 1.00 Dec. 27, 2005 Page 736 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 20 Bit Name TDE Initial Value 0 R/W R/W Description Transmit Descriptor Empty Indicates that the transmit descriptor valid bit (TACT) of a transmit descriptor read by the E-DMAC is not set if the previous descriptor does not represent the end of a frame for the processing of multi-buffer frame based on the single-frame/multi-descriptor. As a result, an incomplete frame may be transmitted. 0: Transmit descriptor active bit TACT = 1 detected 1: Transmit descriptor active bit TACT = 0 detected When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate transmission. In this case, the address that is stored in the transmit descriptor list address register (TDLAR) is transmitted first. 19 TFUF 0 R/W Transmit FIFO Underflow Indicates that underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. 0: Underflow has not occurred 1: Underflow has occurred 18 FR 0 R/W Frame Reception Indicates that a frame has been received and the receive descriptor has been updated. This bit is set to 1 each time a frame is received. 0: Frame not received 1: Frame received Rev. 1.00 Dec. 27, 2005 Page 737 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 17 Bit Name RDE Initial Value 0 R/W R/W Description Receive Descriptor Empty Indicates that the RACT bit of a receive descriptor read by the E-DMAC for receive DMA is cleared to 0 (invalid). When receive descriptor empty (RDE = 1) occurs, reception can be resumed by setting the RACT bit (cleared to 0) of the receive descriptor to 1 and writing 1 to the RR bit in EDRRR. 0: Receive descriptor active bit RACT = 1 detected 1: Receive descriptor active bit RACT = 0 detected 16 RFOF 0 R/W Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CND 0 R/W Carrier Not Detect Indicates the carrier detection status during preamble transmission. 0: A carrier is detected when transmission starts 1: A carrier is not detected 10 DLC 0 R/W Detect Loss of Carrier Indicates that loss of the carrier has been detected during frame transmission. 0: Loss of carrier not detected 1: Loss of carrier detected 9 CD 0 R/W Delayed Collision Detect Indicates that a delayed collision has been detected during frame transmission. 0: Delayed collision not detected 1: Delayed collision detected Rev. 1.00 Dec. 27, 2005 Page 738 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 8 Bit Name TRO Initial Value 0 R/W R/W Description Transmit Retry Over Indicates that a retry-over condition has occurred during frame transmission. Total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the EtherC transmission starts. 0: Transmit retry-over condition not detected 1: Transmit retry-over condition detected 7 RMAF 0 R/W Receive Multicast Address Frame 0: Multicast address frame has not been received 1: Multicast address frame has been received 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRF 0 R/W Receive Residual-Bit Frame 0: Residual-bit frame has not been received 1: Residual-bit frame has been received 3 RTLF 0 R/W Receive Too-Long Frame Indicates that the frame more than the number of receive frame length upper limit set by RFLR has been received. 0: Too-long frame has not been received 1: Too-long frame has been received 2 RTSF 0 R/W Receive Too-Short Frame Indicates that a frame of fewer than 64 bytes has been received. 0: Too-short frame has not been received 1: Too-short frame has been received 1 PRE 0 R/W PHY-LSI Receive Error 0: PHY-LSI receive error not detected 1: PHY-LSI receive error detected 0 CERF 0 R/W CRC Error on Received Frame 0: CRC error not detected 1: CRC error detected Rev. 1.00 Dec. 27, 2005 Page 739 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 TWBIP 0 R/W Write-Back Complete Interrupt Enable 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled 29 to 27 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 TABTIP 0 R/W Transmit Abort Detection Interrupt Enable 0: Transmit abort detection interrupt is disabled 1: Transmit abort detection interrupt is enabled 25 RABTIP 0 R/W Receive Abort Detection Interrupt Enable 0: Receive abort detection interrupt is disabled 1: Receive abort detection interrupt is enabled 24 RFCOFIP 0 R/W Receive Frame Counter Overflow Interrupt Enable 0: Receive frame counter overflow interrupt is disabled 1: Receive frame counter overflow interrupt is enabled 23 ADEIP 0 R/W Address Error Interrupt Enable 0: Address error interrupt is disabled 1: Address error interrupt is enabled 22 ECIIP 0 R/W EtherC Status Register Interrupt Enable 0: EtherC status interrupt is disabled 1: EtherC status interrupt is enabled 21 TCIP 0 R/W Frame Transmit Complete Interrupt Enable 0: Frame transmit complete interrupt is disabled 1: Frame transmit complete interrupt is enabled Rev. 1.00 Dec. 27, 2005 Page 740 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 20 Bit Name TDEIP Initial Value 0 R/W R/W Description Transmit Descriptor Empty Interrupt Enable 0: Transmit descriptor empty interrupt is disabled 1: Transmit descriptor empty interrupt is enabled 19 TFUFIP 0 R/W Transmit FIFO Underflow Interrupt Enable 0: Underflow interrupt is disabled 1: Underflow interrupt is enabled 18 FRIP 0 R/W Frame Received Interrupt Enable 0: Frame received interrupt is disabled 1: Frame received interrupt is enabled 17 RDEIP 0 R/W Receive Descriptor Empty Interrupt Enable 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled 16 RFOFIP 0 R/W Receive FIFO Overflow Interrupt Enable 0: Receive FIFO overflow interrupt is disabled 1: Receive FIFO overflow interrupt is enabled 15 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CNDIP 0 R/W Carrier Not Detect Interrupt Enable 0: Carrier not detect interrupt is disabled 1: Carrier not detect interrupt is enabled 10 DLCIP 0 R/W Detect Loss of Carrier Interrupt Enable 0: Detect loss of carrier interrupt is disabled 1: Detect loss of carrier interrupt is enabled 9 CDIP 0 R/W Delayed Collision Detect Interrupt Enable 0: Delayed collision detect interrupt is disabled 1: Delayed collision detect interrupt is enabled 8 TROIP 0 R/W Transmit Retry Over Interrupt Enable 0: Transmit retry over interrupt is disabled 1: Transmit retry over interrupt is enabled Rev. 1.00 Dec. 27, 2005 Page 741 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 7 Bit Name RMAFIP Initial Value 0 R/W R/W Description Receive Multicast Address Frame Interrupt Enable 0: Receive multicast address frame interrupt is disabled 1: Receive multicast address frame interrupt is enabled 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRFIP 0 R/W Receive Residual-Bit Frame Interrupt Enable 0: Receive residual-bit frame interrupt is disabled 1: Receive residual-bit frame interrupt is enabled 3 RTLFIP 0 R/W Receive Too-Long Frame Interrupt Enable 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled 2 RTSFIP 0 R/W Receive Too-Short Frame Interrupt Enable 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled 1 PREIP 0 R/W PHY-LSI Receive Error Interrupt Enable 0: PHY-LSI receive error interrupt is disabled 1: PHY-LSI receive error interrupt is enabled 0 CERFIP 0 R/W CRC Error on Received Frame 0: CRC error on received frame interrupt is disabled 1: CRC error on received frame interrupt is enabled Rev. 1.00 Dec. 27, 2005 Page 742 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER indicates whether multicast address frame receive status information reported by bit 7 in EESR is reflected in the RFE bit in the corresponding descriptor (for details of descriptor descriptions, see section 19.3.1, Descriptors and Descriptor List). The RMAFCE bit in this register corresponds to bit 7 in EESR. When the RMAFCE bit is cleared to 0, the receive status (bit 7 in EESR) is reflected in the RFE bit in the receive descriptor. When this bit is set to 1, the status is not reflected in the descriptor even if the corresponding source occurs. The RMAFCE bit is cleared to 0 after a power-on reset and manual reset. Bit 31 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 RMAFCE 0 R/W RMAF Bit Copy Directive 0: Reflects the RMAF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 743 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.9 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded. The number of frames discarded at this time is counted. When the value in this register reaches HFFFF, counting-up is halted. When this register is read, the counter value is cleared to 0. Write operations to this register have no effect. Bit 31 to 16 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MFC15 to MFC0 All 0 R Missed-Frame Counter Indicate the number of frames that are discarded and not transferred to the receive buffer during reception. Rev. 1.00 Dec. 27, 2005 Page 744 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.10 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting this register, do so in the transmission-halt state. Rev. 1.00 Dec. 27, 2005 Page 745 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 31 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TFT10 to TFT0 All 0 R/W Transmit FIFO threshold When setting a transmit FIFO, the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR. H00: Store and forward modes H01 to H0C: Setting prohibited H0D: 52 bytes H0E: 56 bytes : : H1F: 124 bytes H20: 128 bytes : : H3F: 252 bytes H40: 256 bytes : : H7F: 508 bytes H80: 512 bytes : : HFF: 1020 bytes H100: 1024 bytes : : H1FF: 2044 bytes H200: 2048 bytes Note: When starting transmission before one frame of data write has completed, take care the generation of the underflow. Rev. 1.00 Dec. 27, 2005 Page 746 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.11 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the size of the transmit and receive FIFOs. Bit 31 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 TFD2 to TFD0 All 1 R/W Transmit FIFO Size Specifies 256 bytes to 2 kbytes in 256-byte units as the size of the transmit FIFO. The setting must not be changed after transmission/reception has started. All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 RFD2 to RFD0 All 1 R/W Receive FIFO Size Specifies 256 bytes to 2 kbytes in 256-byte units as the size of the receive FIFO. The setting must not be changed after transmission/reception has started. 7 to 3 Rev. 1.00 Dec. 27, 2005 Page 747 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.12 Receiving Method Control Register (RMCR) RMCR is a 32-bit readable/writable register that specifies the control method for the RE bit in ECMR when a frame is received. This register must be set during the receiving-halt state. Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RNC 0 R/W Receive Enable Control Sets whether to continue frame reception. 0: Upon completion of reception of one frame, the EDMAC writes receive status to the descriptor and clears the RR bit in EDRRR to 0 1: Upon completion of reception of one frame, the EDMAC writes (writes back) receive status to the descriptor. In addition, the E-DMAC reads the next descriptor and prepares for the reception of the next frame Rev. 1.00 Dec. 27, 2005 Page 748 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.13 E-DMAC Operation Control Register (EDOCR) EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC operation. Bit 31 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 FEC 0 R/W FIFO Error Control Specifies E-DMAC operation when transmit FIFO underflow or receive FIFO overflow occurs. 0: E-DMAC operation continues when underflow or overflow occurs 1: E-DMAC operation halts when underflow or overflow occurs 2 AEC 0 R/W Address Error Control Indicates detection of an illegal memory address in an attempted E-DMAC transfer. 0: Illegal memory address not detected (normal operation) 1: Indicates that E-DMAC operation is halted because an illegal memory address is detected. When 0 is written to this bit, the E-DMAC resumes operation 1 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 749 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.14 Receive Buffer Write Address Register (RBWAR) RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes data to the receiving buffer. Which addresses in the receiving buffer are processed by the EDMAC can be recognized by monitoring addresses displayed in this register. The address that the E-DMAC is actually processing may be different from the value read from this register. Bit 31 to 0 Bit Name RBWA31 to RBWA0 Initial Value All 0 R/W R Description Receiving-Buffer Write Address These bits can only be read. Writing is prohibited. 19.2.15 Receive Descriptor Fetch Address Register (RDFAR) RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the receiving descriptor. Which receiving descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit 31 to 0 Bit Name RDFA31 to RDFA0 Initial Value All 0 R/W R Description Receiving-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 19.2.16 Transmit Buffer Read Address Register (TBRAR) TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually reading in the buffer may be different from the value read from this register. Bit 31 to 0 Bit Name TBRA31 to TBRA0 Initial Value All 0 R/W R Description Transmission-Buffer Read Address These bits can only be read. Writing is prohibited. Rev. 1.00 Dec. 27, 2005 Page 750 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.17 Transmit Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmission descriptor. Which transmission descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit 31 to 0 Bit Name TDFA31 to TDFA0 Initial Value All 0 R/W R Description Transmission-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 19.2.18 Overflow Alert FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC. The threshold can be specified by the size of the receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). If the same receive FIFO size as set by the FIFO size register (FDR) is set when flow control is turned on according to the RFD setting condition, flow control is turned on with (FIFO data size - 64) bytes. For instance, when RFD in FDR = 7 and RFD in FCFTR = 7, flow control is turned on when (2048 - 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR. Flow control is turned on when any of the setting conditions of the RFF2 to RFF0 bits or the RFD2 to RFD0 bits is satisfied. Flow control is turned off when none of the conditions is satisfied (release). Rev. 1.00 Dec. 27, 2005 Page 751 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 31 to 19 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18 17 16 RFF2 RFF1 RFF0 1 1 1 R/W R/W R/W Receive FIFO Overflow Alert Signal Output Threshold 000: When one receive frame has been stored in the receive FIFO 001: When two receive frames have been stored in the receive FIFO : : 110: When seven receive frames have been stored in the receive FIFO 111: When eight receive frames have been stored in the receive FIFO 15 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 RFD2 RFD1 RFD0 1 1 1 R/W R/W R/W Receive FIFO Overflow Alert Signal Output Threshold 000: When (256 - 32) bytes of data is stored in the receive FIFO 001: When (512 - 32) bytes of data is stored in the receive FIFO : : 110: When (1792 - 32) bytes of data is stored in the receive FIFO 111: When (2048 - 64) bytes of data is stored in the receive FIFO Rev. 1.00 Dec. 27, 2005 Page 752 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.2.19 Transmit Interrupt Register (TRIMD) TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using the TWB bit in EESR and an interrupt on transmit operations. Bit 31 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TIS 0 R/W Transmit Interrupt Setting 0: Write-backed completion for each frame using the TWB bit in EESR is notified 1: Write-back completion for each frame is not notified 19.3 Operation Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of transmit/receive data between a Ethernet frame transmission/reception data storage destination of user- specified (accessible memory space: transmit buffer/receive buffer) and the transmit/receive FIFO in the E-DMAC. (The user cannot read and write data in the transmit/receive FIFO directly via the CPU). To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive data storage address and so forth, referred to as a descriptor, is required. Before Ethernet frame transmission/reception, the E-DMAC reads descriptor information, then reads transmit data from the transmit buffer or writes receive data to the receive buffer according to the read descriptor information. By arranging multiple descriptors as a descriptor row (list) (to be placed in a readable/writable memory space), multiple Ethernet frames can be transmitted or received continuously. Rev. 1.00 Dec. 27, 2005 Page 753 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.3.1 Descriptors and Descriptor List Two types of descriptors are available: transmit descriptors and receive descriptors. The E-DMAC automatically starts reading a transmit/receive descriptor when the TR bit in EDTRR is set to 1 or the RR bit in EDRRR is set to 1. In a transmit/receive descriptor, the user stores information about DMA transfer of transmit/receive data. After completion of Ethernet frame transmission/reception, the E-DMAC disables the descriptor valid/invalid bit and reflects the result of transmission/reception in the status bits. Descriptors are placed in a readable/writable memory space. The address of the start descriptor (descriptor to be read first by the E-DMAC) is set in TDLAR/RDLAR. When multiple descriptors are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous (memory) addresses according to the descriptor length set in the DL0 and DL1 bits in EDMR. The E-DMAC consists of two systems: system 0 and system 1. The DMAC for transmission and the DMAC for reception operate independently of each other, and the DMAC for system 0 and the DMAC for system 1 operate independently of each other. For normal E-DMAC operation, place descriptors for transmission and reception and descriptors for system 0 and system 1 in those address spaces that do not overlap. (1) Transmit Descriptor Figure 19.2 shows the configuration of a transmit descriptor and the relationship with a transmit buffer. The data of a transmit descriptor consists of TD0, TD1, TD2, and padding data in groups of 32 bits from top to end. The length of padding data is determined according to the descriptor length specified by the DL0 and DL1 bits in EDMR. In the figure, TBA (bits 31 to 0 in TD2) indicates the start address of a transmit buffer, and TDL (bits 31 to 16 in TD1) indicates the valid data length of the transmit buffer. TD0 indicates whether the transmit descriptor is valid or invalid as well as information about the descriptor configuration and status. TD1 indicates the length of data in a transmit buffer to be transferred according to the specification of the descriptor. TD2 indicates the start address of a transmit buffer that holds data to be transferred. Depending on the descriptor specification, one transmit descriptor can specify all transmit data of one frame (single-frame/single-buffer) or multiple descriptors can specify the transmit data of one frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by multiple descriptors. For example, multiple descriptors can share the destination address and Rev. 1.00 Dec. 27, 2005 Page 754 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) transmit source address in an Ethernet frame, and the remaining data can be stored in each separate buffer. Transmit descriptor 31 30 29 28 27 26 TTTTT ADFFF CLPPE TE10 31 Transmit buffer 0 TFS26 to TFS0 Valid transmit data TD0 16 TD1 31 TDL 0 TD2 TBA Padding (4/20/52 bytes)* Note: * According to the descriptor length set by the DL0 and DL1 bits in EDMR, the padding size is determined as follows: For 16 bytes: Padding = 4 bytes For 32 bytes: Padding = 20 bytes For 64 bytes: Padding = 52 bytes Figure 19.2 Relationship between Transmit Descriptor and Transmit Buffer Rev. 1.00 Dec. 27, 2005 Page 755 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Transmit Descriptor 0 (TD0) Before the TR bit in EDTRR is set to 1, the user sets the descriptor valid/invalid bit and sets other descriptor configuration. After completion of Ethernet frame transmission, the E-DMAC disables the descriptor valid/invalid bit and writes status information. This operation is referred to as writeback. When using TD0, the user should write desired values to bits 31 to 28 according to the descriptor configuration. Write 0 to bits 27 to 0. Bit 31 Bit Name TACT Initial Value 0 R/W R/W Description Transmit Descriptor Valid/Invalid Indicates whether the corresponding descriptor is valid or invalid. To make this bit valid, store transmit data in a transmit buffer (user-specified transmit data storage destination) beforehand, then write 1 to this bit. The E-DMAC clears this bit to 0 upon completion of data transfer. 0: Indicates that the transmit descriptor is invalid Indicates the initial setting state, the state after 0 is written, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because of completion of the processing of the E-DMAC data transfer. If this state is recognized when the E-DMAC reads a descriptor, the E-DMAC clears the TR bit in EDTRR to 0, and halts transfer operation related to transmission by the E-DMAC. 1: Indicates that the transmit descriptor is valid After the user writes 1 to this bit, this bit indicates that data is not transferred yet or data is being transferred. When there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the E-DMAC can continue operation when this bit of the next descriptor is valid. Rev. 1.00 Dec. 27, 2005 Page 756 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30 Bit Name TDLE Initial Value 0 R/W R/W Description Transmit Descriptor List End Indicates whether the corresponding descriptor is the last descriptor of the descriptor row (descriptor list). 0: Not last descriptor Upon completion of transfer of the corresponding descriptor, the E-DMAC reads the next one in the list of continuous descriptors. 1: Last descriptor Upon completion of transfer of the corresponding descriptor, the E-DMAC reads the descriptor placed at the address indicated by TDLAR. Rev. 1.00 Dec. 27, 2005 Page 757 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 29 28 Bit Name TFP1 TFP0 Initial Value 0 0 R/W R/W R/W Description Transmit Frame Position 1, 0 Indicates whether information of the corresponding descriptor represents information about the start, middle, or end of the transmit frame. 00: The information of the descriptor represents information about the middle of the frame. 01: The information of the descriptor represents information about the end of the frame. 10: The information of the descriptor represents information about the start of the frame. 11: The information of the descriptor represents all information about the frame (single-frame/singledescriptor (single-buffer)). Reference: When one frame is divided for use, the method of specifying this bit for a descriptor row according to the number of divisions is described below. [For single-frame/single-descriptor operation] First descriptor: TFP[1:0] = 11 [For single-frame/two-descriptor operation] First descriptor: TFP[1:0] = 10 Second descriptor: TFP[1:0] = 01 [For single-frame/three-descriptor operation] First descriptor: TFP[1:0] = 10 Second descriptor: TFP[1:0] = 00 Third descriptor: TFP[1:0] = 01 When the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with TFP[1:0] = 00. Rev. 1.00 Dec. 27, 2005 Page 758 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 27 Bit Name TFE Initial Value 0 R/W R/W Description Transmit Frame Error Occurrence Indicates that an error occurred in the transmit frame. The errors occurred in TFS8 (bit 8), or TFS3 to TFS0 (bits 3 to 0). 26 to 0 TFS26 to TFS0 All 0 R/W Transmit Frame Status Indicate the status of the corresponding frame. A bit below, when set to 1, indicates the occurrence of the corresponding event. If the events of TFS8, or TFS3 to TFS0 occur, frames are incompletely transmitted. TFS26 to TFS9: Reserved (The write value should always be 0.) TFS8: Transmit abort detected Note: This bit is set when any bit of TFS3 to TFS0 is set. TFS7 to TFS4: Reserved (The write value should always be 0) TFS3: Failure to detect the carrier at the start of transmission (corresponding to the CND bit in EESR) TFS2: Loss of the carrier during transmission (corresponding to the DLC bit in EESR) TFS1: Late (delayed) collision (corresponding to the CD bit in EESR) TFS0: Transmit retry over (corresponding to the TRO bit in EESR) Rev. 1.00 Dec. 27, 2005 Page 759 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Transmit Descriptor 1 (TD1) TD1 indicates the data length of the transmit buffer used by the corresponding descriptor. The user should set TD1 before the start of a read by the E-DMAC. Bit 31 to 16 Bit Name TDL Initial Value All 0 R/W R/W Description Transmit Buffer Data Length (in bytes) Indicate the data length of the corresponding transmit buffer in bytes. 15 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. (c) Transmit Descriptor 2 (TD2) TD2 indicates the start address of the corresponding 32-bit width transmit buffer. An address value on a longword boundary should be specified. The user should set TD2 before the start of a read by the E-DMAC. (2) Receive Descriptor Figure 19.3 shows the relationship between a receive descriptor and receive buffer. The data of a receive descriptor consists of RD0, RD1, RD2, and padding data in groups of 32 bits from top to end. The length of padding data is determined according to the descriptor length specified by the DL0 and DL1 bits in EDMR. In the figure, RBA (bits 31 to 0 in RD2) indicates the start address of a receive buffer. RBL (bits 31 to 16 in RD1) indicates the usable data length of the receive buffer. RDL (bits 15 to 0 in RD1) indicates the data length of a received frame. RD0 indicates whether the receive descriptor is valid or invalid as well as information about descriptor configuration and status. RD1 indicates the length (storage destination size) of data in the receive buffer to be received according to the specification of the descriptor. RD2 indicates the start address of the receive buffer for storing receive data. Depending on the descriptor specification, one receive descriptor can specify the storing of all receive data of one frame in a receive buffer (single-frame/single-buffer) or multiple descriptors can specify the storing of the receive data of one frame in receive buffers (single-frame/multibuffer). As an example of single-frame/multi-buffer operation, suppose that a row of multiple descriptors (descriptor list) is prepared, RBL of each descriptor is 500 bytes, and a 1514-byte Rev. 1.00 Dec. 27, 2005 Page 760 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Ethernet frame is received. In such a case, the received Ethernet frame is transferred sequentially to buffers, 500 bytes for each buffer, starting with the first descriptor. Only the last 14 bytes are transferred to the fourth buffer. When a frame longer than RBL of a descriptor is received, the E-DMAC transfers the remaining data to the receive buffer by using the subsequent descriptors. As an example of efficient single-frame/multi-buffer operation, information items on different processing layers in an Ethernet frame can be separated from each other by using different buffers. For example, the destination address, transmit source address, and type field data in an Ethernet frame can be stored in buffer 1 (with RBL set to 14 bytes) and the remaining data can be stored in buffer 2 (with RBL set to 1500 bytes). All receive frames, of course, can be stored in a single buffer if multiple descriptors are prepared and RBL of each descriptor is set to more than 1514 bytes (maximum Ethernet frame length). Receive descriptor 31 30 29 28 27 26 RRRRR ADF FF CLPPE TE1 0 RBL 31 31 16 RBA Padding (4/20/52 bytes)* 0 RFS26 to RFS0 Valid receive data Receive buffer RD0 15 0 RD1 RD2 RDL 0 Note: * According to the descriptor length set by the DL0 and DL1 bits in EDMR, the padding size is determined as follows: For 16 bytes: Padding = 4 bytes For 32 bytes: Padding = 20 bytes For 64 bytes: Padding = 52 bytes Figure 19.3 Relationship between Receive Descriptor and Receive Buffer Rev. 1.00 Dec. 27, 2005 Page 761 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Receive Descriptor 0 (RD0) The user sets the descriptor valid/invalid bit and sets whether the descriptor represents the end of the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the start of a read by the EDMAC. After completion of receive DMA transfer of an Ethernet frame by the E-DMAC, the EDMAC disables the descriptor valid/invalid bit and writes status information. This operation is referred to as write-back. When using RD0, the user should write desired values to bits 31 and 30 according to the descriptor configuration. Write 0 to bits 29 to 0. Bit 31 Bit Name RACT Initial Value 0 R/W R/W Description Receive Descriptor Valid/Invalid Indicates whether the corresponding descriptor is valid or invalid. To make this bit valid, prepare a receive buffer (user-specified receive data storage destination) beforehand, then write 1 to this bit. The E-DMAC clears this bit to 0 upon completion of data transfer. 0: Indicates that the receive descriptor is invalid Indicates the initial setting state, the state after 0 is written, or (in case the user writes 1 to this bit) that this bit is cleared to 0 because of completion of the processing of the E-DMAC data transfer. If this state is recognized when the E-DMAC reads a descriptor, the E-DMAC clears the RR bit in EDRRR to 0, and halts transfer operation related to reception by the E-DMAC. 1: Indicates that the receive descriptor is valid Indicates that data is not transferred yet after the user writes 1 to this bit, or that data is being transferred. When there is a descriptor row (descriptor list) consisting of multiple continuous descriptors, the E-DMAC can continue operation when this bit of the next descriptor is valid. Rev. 1.00 Dec. 27, 2005 Page 762 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30 Bit Name RDLE Initial Value 0 R/W R/W Description Receive Descriptor List End Indicates whether the corresponding descriptor is the last descriptor of the descriptor row (descriptor list). 0: Not last descriptor Upon completion of transfer of the corresponding descriptor, the E-DMAC reads the next one in the list of continuous descriptors. 1: Last descriptor Upon completion of transfer of the corresponding descriptor, the E-DMAC reads the descriptor placed at the address indicated by RDLAR. Rev. 1.00 Dec. 27, 2005 Page 763 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 29 28 Bit Name RFP1 RFP0 Initial Value 0 0 R/W R/W R/W Description Receive Frame Position 1, 0 The E-DMAC indicates by write-back operation whether information of the corresponding descriptor represents information about the start, middle, or end of the receive frame. 00: The information of the descriptor represents information about the middle of the frame. 01: The information of the descriptor represents information about the end of the frame. 10: The information of the descriptor represents information about the start of the frame. 11: The information of the descriptor represents all information about the frame (single-frame/singledescriptor (single-buffer)). Reference: The relationship between a frame after reception of one frame and a descriptor is described below. [For single-frame/single-descriptor operation] First descriptor: RFP[1:0] = 11 [For single-frame/two-descriptor operation] First descriptor: RFP[1:0] = 10 Second descriptor: RFP[1:0] = 01 [For single-frame/three-descriptor operation] First descriptor: RFP[1:0] = 10 Second descriptor: RFP[1:0] = 00 Third descriptor: RFP[1:0] = 01 When the number of divisions is large, a descriptor row is configured by adding intermediate descriptors with RFP[1:0] = 00. Rev. 1.00 Dec. 27, 2005 Page 764 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 27 Bit Name RFE Initial Value 0 R/W R/W Description Receive Frame Error Occurrence Indicates that an error occurred in the receive frame. The errors occurred in RFS8 (bit 8), or RFS3 to RFS0 (bits 3 to 0). TRSCER can specify whether the multicast address frame receive information is reflected in this bit or not. 26 to 0 RFS26 to RFS0 All 0 R/W Receive Frame Status Indicate the status of the corresponding frame. A bit below, when set to 1, indicates the occurrence of the corresponding event. If the events of RFS8, or RFS4 to RFS0 occur, frames are incompletely received. RFS26 to RFS10: Reserved (The write value should always be 0) RFS9: Receive FIFO overflow (corresponding to the RFOF bit in EESR) RFS8: Receive abort detected Note: This bit is set when any bit of RFS3 to RFS0 is set. RFS7: Multicast address frame received (corresponding to the RMAF bit in EESR) RFS6 and RFS5: Reserved (The write value should always be 0) RFS4: residual-bit frame receive error (corresponding to the RRF bit in EESR) RFS3: Too-long frame receive error (corresponding to the RTLF bit in EESR) RFS2: Too-short frame receive error (corresponding to the RTSF bit in EESR) RFS1: PHY-LSI receive error (corresponding to the PRE bit in EESR) RFS0: CRC error on receive frame (corresponding to the CERF bit in EESR) Rev. 1.00 Dec. 27, 2005 Page 765 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Receive Descriptor 1 (RD1) In RD1, the user specifies the data length of a receive buffer usable by the corresponding descriptor. After reception of a frame, RD1 indicates the length of a frame received by the E-DMAC. The user should set RD1 before the start of a read by the E-DMAC. Bit 31 to 16 Bit Name RBL Initial Value All 0 R/W R/W Description Receive Buffer Data Length (in bytes, to be specified on 16-byte boundary) Set the length of data that can be received by the corresponding receive buffer in bytes. Set a receive buffer length on a 16-byte boundary (with bits 19 to 16 cleared to 0). In single-frame/single-buffer (descriptor) operation, the maximum receive frame length excluding CRC data is 1514 bytes. When specifying a receive buffer length, set 1520 bytes (H'05F0), which is determined considering the maximum receive frame length and a 16-byte boundary. 15 to 0 RDL All 0 R Receive Data Length Indicate the data length of a receive frame stored in the receive buffer. Receive data transferred to the receive buffer does not include CRC data (4 bytes) placed at the end of a frame. As a receive frame length, the number of bytes (valid data bytes) not including CRC data are reported. In single-frame/multi-buffer (descriptor) operation, only the receive data length of the last descriptor is valid. The receive data length of an intermediate descriptor has no meaning. (c) Receive Descriptor 2 (RD2) RD2 indicates the start address of the corresponding 32-bit width receive buffer. Set the start address of a receive buffer on a longword boundary. When an SDRAM is connected, set the start address of a receive buffer on a 16-byte boundary. The user should set RD2 before the start of a read by the E-DMAC. Rev. 1.00 Dec. 27, 2005 Page 766 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.3.2 Transmission When 1 is written to the transmit request bit (TR) in the E-DMAC transmit request register (EDTRR) while the TE bit in ECMR is set to 1, the E-DMAC reads the descriptor following the previously used descriptor from the transmit descriptor list (or the descriptor indicated by the transmit descriptor start address register (TDLAR) at the initial start time). If the TACT bit of the read descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit frame data from the transmit buffer start address specified by TD2 for transfer to the EtherC. The EtherC creates a transmit frame and starts transmission to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the TFP value. 1. TFP = 00 or 10 (frame continuation): Descriptor write-back (writing 0 to the TACT bit) is performed after DMA transfer. 2. TFP = 01 or 11 (frame end): Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after completion of frame transmission. As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC descriptors and the transmission of frames continue. When a descriptor with the TACT bit cleared to 0 (invalid) is read, the E-DMAC clears the TR bit in EDTRR to 0 and completes transmit processing. Rev. 1.00 Dec. 27, 2005 Page 767 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission flowchart This LSI + memory E-DMAC Transmit FIFO EtherC Ethernet EtherC/E-DMAC initialization Transmit descriptor and transmit buffer setting Start of transmission Transmit descriptor read Transmit data transfer Transmit descriptor write-back Transmit descriptor read Transmit data transfer Frame transmission Transmit descriptor write-back Transmission completed [Legend] EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1. Transmit descriptor and transmit buffer setting: Sets transmit descriptors and transmit buffers, and sets EtherC and E-DMAC registers, then writes 1 to the TE bit in ECMR and the TR bit in EDTRR. Start of transmission: Occurs when 1 is written to the TE bit in ECMR and the TR bit in EDTRR. Transmit descriptor read: The E-DMAC reads a transmit descriptor. Transmit data transfer: Writes transmit data to the transmit FIFO by using DMA transfer by the E-DMAC. Transmit descriptor write-back: The E-DMAC writes 0 to the TACT bit and writes the transmit status to the transmit descriptor. Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) Rev. 1.00 Dec. 27, 2005 Page 768 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.3.3 Reception When 1 is written to the receive request bit (RR) in the E-DMAC receive request register (EDRRR) while the RE bit in ECMR is set to 1, the E-DMAC reads the descriptor following the previously used descriptor from the receive descriptor list (or the descriptor indicated by the receive descriptor start address register (RDLAR) at the initial start time) then enters the receive standby state. When the EtherC receives a frame for this LSI (with an address enabled for reception by this LSI), the EtherC stores the receive data in the receive FIFO. The receive data is transferred to the receive buffer specified by RD2 according to the receive descriptor with the RACT bit set to 1 (valid). If the data length of a received frame is longer than the buffer length specified by RD1, the E-DMAC performs a write-back operation to the descriptor (with RFP set to 10 or 00) when the buffer becomes full, then reads the next descriptor. The E-DMAC then continues to transfer data to the receive buffer specified by the new RD2. When frame reception is completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC performs write-back to the relevant descriptor (with RFP set to 11 or 01), and then ends the receive processing. The E-DMAC then reads the next descriptor and enters the receive standby state again. To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the receive method control register (RMCR). The initial value is 0. Rev. 1.00 Dec. 27, 2005 Page 769 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Reception flowchart This LSI + memory E-DMAC Receive FIFO EtherC Ethernet EtherC/E-DMAC initialization Receive descriptor and receive buffer setting Start of reception Receive descriptor read Frame reception Receive data transfer Receive descriptor write-back Receive descriptor read Receive data transfer Receive descriptor write-back Receive descriptor read (preparation for receiving the next frame) [Legend] EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1. Receive descriptor and receive buffer setting: Sets receive descriptors and receive buffers, and sets EtherC and E-DMAC registers, then writes 1 to the RE bit in ECMR and the RR bit in EDRRR. Start of reception: Occurs when 1 is written to the RE bit in ECMR and the RR bit in EDRRR. Receive descriptor read: The E-DMAC reads a receive descriptor. Receive data transfer: Writes receive data from the receive FIFO to the receive buffer by using DMA transfer by the E-DMAC. Receive descriptor write-back: The E-DMAC writes 0 to the RACT bit and writes the receive status to the receive descriptor. Reception completed Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor) Rev. 1.00 Dec. 27, 2005 Page 770 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.3.4 Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/ Multi-Descriptor) (1) Multi-Buffer Frame Transmit Processing If an error occurs during multi-buffer frame transmission, the processing shown in figure 19.6 is carried out by the E-DMAC. In the figure where the transmit descriptor is shown as inactive (TACT bit = 0), buffer data has already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit frame is determined on the basis of bits TFP1 and TFP0 (continuing [B00] or end [B01]). In the case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the final descriptor write-back. Descriptors T A C T T D L E T F P 1 T F P 0 Frame Type Start Continue Continue Continue Continue Continue Continue End Start Buffer length set by descriptor Untransmitted data is not transmitted after error occurrence. Descriptor is only processed. 00 00 00 Inactivates TACT (change 1 to 0) E-DMAC Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT and writes TFE, TFS 10 10 10 10 10 11 10 00 00 00 00 00 00 01 10 Transmit error occurrence One frame Transmitted data Untransmitted data Figure 19.6 E-DMAC Operation after Transmit Error Rev. 1.00 Dec. 27, 2005 Page 771 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (2) Receive Processing in Case of Multi-Buffer Frame If an error occurs during reception in the case of a multi-buffer frame where a receive frame is divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure 19.7. In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the normal reception of data to be stored in buffers, and the valid receive descriptors (with the RACT bit set to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor shown in the figure, the status is written back to the corresponding descriptor. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame receive request, reception is continued from the buffer after that in which the error occurred. Descritptors . . . . . . . . Inactivates RACT and writes RFE, RFS E-DMAC R A C T 0 0 0 1 R D L E 0 0 0 0 0 0 0 0 1 R F P 1 1 0 0 0 0 0 0 0 0 R F P 0 0 Frame type Start Start of frame 0 Continue 0 Continue 0 0 0 0 0 0 Buffer length set by descriptor New frame reception continues from this buffer Receive error occurrence Descriptor read 1 1 1 1 1 Received data Unreceived data Figure 19.7 E-DMAC Operation after Receive Error Rev. 1.00 Dec. 27, 2005 Page 772 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY) The E-DMAC outputs the receive FIFO overflow alert signal (ARBUSY) to the EtherC to support flow control function conforming to IEEE802.3x of the EtherC. The ARBUSY signal synchronized with the bus clock (B clock) signal is also output to an external pin of this LSI. When the capacity of data received in receive FIFO or the number of receive frames reach the threshold (RFF2 to RFF0, or RFD2 to RFD0) specified in FCFTR in E-DMAC, ARBUSY is valid. The threshold is the value less than the overflow value: 2048 - 64, 1792 - 32, 1536 - 32, and 256 - 32 bytes. Figure 19.9 shows the configuration of the receive FIFO overflow alert signal (ARBUSY) output. As shown in figure 19.9, because the ARBUSY signal passes through the system clock synchronization circuit, it is behind the receive FIFO overflow alert signal received in EtherC. This LSI E-DMAC0 Receive FIFO overflow alert signal EtherC E-DMAC1 Receive FIFO overflow alert signal System clock synchronization circuit ARBUSY Figure 19.8 Configuration of ARBUSY Rev. 1.00 Dec. 27, 2005 Page 773 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) (1) Operation of Receive FIFO Overflow Alert Signal Receive FIFO overflow alert signal is asserted when the number of the receive data accumulated in the receive FIFO is equal to or more than the threshold set in the overflow alert FIFO threshold register (FCFTR) (1). After that, when the number of the accumulated receive data drops below (threshold - 32) bytes, the signal is negated (2). Here, threshold values are as follows: 2048 - 64, 1792 - 32,.... Therefore, the signal-negated values are as follows: 2048 - 96, 1792 - 64,.... Receive data full Receive FIFO Threshold (threshold - 32) bytes (1) empty Alert signal Transfer to memory by E-DMAC (2) t Figure 19.9 Summary of Receive FIFO Overflow Alert Signal (a) Receive FIFO Overflow Alert Signal Changing The receive FIFO in the E-DMAC can perform writing (reception) data from the Ethernet line and reading data from the system simultaneously. Therefore during system operation, receive data of FIFO is always increased or decreased. If the change is performed near the threshold, the receive FIFO overflow alert signal may be seen as shown in figure 19.10. Minimum of receive data changes depending on the number of FIFO read cycles and rate of Ethernet line (10 to 100 Mbs). Rev. 1.00 Dec. 27, 2005 Page 774 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Threshold ( threshold - 32) bytes empty ARBUSY signal Minimum value (low): 150 nsec (Exernal bus operated at 66.66MHz and 16-byte burst transfer (5 cycle x 2)) t Minimum value (high): 2560 nsec (100 Base-T (100M Ether) operation) (Time for receiving 32-byte data) Figure 19.10 ARBUSY Signal Change and Minimum Pulse Width Depending on Increase and Decrease of FIFO Rev. 1.00 Dec. 27, 2005 Page 775 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.4 19.4.1 Usage Notes Using of EDTRR and EDRRR [Problems] While the Ethernet functions are being used, the TR bit in EDTRR or the RR bit in EDRRR is cleared to 0 to stop the E-DAMC functions if the descriptor valid bit is invalid. When the request bit (TR or RR) is cleared by the E-DMAC and the request bit (TR or RR) is set by the user's firmware simultaneously, transmission or reception may not be started even if the request bit (TR or RR) is set to 1. [Occurring Condition] When the user's firmware tries to set the request bit (TR or RR), while the request bit (TR or RR) is 1. [Avoiding Methods] To prevent the simultaneous occurrence of the request bit (TR or RR) being cleared by the EDMAC and the request bit (TR or RR) being set by the user's firmware, the user's firmware should set the request bit (TR or RR) after confirming that it is cleared by the E-DMAC. The methods to clear the RR bit with E-DMAC are as follows. (1) Confirmation of the TR bit As a direct method, it is possible to confirm by reading the TR bit in EDTRR as 0. As an indirect method, it is possible to confirm by reading the TDE bit in EESR as 1. (2) Confirmation of the RR bit As a direct method, it is possible to confirm by reading the RR bit in EDRRR as 0. As an indirect method, it is possible to confirm by reading the RDE bit in EESR as 0. Rev. 1.00 Dec. 27, 2005 Page 776 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) 19.4.2 Endian Support in E-DMAC When the external memory is accessed through the E-DMAC, big endian is supported but little endian is not supported. Therefore, if the external memory is accessed through the E-DMAC in little endian mode, data format should be converted from big endian mode to little endian mode through software. Rev. 1.00 Dec. 27, 2005 Page 777 of 932 REJ09B0269-0100 Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 1.00 Dec. 27, 2005 Page 778 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) Section 20 Pin Function Controller (PFC) 20.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Tables 20.1 and 20.2 list the multiplexed pins. Table 20.1 List of Multiplexed Pins (1) Port A A A A A A A A B B B B B B B B C C C C Port Function (Related Module) PTA7 input/output (port) PTA6 input/output (port) PTA5 input/output (port) PTA4 input/output (port) PTA3 input/output (port) PTA2 input/output (port) PTA1 input/output (port) PTA0 input/output (port) PTB7 input/output (port) PTB6 input/output (port) PTB5 input/output (port) PTB4 input/output (port) PTB3 input/output (port) PTB2 input/output (port) PTB1 input/output (port) PTB0 input/output (port) PTC7 input/output (port) PTC6 input/output (port) PTC5 input/output (port) PTC4 input/output (port) Other Function (Related Module) SIOFSYNC0 input/output (SIOF0) TXD_SIO0 output (SIOF0) RXD_SIO0 input (SIOF0) SIOMCLK0 input (SIOF0) SCK_SIO0 input/output (SIOF0) SCIF0CK input/output (SCIF0) TXD0 output (SCIF0) RXD0 input (SCIF0) RTS0 output (SCIF0) CTS0 input (SCIF0) SCIF1CK input/output (SCIF1) TXD1 output (SCIF1) RXD1 input (SCIF1) RTS1 output (SCIF1) CTS1 input (SCIF1) Reserved (setting prohibited)* IOIS16 input (BSC) CE2B output (BSC) CE2A output (BSC) SIOFSYNC1 input/output (SIOF1) Rev. 1.00 Dec. 27, 2005 Page 779 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) Port C C C C Note: * Port Function (Related Module) PTC3 input/output (port) PTC2 input/output (port) PTC1 input/output (port) PTC0 input/output (port) Other Function (Related Module) TXD_SIO1 output (SIOF1) RXD_SIO1 input (SIOF1) SIOMCLK1 input (SIOF1) SCK_SIO1 input/output (SIOF1) When the register is set to reserved, the operation is not guaranteed. Table 20.2 List of Multiplexed Pins (2) Ethernet controller Function EXOUT1 output CAMSEN1 input EXOUT0 output CAMSEN0 input Other Function (Related Module) TEND1 output (DMAC) IRQ5 input (INTC) TEND0 output (DMAC) IRQ4 input (INTC) 20.2 Register Configuration The registers of the pin function controller are shown below. * * * * Port A control register (PACR) Port B control register (PBCR) Port C control register (PCCR) Ethernet controller pin control register (PETCR) Rev. 1.00 Dec. 27, 2005 Page 780 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) 20.3 20.3.1 Register Descriptions Port A Control Register (PACR) PACR is a 16-bit readable/writable register that selects the pin functions. PACR is initialized to HAAAA by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA7MD1 PA7MD0 PA6MD1 PA6MD0 PA5MD1 PA5MD0 PA4MD1 PA4MD0 PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Modes PA7 to PA0 Control The combination of PAnMD1 and PAnMD0 (n = 0 to 7) selects the pin functions and control input pull-up MOS. 00: Other function (see Table 20.1) 01: Port output 10: Port input (pull-up MOS: on) 11: Port input (pull-up MOS: off) Rev. 1.00 Dec. 27, 2005 Page 781 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) 20.3.2 Port B Control Register (PBCR) PBCR is a 16-bit readable/writable register that selects the pin functions. PBCR is initialized to HAAAA by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Modes PB7 to PB0 Control The combination of PBnMD1 and PBnMD0 (n = 0 to 7) selects the pin functions and controls input pull-up MOS. 00: Other function (n = 1 to 7) or reserved (n = 0) (see Table 20.1) 01: Port output 10: Port input (pull-up MOS: on) 11: Port input (pull-up MOS: off) Rev. 1.00 Dec. 27, 2005 Page 782 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) 20.3.3 Port C Control Register (PCCR) PCCR is a 16-bit readable/writable register that selects the pin functions. PCCR is initialized to HAAAA by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PC7MD1 PC7MD0 PC6MD1 PC6MD0 PC5MD1 PC5MD0 PC4MD1 PC4MD0 PC3MD1 PC3MD0 PC2MD1 PC2MD0 PC1MD1 PC1MD0 PC0MD1 PC0MD0 Initial Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Modes PC7 to PC0 Control The combination of PCnMD1 and PCnMD0 (n = 0 to 7) selects the pin functions and controls input pull-up MOS. 00: Other function (see Table 20.1.) 01: Port output 10: Port input (pull-up MOS: on) 11: Port input (pull-up MOS: off) Rev. 1.00 Dec. 27, 2005 Page 783 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) 20.3.4 Ethernet Controller Pin Control Register (PETCR) PETCR is a 16-bit readable/writable register that selects the pin functions. PETCR is initialized to HAAAA by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. Bit 15 Bit Name PET3MD Initial Value 1 R/W R/W Description Controls output of EXOUT1 (Ethernet controller function) and TEND1 (other function). 0: TEND1 (other function) is selected. 1: EXOUT1 (Ethernet controller function) is selected. 14 0 R Reserved This bit is always read as 0. The write value should always be 0. 13 PET2MD 1 R/W Controls input of CAMSEN1 (Ethernet controller function) and IRQ5 (other function). 0: IRQ5 (other function) is selected. 1: CAMSEN1 (Ethernet controller function) is selected. 12 0 R Reserved This bit is always read as 0. The write value should always be 0. 11 PET1MD 1 R/W Controls output of EXOUT0 (Ethernet controller function) and TEND0 (other function). 0: TEND0 (other function) is selected. 1: EXOUT0 (Ethernet controller function) is selected. 10 0 R Reserved This bit is always read as 0. The write value should always be 0. 9 PET0MD 1 R/W Controls input of CAMSEN0 (Ethernet controller function) and IRQ4 (other function). 0: IRQ4 (other function) is selected. 1: CAMSEN0 (Ethernet controller function) is selected. Rev. 1.00 Dec. 27, 2005 Page 784 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) Bit 8 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 7 1 R Reserved This bit is always read as 1. The write value should always be 1. 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5 1 R Reserved This bit is always read as 1. The write value should always be 1. 4 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 1 R Reserved This bit is always read as 1. The write value should always be 1. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 1 R Reserved This bit is always read as 1. The write value should always be 1. 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Dec. 27, 2005 Page 785 of 932 REJ09B0269-0100 Section 20 Pin Function Controller (PFC) Rev. 1.00 Dec. 27, 2005 Page 786 of 932 REJ09B0269-0100 Section 21 I/O Ports Section 21 I/O Ports 21.1 Overview This LSI has three 8-bit ports (ports A to C). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins. 21.2 21.2.1 Register Descriptions Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. PADR is initialized to H00 by a power-on reset but is not initialized by a manual reset, in standby mode, or sleep mode. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin function is general output port, if the port is read, the value of the corresponding PADR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 21.1 shows the function of PADR. Rev. 1.00 Dec. 27, 2005 Page 787 of 932 REJ09B0269-0100 Section 21 I/O Ports Table 21.1 Port A Data Register (PADR) Read/Write Operations PAnMD1 PAnMD0 Pin State 0 0 1 1 0 1 [Legend] n = 0 to 7 Read Write Value is written to PADR, but does not affect pin state. Write value is output from pin. Value is written to PADR, but does not affect pin state. Value is written to PADR, but does not affect pin state. Other function PADR value Output Input (Pull-up MOS on) Input (Pull-up MOS off) PADR value Pin state Pin state 21.2.2 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores the data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to the pins PTB7 to PTB0. PBDR is initialized to H00 by a poweron reset but is not initialized by a manual reset, in standby mode, or sleep mode. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin function is general output port, if the port is read, the value of the corresponding PBDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Tables 21.2 and 21.3 show the function of PBDR. Rev. 1.00 Dec. 27, 2005 Page 788 of 932 REJ09B0269-0100 Section 21 I/O Ports Table 21.2 Port B Data Register (PBDR) Read/Write Operations (1) PBnMD1 PBnMD0 Pin State 0 0 1 1 0 1 [Legend] n = 1 to 7 Read Write Value is written to PBDR, but does not affect pin state. Write value is output from pin. Value is written to PBDR, but does not affect pin state. Value is written to PBDR, but does not affect pin state. Other function PBDR value Output Input (Pull-up MOS on) Input (Pull-up MOS off) PBDR value Pin state Pin state Table 21.3 Port B Data Register (PBDR) Read/Write Operations (2) PBnMD1 PBnMD0 Pin State 0 0 1 1 0 1 [Legend] n=0 Note: * Reserved* Output Input (Pull-up MOS on) Input (Pull-up MOS off) Read PBDR value PBDR value Pin status Pin status Write Value is written to PBDR, but does not affect pin state. Write value is output from pin. Value is written to PBDR, but does not affect pin state. Value is written to PBDR, but does not affect pin state. When this pin is specified as a reserved pin, its operation is not guaranteed. Rev. 1.00 Dec. 27, 2005 Page 789 of 932 REJ09B0269-0100 Section 21 I/O Ports 21.2.3 Port C Data Register (PCDR) PCDR is an 8-bit readable/writable register that stores the data for pins PTC7 to PTC0. Bits PC7DT to PC0DT correspond to the pins PTC7 to PTC0. PCDR is initialized to H00 by a poweron reset but is not initialized by a manual reset, in standby mode, or sleep mode. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 21.4 shows the function of PCDR. Table 21.4 Port C Data Register (PCDR) Read/Write Operations PCnMD1 PCnMD0 Pin State 0 0 1 1 0 1 [Legend] n = 0 to 7 Read Write Value is written to PCDR, but does not affect pin state. Write value is output from pin. Value is written to PCDR, but does not affect pin state. Value is written to PCDR, but does not affect pin state. Other function PCDR value Output Input (Pull-up MOS on) Input (Pull-up MOS off) PCDR value Pin state Pin state Rev. 1.00 Dec. 27, 2005 Page 790 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Section 22 User Debugging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section describes the H-UDI. The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD. 22.1 Features The H-UDI (User debugging interface) is a serial I/O interface which conforms to JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and BoundaryScan Architecture) specifications. The H-UDI in this LSI supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. Figure 22.1 shows a block diagram of the H-UDI. TDI SDBPR Shift register SDBSR SDIR SDID TDO MUX TCK TMS TRST TAP controller Decoder Local bus Figure 22.1 Block Diagram of H-UDI Rev. 1.00 Dec. 27, 2005 Page 791 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) 22.2 Input/Output Pins Table 22.1 shows the pin configuration of the H-UDI. Table 22.1 Pin Configuration Pin Name TCK Input/Output Input Description Serial Data Input/Output Clock Pin Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. TMS Input Mode Select Input Pin The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std.1149.1). TRST Input Reset Input Pin Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. TRST must be low for a constant period when power is turned on regardless of using the H-UDI function. As the same as the RESETP pin, the TRST pin should be driven low at the power-on reset state and driven high after the power-on reset state is released. This is different from the JTAG standard. See section 22.4.2, Reset Configuration, for more information. TDI Input Serial Data Input Pin Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. TDO Output Serial Data Output Pin Data read from the H-UDI is executed by reading this pin in synchronization with TCK. The data output timing depends on the command type set in the SDIR. See section 22.4.3 TDO Output Timing, for more information. ASEMD0 Input ASE Mode Select Pin If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. In ASE mode, dedicated emulator function can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. Rev. 1.00 Dec. 27, 2005 Page 792 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Pin Name ASEBRKAK AUDSYNC AUDATA3 to 0 AUDCK Input/Output Output Output Output Output Description Dedicated emulator pin 22.3 Register Descriptions The H-UDI has the following registers. Refer the section 23, List of Registers, for the addresses and access size for registers. * * * * Bypass register (SDBPR) Instruction register (SDIR) Boundary scan register (SDBSR) ID register (SDID) Bypass Register (SDBPR) 22.3.1 SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined but SDBPR is initialized to 0 if the TAP is in Capture-DR state. 22.3.2 Instruction Register (SDIR) SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the HUDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register. Rev. 1.00 Dec. 27, 2005 Page 793 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 15 to 13 12 11 to 8 7 to 2 1 0 Bit Name TI7 to TI5 TI4 TI3 to TI0 Initial Value All 1 0 All 1 All 1 0 1 R/W R R R R R R Description Test Instruction 7 to 0 The H-UDI instruction is transferred to SDIR by a serial input from TDI. For commands, see Table 22.2. Reserved These bits are always read as 1. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Table 22.2 H-UDI Commands Bits 15 to 8 TI7 0 0 0 0 0 0 1 1 1 TI6 0 0 0 1 1 1 0 1 1 TI5 0 1 1 0 1 1 1 1 1 TI4 0 0 1 0 0 1 -- 0 1 TI3 -- -- -- -- -- -- -- -- -- TI2 -- -- -- -- -- -- -- -- -- TI1 -- -- -- -- -- -- -- -- -- TI0 -- -- -- -- -- -- -- -- -- Description JTAG EXTEST JTAG CLAMP JTAG HIGHZ JTAG SAMPLE/PRELOAD H-UDI reset negate H-UDI reset assert H-UDI interrupt JTAG IDCODE (Initial value) JTAG BYPASS Reserved Other than the above 22.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register, located on the PAD, for controlling the input/output pins of this LSI. The initial value is undefined. SDBSR cannot be accessed by the CPU. Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 22.3 shows the correspondence between this LSI's pins and boundary scan register bits. Rev. 1.00 Dec. 27, 2005 Page 794 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Table 22.3 This LSI's Pins and Boundary Scan Register Bits Bit Pin Name from TDI 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 BREQ WAIT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 BACK CS0 CS4 CS5A CS6A RD BS D0 D1 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN I/O Bit 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 Pin Name D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WE0(BE0)/DQMLL WE1(BE1)/DQMLU/WE RD/WR CAS CKE RAS CS2 CS3 A0 A1 A2 A3 A4 A5 A6 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT REFOUT/IRQOUT/ARBUSY OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 1.00 Dec. 27, 2005 Page 795 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 Pin Name A7 A8 A9 A10 A11 A12 BACK CS0 CS4 CS5A CS6A RD BS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WE0(BE0)/DQMLL WE1(BE1)/DQMLU/WE I/O OUT OUT OUT OUT OUT OUT Bit 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 Pin Name RD/WR CAS CKE RAS CS2 CS3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN REFOUT/IRQOUT/ARBUSY Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 1.00 Dec. 27, 2005 Page 796 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 Pin Name D29 D30 D31 PTB0 PTB1/CTS1 PTB2/RTS1 PTB3/RXD1 PTB4/TXD1 PTB5/SCIF1CK PTB6/CTS0 PTB7/RTS0 PTA0/RXD0 PTA1/TXD0 PTA2/SCIF0CK PTA3/SCK_SIO0 PTA4/SIOMCLK0 PTA5/RXD_SIO0 PTA6/TXD_SIO0 PTA7/SIOFSYNC0 A13 A14 A15 A16 A17 WE2(BE2)/DQMUL/ICIORD I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT Bit 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 Pin Name D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A18 A19 A20 A21 A22 A23 A24 A25 PTB0 PTB1/CTS1 PTB2/RTS1 PTB3/RXD1 PTB4/TXD1 PTB5/SCIF1CK PTB6/CTS0 PTB7/RTS0 PTA0/RXD0 PTA1/TXD0 PTA2/SCIF0CK PTA3/SCK_SIO0 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT WE3(BE3)/DQMUU/ICIOWR OUT D16 D17 D18 D19 D20 OUT OUT OUT OUT OUT Rev. 1.00 Dec. 27, 2005 Page 797 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 Pin Name PTA4/SIOMCLK0 PTA5/RXD_SIO0 PTA6/TXD_SIO0 PTA7/SIOFSYNC0 A13 A14 A15 A16 A17 I/O OUT OUT OUT OUT Control Control Control Control Control Bit 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 Pin Name A22 A23 A24 A25 PTB0 PTB1/CTS1 PTB2/RTS1 PTB3/RXD1 PTB4/TXD1 PTB5/SCIF1CK PTB6/CTS0 PTB7/RTS0 PTA0/RXD0 PTA1/TXD0 PTA2/SCIF0CK PTA3/SCK_SIO0 PTA4/SIOMCLK0 PTA5/RXD_SIO0 PTA6/TXD_SIO0 PTA7/SIOFSYNC0 CRS1 COL1 TX-CLK1 RX-ER1 RX-CLK1 RX-DV1 ERXD10 ERXD11 ERXD12 ERXD13 MDIO1 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN WE2(BE2)/DQMUL/ICIORD Control WE3(BE3)/DQMUU/ICIOWR Control D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A18 A19 A20 A21 Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 1.00 Dec. 27, 2005 Page 798 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Pin Name LNKSTA1 CAMSEN1/IRQ5 CRS0 COL0 TX-CLK0 RX-ER0 RX-CLK0 RX-DV0 ERXD00 ERXD01 ERXD02 ERXD03 MDIO0 LNKSTA0 CAMSEN0/IRQ4 MD4 MD5 ETXD13 ETXD12 ETXD11 ETXD10 TX-EN1 TX-ER1 MDC1 MDIO1 WOL1 EXOUT1/TEND1 ETXD03 ETXD02 ETXD01 ETXD00 I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Pin Name TX-EN0 TX-ER0 MDC0 MDIO0 WOL0 EXOUT0/TEND0 ETXD13 ETXD12 ETXD11 ETXD10 TX-EN1 TX-ER1 MDC1 MDIO1 WOL1 EXOUT1 ETXD03 ETXD02 ETXD01 ETXD00 TX-EN0 TX-ER0 MDC0 MDIO0 WOL0 EXOUT0 NMI IRQ0/IRL0 IRQ1/IRL1 IRQ2/IRL2 IRQ3/IRL3 I/O OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN Rev. 1.00 Dec. 27, 2005 Page 799 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Bit 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Pin Name DREQ0 DREQ1 PTC0/SCK_SIO1 PTC1/SIOMCLK1 PTC2/RXD_SIO1 PTC3/TXD_SIO1 PTC4/SIOFSYNC1 PTC5/CE2A PTC6/CE2B PTC7/IOIS16 MD0 MD1 MD2 MD3 ASEBRKAK AUDSYNC AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 STATUS0 STATUS1 DACK0 DACK1 PTC0/SCK_SIO1 PTC1/SIOMCLK1 PTC2/RXD_SIO1 PTC3/TXD_SIO1 I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pin Name PTC4/SIOFSYNC1 PTC5/CE2A PTC6/CE2B PTC7/IOIS16 CS5B/CE1A CS6B/CE1B ASEBRKAK AUDSYNC AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 STATUS0 STATUS1 DACK0 DACK1 PTC0/SCK_SIO1 PTC1/SIOMCLK1 PTC2/RXD_SIO1 PTC3/TXD_SIO1 PTC4/SIOFSYNC1 PTC5/CE2A PTC6/CE2B PTC7/IOIS16 CS5B/CE1A CS6B/CE1B To TDO I/O OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Note: Control is an active-low signal. When Control is driven low, the corresponding pin is driven by the value of OUT. Rev. 1.00 Dec. 27, 2005 Page 800 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) 22.3.4 ID Register (SDID) The ID register (SDID) is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by CPU. The IDCODE command is set from the H-UDI pin. This register can be read from the TDO when the TAP state is Shift-DR. Writing is disabled. Bit 31 to 0 Bit Name DID31 to DID0 Initial Value Refer to description R/W R Description Device ID31 to 0 Device ID register that is stipulated by JTAG. Device ID in this LSI is H'081E200F. Upper four bits may be changed by the chip version. SDIDH corresponds to bits 31 to 16. SDIDL corresponds to bits 15 to 0. Rev. 1.00 Dec. 27, 2005 Page 801 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) 22.4 22.4.1 Operation TAP Controller Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 1 1 1 0 Run-test/idle Select-DR-scan 0 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 0 1 0 Pause-DR 1 Exit2-DR 1 Update-DR 0 1 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 Figure 22.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details on change timing of the TDO value, see section 22.4.3, TDO Output Timing. The TDO is at high impedance, except with shift-DR and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. Rev. 1.00 Dec. 27, 2005 Page 802 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) 22.4.2 Reset Configuration Table 22.4 Reset Configuration ASEMD0*1 H RESETP L TRST L H H L H L L L H Chip State Normal reset and H-UDI reset*4 Normal reset*4 H-UDI reset only Normal operation Reset hold*2 In ASE user mode*3: Normal reset In ASE break mode* : RESETP assertion is masked 3 H L H H-UDI reset only Normal operation Notes: 1. Performs normal mode and ASE mode settings ASEMD0 = H, normal mode ASEMD0 = L, ASE mode 2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a constant cycle. In this state, the CPU does not activate, even if RESETP is driven high. When TRST is driven high, H-UDI operation is enabled, but the CPU does not activate. The reset hold state is canceled by the following conditions: * Another RESETP assertion (power-on reset) * TRST reassertion 3. ASE mode is classified into two modes; ASE break mode to execute the firmware program of an emulator and ASE user mode to execute the user program. 4. Make sure the TRST pin is low when the power is turned on. 22.4.3 TDO Output Timing The timing of data output from the TDO is switched by the command type set in the SDIR. The timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ, SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard. When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle. Rev. 1.00 Dec. 27, 2005 Page 803 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) TCK TDO (when the H-UDI command is set) TDO (when the JTAG command is set) tTDO tTDO Figure 22.3 H-UDI Data Transfer Timing 22.4.4 H-UDI Reset An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command. The required time between the H-UDI reset assert command and H-UDI reset negate command is the same as time for keeping the RESETP pin low to apply a power-on reset. SDIR H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Branch to H'A0000000 Figure 22.4 H-UDI Reset 22.4.5 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a fixed priority level of 15. H-UDI interrupts are accepted in sleep mode. Rev. 1.00 Dec. 27, 2005 Page 804 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) 22.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 22.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The upper four bits of the instruction code are B'1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The upper four bits of the instruction code are 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when the this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Rev. 1.00 Dec. 27, 2005 Page 805 of 932 REJ09B0269-0100 Section 22 User Debugging Interface (H-UDI) Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The upper four bits of the instruction code are B'0000. IDCODE: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the IDCODE mode stipulated by JTAG. When the H-UDI is initialized (TRST is asserted or TAP is in the Test-Logic-Reset state), the IDCODE mode is entered. CLAMP, HIGHZ: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the CLAMP or HIGHZ mode stipulated by JTAG. 22.5.2 Points for Attention 1. Boundary scan mode does not cover clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO, CKIO2). 2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM). 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. Boundary scan mode does not cover the ASEMD0 pin. 5. When the EXTEST, CLAMP, and HIGHZ commands are set, fix the RESETP pin low. 6. When a boundary scan test for other than BYPASS and IDCODE is carried out, fix the ASEMD0 pin high. 22.6 Usage Notes 1. An H-UDI command, once set, will not be modified as long as another command is not reissued from the H-UDI. If the same command is given continuously, the command must be set after a command (BYPASS, etc.) that does not affect chip operations is once set. 2. In standby mode, the H-UDI function cannot be used. To retain the TAP status before and after standby mode, keep TCK high before entering standby mode. 3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. 22.7 Advanced User Debugger (AUD) The AUD is a function only for an emulator. For details on the AUD, refer to each emulator's user's manual. Rev. 1.00 Dec. 27, 2005 Page 806 of 932 REJ09B0269-0100 Section 23 List of Registers Section 23 List of Registers The address map gives information on the on-chip I/O registers and is configured as described below. Register Addresses (by functional module, in order of the corresponding section numbers): * Descriptions by functional module, in order of the corresponding section numbers. * Access to reserved addresses which are not described in this list is prohibited. * When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the presumption of a big-endian system. Register Bits: * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * Reserved bits are indicated by in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 or 32 bits, bits are described from the MSB side. The order in which bytes are described is on the presumption of a big-endian system. Register States in Each Operating Mode: * Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module. Rev. 1.00 Dec. 27, 2005 Page 807 of 932 REJ09B0269-0100 Section 23 List of Registers 23.1 Register Addresses (by functional module, in order of the corresponding section numbers) Entries under Access Size indicates number of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Abbreviation INTEVT INTEVT2 TRA EXPEVT TEA MMUCR PTEH PTEL TTB CCR1 CCR2 CCR3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI ICR0 ICR1 INTC Cache MMU Module*1 Exception handling Bus*2 L L L L L L L L L L L L P P P P P P P P P P P Address H'FFFF FFD8 H'A400 0000 H'FFFF FFD0 H'FFFF FFD4 H'FFFF FFFC H'FFFF FFE0 H'FFFF FFF0 H'FFFF FFF4 H'FFFF FFF8 H'FFFF FFEC H'A400 00B0 H'A400 00B4 H'A414 FEE2 H'A414 FEE4 H'A414 0016 H'A414 0018 H'A414 001A H'A408 0000 H'A408 0002 H'A408 0004 H'A408 0006 H'A414 FEE0 H'A414 0010 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 16 16 16 16 16 16 Rev. 1.00 Dec. 27, 2005 Page 808 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation IRR0 IRR1 IRR2 IRR3 IRR4 IRR5 IRR7 IRR8 BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR BASRA BASRB STBCR STBCR2 STBCR3 FRQCR WTCNT WTCSR CMNCR CS0BCR CS2BCR Module*1 INTC Bus*2 P P P P P P P P Address H'A414 0004 H'A414 0006 H'A414 0008 H'A414 000A H'A414 000C H'A408 0020 H'A408 0024 H'A408 0026 H'A4FF FFB0 H'A4FF FFB4 H'A4FF FFB8 H'A4FF FFA0 H'A4FF FFA4 H'A4FF FFA8 H'A4FF FF90 H'A4FF FF94 H'A4FF FF98 H'A4FF FF9C H'A4FF FFAC H'A4FF FFBC H'FFFF FFE4 H'FFFF FFE8 H'A415 FF82 H'A415 FF88 H'A40A 0000 H'A415 FF80 H'A415 FF84 H'A415 FF86 H'A4FD 0000 H'A4FD 0004 H'A4FD 0008 Access Size Size (bit) (bit)*3 8 8 8 8 8 8 8 8 32 32 16 32 32 16 32 32 32 16 32 32 8 8 8 8 8 16 8 8 32 32 32 8 8 8 8 8 8 8 8 32 32 16 32 32 16 32 32 32 16 32 32 8 8 8 8 8 16 8/16*4 8/16*4 32 32 32 UBC L L L L L L L L L L L L L L Power-down P mode P P CPG P P P BSC I I I Rev. 1.00 Dec. 27, 2005 Page 809 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation CS3BCR CS4BCR CS5ABCR CS5BBCR CS6ABCR CS6BBCR CS0WCR CS2WCR CS3WCR CS4WCR CS5AWCR CS5BWCR CS6AWCR CS6BWCR SDCR RTCSR RTCNT RTCOR SDMR2 SDMR3 SAR_0 DAR_0 DMATCR_0 CHCR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 SAR_2 DAR_2 DMATCR_2 Module*1 BSC Bus*2 I I I I I I I I I I I I I I I I I I I I Address H'A4FD 000C H'A4FD 0010 H'A4FD 0014 H'A4FD 0018 H'A4FD 001C H'A4FD 0020 H'A4FD 0024 H'A4FD 0028 H'A4FD 002C H'A4FD 0030 H'A4FD 0034 H'A4FD 0038 H'A4FD 003C H'A4FD 0040 H'A4FD 0044 H'A4FD 0048 H'A4FD 004C H'A4FD 0050 H'A4FD 4xxx H'A4FD 5xxx H'A401 0020 H'A401 0024 H'A401 0028 H'A401 002C H'A401 0030 H'A401 0034 H'A401 0038 H'A401 003C H'A401 0040 H'A401 0044 H'A401 0048 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 DMAC P P P P P P P P P P P Rev. 1.00 Dec. 27, 2005 Page 810 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation CHCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 SAR_4 DAR_4 DMATCR_4 CHCR_4 SAR_5 DAR_5 DMATCR_5 CHCR_5 DMAOR DMARS0 DMARS1 DMARS2 TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 R64CNT RSECCNT RMINCNT RHRCNT Module*1 DMAC Bus*2 P P P P P P P P P P P P P P P P P Address H'A401 004C H'A401 0050 H'A401 0054 H'A401 0058 H'A401 005C H'A401 0070 H'A401 0074 H'A401 0078 H'A401 007C H'A401 0080 H'A401 0084 H'A401 0088 H'A401 008C H'A401 0060 H'A409 0000 H'A409 0004 H'A409 0008 H'A412 FE92 H'A412 FE94 H'A412 FE98 H'A412 FE9C H'A412 FEA0 H'A412 FEA4 H'A412 FEA8 H'A412 FEAC H'A412 FEB0 H'A412 FEB4 H'A413 FEC0 H'A413 FEC2 H'A413 FEC4 H'A413 FEC6 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 8 32 32 16 32 32 16 32 32 16 8 8 8 8 8/16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 8/16/32 8/16 16 16 16 8 32 32 16 32 32 16 32 32 16 8 8 8 8 TMU P P P P P P P P P P RTC P P P P Rev. 1.00 Dec. 27, 2005 Page 811 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 RYRAR RCR3 SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 Module*1 RTC Bus*2 P P P P P P P P P P P P P P Address H'A413 FEC8 H'A413 FECA H'A413 FECC H'A413 FECE H'A413 FED0 H'A413 FED2 H'A413 FED4 H'A413 FED6 H'A413 FED8 H'A413 FEDA H'A413 FEDC H'A413 FEDE H'A413 FEE0 H'A413 FEE4 H'A440 0000 H'A440 0004 H'A440 0008 H'A440 000C H'A440 0010 H'A440 0014 H'A440 0018 H'A440 001C H'A440 0024 H'A441 0000 H'A441 0004 H'A441 0008 H'A441 000C H'A441 0010 H'A441 0014 H'A441 0018 H'A441 001C Access Size Size (bit) (bit)*3 8 8 8 16 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 16 16 16 8 16 8 16 8 16 16 8 8 8 16 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 16 16 16 8 16 8 16 8 16 16 SCIF P P P P P P P P P P P P P P P P P Rev. 1.00 Dec. 27, 2005 Page 812 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation SCLSR_1 SIMDR_0 SISCR_0 SITDAR_0 SIRDAR_0 SICDAR_0 SICTR_0 SIFCTR_0 SISTR_0 SIIER_0 SITDR_0 SIRDR_0 SITCR_0 SIRCR_0 SIMDR_1 SISCR_1 SITDAR_1 SIRDAR_1 SICDAR_1 SICTR_1 SIFCTR_1 SISTR_1 SIIER_1 SITDR_1 SIRDR_1 SITCR_1 SIRCR_1 ECMR0 ECSR0 ECSIPR0 PIR0 Module*1 SCIF SIOF Bus*2 P P P P P P P P P P P P P P P P P P P P P P P P P P P Address H'A441 0024 H'A442 0000 H'A442 0002 H'A442 0004 H'A442 0006 H'A442 0008 H'A442 000C H'A442 0010 H'A442 0014 H'A442 0016 H'A442 0020 H'A442 0024 H'A442 0028 H'A442 002C H'A443 0000 H'A443 0002 H'A443 0004 H'A443 0006 H'A443 0008 H'A443 000C H'A443 0010 H'A443 0014 H'A443 0016 H'A443 0020 H'A443 0024 H'A443 0028 H'A443 002C H'A700 0160 H'A700 0164 H'A700 0168 H'A700 016C Access Size Size (bit) (bit)*3 16 16 16 16 16 16 16 16 16 16 32 32 32 32 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 16 16 16 16 16 16 16 16 16 16 32 32 32 32 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 EtherC (MAC-0) I I I I Rev. 1.00 Dec. 27, 2005 Page 813 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation MAHR0 MALR0 RFLR0 PSR0 TROCR0 CDCR0 LCCR0 CNDCR0 CEFCR0 FRECR0 TSFRCR0 TLFRCR0 RFCR0 MAFCR0 IPGR0 ECMR1 ECSR1 ECSIPR1 PIR1 MAHR1 MALR1 RFLR1 PSR1 TROCR1 CDCR1 LCCR1 CNDCR1 CEFCR1 FRECR1 TSFRCR1 Module*1 EtherC (MAC-0) Bus*2 I I I I I I I I I I I I I I I Address H'A700 0170 H'A700 0174 H'A700 0178 H'A700 017C H'A700 0180 H'A700 0184 H'A700 0188 H'A700 018C H'A700 0194 H'A700 0198 H'A700 019C H'A700 01A0 H'A700 01A4 H'A700 01A8 H'A700 01B4 H'A700 0560 H'A700 0564 H'A700 0568 H'A700 056C H'A700 0570 H'A700 0574 H'A700 0578 H'A700 057C H'A700 0580 H'A700 0584 H'A700 0588 H'A700 058C H'A700 0594 H'A700 0598 H'A700 059C Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 EtherC (MAC-1) I I I I I I I I I I I I I I I Rev. 1.00 Dec. 27, 2005 Page 814 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation TLFRCR1 RFCR1 MAFCR1 IPGR1 ARSTR TSU_CTRST TSU_FWEN0 TSU_FWEN1 TSU_FCM TSU_BSYSL0 TSU_BSYSL1 TSU_PRISL0 TSU_PRISL1 TSU_FWSL0 TSU_FWSL1 TSU_FWSLC TSU_QTAGM0 TSU_QTAGM1 TSU_ADQT0 TSU_ADQT1 TSU_FWSR TSU_FWINMK TSU_ADSBSY TSU_TEN TSU_POST1 TSU_POST2 TSU_POST3 TSU_POST4 TXNLCR0 TXALCR0 Module*1 EtherC (MAC-1) Bus*2 I I I I Address H'A700 05A0 H'A700 05A4 H'A700 05A8 H'A700 05B4 H'A700 0800 H'A700 0804 H'A700 0810 H'A700 0814 H'A700 0818 H'A700 0820 H'A700 0824 H'A700 0828 H'A700 082C H'A700 0830 H'A700 0834 H'A700 0838 H'A700 0840 H'A700 0844 H'A700 0848 H'A700 084C H'A700 0850 H'A700 0854 H'A700 0860 H'A700 0864 H'A700 0870 H'A700 0874 H'A700 0878 H'A700 087C H'A700 0880 H'A700 0884 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 EtherC EtherC (TSU) I I I I I I I I I I I I I I I I I I I I I I I I I I Rev. 1.00 Dec. 27, 2005 Page 815 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation RXNLCR0 RXALCR0 FWNLCR0 FWALCR0 TXNLCR1 TXALCR1 RXNLCR1 RXALCR1 FWNLCR1 FWALCR1 TSU_ADRH0 TSU_ADRL0 TSU_ADRH1 TSU_ADRL1 TSU_ADRH2 TSU_ADRL2 TSU_ADRH3 TSU_ADRL3 TSU_ADRH4 TSU_ADRL4 TSU_ADRH5 TSU_ADRL5 TSU_ADRH6 TSU_ADRL6 TSU_ADRH7 TSU_ADRL7 TSU_ADRH8 TSU_ADRL8 TSU_ADRH9 TSU_ADRL9 TSU_ADRH10 Module*1 Bus*2 Address H'A700 0888 H'A700 088C H'A700 0890 H'A700 0894 H'A700 08A0 H'A700 08A4 H'A700 08A8 H'A700 08AC H'A700 08B0 H'A700 08B4 H'A700 0900 H'A700 0904 H'A700 0908 H'A700 090C H'A700 0910 H'A700 0914 H'A700 0918 H'A700 091C H'A700 0920 H'A700 0924 H'A700 0928 H'A700 092C H'A700 0930 H'A700 0934 H'A700 0938 H'A700 093C H'A700 0940 H'A700 0944 H'A700 0948 H'A700 094C H'A700 0950 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 EtherC (TSU) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Rev. 1.00 Dec. 27, 2005 Page 816 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation TSU_ADRL10 TSU_ADRH11 TSU_ADRL11 TSU_ADRH12 TSU_ADRL12 TSU_ADRH13 TSU_ADRL13 TSU_ADRH14 TSU_ADRL14 TSU_ADRH15 TSU_ADRL15 TSU_ADRH16 TSU_ADRL16 TSU_ADRH17 TSU_ADRL17 TSU_ADRH18 TSU_ADRL18 TSU_ADRH19 TSU_ADRL19 TSU_ADRH20 TSU_ADRL20 TSU_ADRH21 TSU_ADRL21 TSU_ADRH22 TSU_ADRL22 TSU_ADRH23 TSU_ADRL23 TSU_ADRH24 TSU_ADRL24 TSU_ADRH25 TSU_ADRL25 Module*1 Bus*2 Address H'A700 0954 H'A700 0958 H'A700 095C H'A700 0960 H'A700 0964 H'A700 0968 H'A700 096C H'A700 0970 H'A700 0974 H'A700 0978 H'A700 097C H'A700 0980 H'A700 0984 H'A700 0988 H'A700 098C H'A700 0990 H'A700 0994 H'A700 0998 H'A700 099C H'A700 09A0 H'A700 09A4 H'A700 09A8 H'A700 09AC H'A700 09B0 H'A700 09B4 H'A700 09B8 H'A700 09BC H'A700 09C0 H'A700 09C4 H'A700 09C8 H'A700 09CC Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 EtherC (TSU) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Rev. 1.00 Dec. 27, 2005 Page 817 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation TSU_ADRH26 TSU_ADRL26 TSU_ADRH27 TSU_ADRL27 TSU_ADRH28 TSU_ADRL28 TSU_ADRH29 TSU_ADRL29 TSU_ADRH30 TSU_ADRL30 TSU_ADRH31 TSU_ADRL31 EDMR0 EDTRR0 EDRRR0 TDLAR0 RDLAR0 EESR0 EESIPR0 TRSCER0 RMFCR0 TFTR0 FDR0 RMCR0 EDOCR0 FCFTR0 TRIMD0 RBWAR0 RDFAR0 TBRAR0 TDFAR0 Module*1 Bus*2 Address H'A700 09D0 H'A700 09D4 H'A700 09D8 H'A700 09DC H'A700 09E0 H'A700 09E4 H'A700 09E8 H'A700 09EC H'A700 09F0 H'A700 09F4 H'A700 09F8 H'A700 09FC H'A700 0000 H'A700 0004 H'A700 0008 H'A700 000C H'A700 0010 H'A700 0014 H'A700 0018 H'A700 001C H'A700 0020 H'A700 0024 H'A700 0028 H'A700 002C H'A700 0030 H'A700 0034 H'A700 003C H'A700 0040 H'A700 0044 H'A700 004C H'A700 0050 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 EtherC (TSU) I I I I I I I I I I I I E-DMAC0 I I I I I I I I I I I I I I I I I I I Rev. 1.00 Dec. 27, 2005 Page 818 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation EDMR1 EDTRR1 EDRRR1 TDLAR1 RDLAR1 EESR1 EESIPR1 TRSCER1 RMFCR1 TFTR1 FDR1 RMCR1 EDOCR1 FCFTR1 TRIMD1 RBWAR1 RDFAR1 TBRAR1 TDFAR1 PACR PBCR PCCR PETCR PADR PBDR PCDR Module*1 E-DMAC1 Bus*2 I I I I I I I I I I I I I I I I I I I Address H'A700 0400 H'A700 0404 H'A700 0408 H'A700 040C H'A700 0410 H'A700 0414 H'A700 0418 H'A700 041C H'A700 0420 H'A700 0424 H'A700 0428 H'A700 042C H'A700 0430 H'A700 0434 H'A700 043C H'A700 0440 H'A700 0444 H'A700 044C H'A700 0450 H'A405 0100 H'A405 0102 H'A405 0104 H'A405 0106 H'A405 0120 H'A405 0122 H'A405 0124 Access Size Size (bit) (bit)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 8 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 8 8 8 PFC P P P P I/O port P P P Rev. 1.00 Dec. 27, 2005 Page 819 of 932 REJ09B0269-0100 Section 23 List of Registers Abbreviation SDIR SDID/SDIDH SDIDL Module*1 H-UDI Bus*2 P P P Address H'A410 0200 H'A410 0214 H'A410 0216 Access Size Size (bit) (bit)*3 16 32/16 16 16 32/16 16 Notes: 1. Module: MMU: Memory Management Unit INTC: Interrupt Controller UBC: User Break Controller CPG: Clock Pulse Generator BSC: Bus State Controller DMAC: Direct Memory Access Controller TMU: Timer Unit RTC: Realtime Clock SCIF0: Serial Communication Interface with FIFO 0 SCIF1: Serial Communication Interface with FIFO 1 SIOF0: Serial I/O with FIFO 0 SIOF1: Serial I/O with FIFO 1 EtherC (MAC-0): Ethernet Controller 0 EtherC (MAC-1): Ethernet Controller 1 EtherC (TSU): Transfer Unit for Ethernet Controller E-DMAC0: Ethernet Controller Direct Memory Access Controller 0 E-DMAC1: Ethernet Controller Direct Memory Access Controller 1 PFC: Pin Function Controller H-UDI: User Debugging Interface 2. Bus: L: Connected to the CPU, DSP, CCN, Cache, MMU, and UBC. I: Connected to the BSC, CCN, Cache, DMAC, E-DMAC0, and E-DMAC1. P: Connected to the BSC and peripheral modules (RTC, TMU, SCIF0, SCIF1, SIOF0, SIOF1, DMAC, PORT, INTC, H-UDI, CPG). 3. The access size indicates the size when accessing (read/write) the control registers. If an access is performed in the different size as shown above, the result is not correct data. 4. 16 bits when writing and 8 bits when reading. Rev. 1.00 Dec. 27, 2005 Page 820 of 932 REJ09B0269-0100 Section 23 List of Registers 23.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation Bit 31/ 23/15/7 TRA Bit 30/ 22/14/6 TRA Bit 29/ 21/13/5 TRA Bit 28/ 20/12/4 TRA Bit 27/ 19/11/3 TRA Bit 26/ 18/10/2 TRA Bit 25/ 17/9/1 TRA Bit 24/ 16/8/0 TRA Module Exception handl-ing TRA EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT EXPEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT INTEVT2 INTEVT2 INTEVT2 INTEVT2 INTEVT2 TEA TEA TEA TEA VPN VPN ASID MMU INTEVT2 INTEVT2 INTEVT2 INTEVT2 INTEVT2 INTEVT2 TEA TEA TEA TEA TEA TEA TEA TEA TEA VPN VPN VPN ASID TEA TEA TEA TEA VPN VPN VPN ASID TEA TEA TEA TEA VPN VPN VPN ASID TEA TEA TEA TEA VPN VPN VPN ASID TEA TEA TEA TEA VPN VPN VPN ASID TEA TEA TEA TEA VPN VPN ASID PTEH VPN VPN VPN ASID Rev. 1.00 Dec. 27, 2005 Page 821 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation Bit 31/ 23/15/7 PPN PPN Bit 30/ 22/14/6 PPN PPN PR Bit 29/ 21/13/5 PPN PPN PR Bit 28/ 20/12/4 PPN PPN PPN SZ Bit 27/ 19/11/3 PPN PPN PPN C Bit 26/ 18/10/2 PPN PPN PPN D Bit 25/ 17/9/1 PPN PPN SH Bit 24/ 16/8/0 PPN PPN V Module MMU PTEL TTB MMUCR CSIZE6 RC CSIZE5 RC CSIZE4 CF CSIZE3 TMU1 RTC REF TF CB CSIZE2 IX WT SV AT CE LE Cache CCR1 CCR2 W3LOAD W3LOCK W2LOAD W2LOCK CSIZE1 CSIZE0 INTC CCR3 CSIZE7 IPRA TMU0 TMU2 IPRB WDT IRQ2 IRQ0 IPRC IRQ3 IRQ1 Rev. 1.00 Dec. 27, 2005 Page 822 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation Bit 31/ 23/15/7 IRQ5 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 IRQ4 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module INTC IPRD IPRE DMAC(1) SCIF1 SCIF0 DMAC(2) E-DMAC(2) SIOF0 IRQ50S IRQ10S IRQ2R DEI2R BRI1R CUIR EINT2R BAA26 BAA18 BAA10 BAA2 IRQ41S IRQ01S IRQ1R DEI1R RXI1R PRIR EINT1R BAA25 BAA17 BAA9 BAA1 NMIE IRQ40S IRQ00S IRQ0R DEI0R ERI1R ATIR RCMIR EINT0R BAA24 BAA16 BAA8 BAA0 UBC IPRF E-DMAC(1) E-DMAC(3) IPRG IPRH IPRI SIOF1 ICR0 NMIL IRQLVL IRQ51S IRQ11S IRQ3R DEI3R TXI1R ITIR BAA27 BAA19 BAA11 BAA3 ICR1 MAI BLMASK IRLSEN IRQ21S IRQ5R RXI0R TUNI1R DEI5R TXI0R TXI1R BAA29 BAA21 BAA13 BAA5 IRQ20S IRQ4R ERI0R TUNI0R DEI4R ERI0R ERI1R BAA28 BAA20 BAA12 BAA4 IRQ31S IRQ30S IRR0 IRR1 IRR2 IRR3 IRR4 IRR5 IRR7 IRR8 BARA TXI0R CCI0R CCI1R BAA31 BAA23 BAA15 BAA7 BRI0R TUNI2R RXI0R RXI1R BAA30 BAA22 BAA14 BAA6 Rev. 1.00 Dec. 27, 2005 Page 823 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation Bit 31/ 23/15/7 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module BAMRA BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 UBC BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA7 BAMA6 CDA0 BAB30 BAB22 BAB14 BAB6 BAMA5 IDA1 BAB29 BAB21 BAB13 BAB5 BAMA4 IDA0 BAB28 BAB20 BAB12 BAB4 BAMA3 RWA1 BAB27 BAB19 BAB11 BAB3 BAMA2 RWA0 BAB26 BAB18 BAB10 BAB2 BAMA1 SZA1 BAB25 BAB17 BAB9 BAB1 BAMA8 BAMA0 SZA0 BAB24 BAB16 BAB8 BAB0 BBRA CDA1 BARB BAB31 BAB23 BAB15 BAB7 BAMRB BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB7 BAMB6 BDB30 BDB22 BDB14 BDB6 BAMB5 BDB29 BDB21 BDB13 BDB5 BAMB4 BDB28 BDB20 BDB12 BDB4 BAMB3 BDB27 BDB19 BDB11 BDB3 BAMB2 BDB26 BDB18 BDB10 BDB2 BAMB1 BDB25 BDB17 BDB9 BDB1 BAMB8 BAMB0 BDB24 BDB16 BDB8 BDB0 BDRB BDB31 BDB23 BDB15 BDB7 BDMRB BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB7 BDMB6 CDB0 BDMB5 IDB1 BASMA BDMB4 IDB0 BASMB BDMB3 RWB1 BDMB2 RWB0 PCBA BET10 BET2 BDMB1 XYE SZB1 BET9 BET1 BDMB8 BDMB0 XYS SZB0 ETBE BET8 BET0 BBRB CDB1 BRCR SCMFCA SCMFCB SCMFDA SCMFDB PCTE DBEB PCBB BET6 BET5 BET4 SEQ BET11 BET3 BETR BET7 Rev. 1.00 Dec. 27, 2005 Page 824 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation Bit 31/ 23/15/7 SVF BSA23 BSA15 BSA7 Bit 30/ 22/14/6 BSA22 BSA14 BSA6 BDA22 BDA14 BDA6 BASA6 BASB6 MSTP9 Bit 29/ 21/13/5 BSA21 BSA13 BSA5 BDA21 BDA13 BDA5 BASA5 BASB5 MSTP8 IFC1 Bit 28/ 20/12/4 BSA20 BSA12 BSA4 BDA20 BDA12 BDA4 BASA4 BASB4 MSTP7 CKOEN IFC0 Bit 27/ 19/11/3 BSA27 BSA19 BSA11 BSA3 BDA27 BDA19 BDA11 BDA3 BASA3 BASB3 MSTP6 MSTP33 Bit 26/ 18/10/2 BSA26 BSA18 BSA10 BSA2 BDA26 BDA18 BDA10 BDA2 BASA2 BASB2 MSTP2 MSTP5 MEST32 PFC2 Bit 25/ 17/9/1 BSA25 BSA17 BSA9 BSA1 BDA25 BDA17 BDA9 BDA1 BASA1 BASB1 MSTP1 MSTP31 STC1 PFC1 Bit 24/ 16/8/0 BSA24 BSA16 BSA8 BSA0 BDA24 BDA16 BDA8 BDA0 BASA0 BASB0 MSTP3 MSTP30 STC0 PFC0 Module UBC BRSR BRDR DVF BDA23 BDA15 BDA7 BASRA BASRB STBCR STBCR2 STBCR3 FRQCR BASA7 BASB7 STBY MSTP10 Powerdown mode CPG WTCNT WTCSR CMNCR TME WT/IT RSTS WOVF MAP IOVF BLOCK ENDIAN CKS2 CKS1 CKS0 BSC WAITSEL BSD DPRTY1 DPRTY0 DMAIW2 CK2DRV HIZMEM HIZCNT DMAIW1 DMAIW0 DMAIWA CSnBCR (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRRS1 BSZ0 IWRRS0 IWRWS1 IWRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 TYPE3 TYPE2 TYPE1 TYPE0 BSZ1 Rev. 1.00 Dec. 27, 2005 Page 825 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation CS0WCR* 1 Bit 31/ 23/15/7 WR0 W0 W0 Bit 30/ 22/14/6 WM WM WM WM TRP1 WM Bit 29/ 21/13/5 TRP0 Bit 28/ 20/12/4 BAS BEN SW1 BAS BAS TRWL1 Bit 27/ 19/11/3 SW0 TRCD1 TRWL0 Bit 26/ 18/10/2 WR3 W3 W3 WR3 WR3 TRCD0 Bit 25/ 17/9/1 BW1 BW1 WR2 W2 W2 HW1 WR2 WR2 TRC1 Bit 24/ 16/8/0 BW0 BW0 WR1 W1 W1 HW0 WR1 A2CL1 WR1 A3CL1 TRC0 Module BSC CS2WCR* 2 WR0 A2CL0 CS3WCR* 2 CS3WCR* 2 WR0 A3CL0 Rev. 1.00 Dec. 27, 2005 Page 826 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation CS4WCR* 3 Bit 31/ 23/15/7 WR0 PCW0W0 Bit 30/ 22/14/6 WM WM WM TED3 WM WM WM TED3 WM WM Bit 29/ 21/13/5 SA1 TED2 SA1 TED2 Bit 28/ 20/12/4 BAS BEN SW1 SW1 SW1 BAS SA0 SW1 TED1 SW1 BAS SA0 SW1 TED1 Bit 27/ 19/11/3 SW0 SW0 SW0 SW0 TED0 TEH3 SW0 SW0 TED0 TEH3 Bit 26/ 18/10/2 WW2 WR3 PCW3W3 Bit 25/ 17/9/1 WW1 BW1 WR2 PCW2W2 Bit 24/ 16/8/0 WW0 BW0 WR1 PCW1W1 Module BSC WW2 WR3 WW2 WR3 PCW3 TEH2 WR3 WR3 PCW3 TEH2 HW1 HW1 WW1 WR2 HW1 WW1 WR2 PCW2 HW1 TEH1 WR2 HW1 WR2 PCW2 HW1 TEH1 HW0 HW0 WW0 WR1 HW0 WW0 WR1 PCW1 HW0 TEH0 WR1 HW0 WR1 PCW1 HW0 TEH0 CS5A 4 WCR* WR0 CS5BWCR* 5 WR0 PCW0 CS6AWCR* 4 WR0 CS6BWCR* 6 WR0 PCW0 Rev. 1.00 Dec. 27, 2005 Page 827 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation SDCR Bit 31/ 23/15/7 Bit 30/ 22/14/6 CMIE Bit 29/ 21/13/5 DEEP CKS2 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module BSC A2ROW1 A2ROW0 SLOW RFSH RMODE A2COL1 A2COL0 PDOWN BACTV A3COL1 A3COL0 RRC1 RRC0 A3ROW1 A3ROW0 CKS1 CKS0 RRC2 RTCSR CMF RTCNT RTCOR SAR_n (n = 0 to 5) DMAC DAR_n (n = 0 to 5) DMATCR_n (n = 0 to 5) Rev. 1.00 Dec. 27, 2005 Page 828 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation CHCR_n (n = 0, 1) Bit 31/ 23/15/7 DO DM1 DL Bit 30/ 22/14/6 TL DM0 DS DM0 C1MID4 C0MID4 C3MID4 C2MID4 C5MID4 C4MID4 Bit 29/ 21/13/5 SM1 TB SM1 TB C1MID3 C0MID3 C3MID3 C2MID3 C5MID3 C4MID3 UNIE Bit 28/ 20/12/4 SM0 TS1 SM0 TS1 C1MID2 C0MID2 C3MID2 C2MID2 C5MID2 C4MID2 Bit 27/ 19/11/3 RS3 TS0 RS3 TS0 C1MID1 C0MID1 C3MID1 C2MID1 C5MID1 C4MID1 Bit 26/ 18/10/2 RS2 IE RS2 IE AE C1MID0 C0MID0 C3MID0 C2MID0 C5MID0 C4MID0 STR2 TPSC2 Bit 25/ 17/9/1 AM RS1 TE RS1 TE PR1 NMIF C1RID1 C0RID1 C3RID1 C2RID1 C5RID1 C4RID1 STR1 TPSC1 Bit 24/ 16/8/0 AL RS0 DE RS0 DE PR0 DME C1RID0 C0RID0 C3RID0 C2RID0 C5RID0 C4RID0 STR0 UNF TPSC0 Module DMAC CHCR_m (m = 2 to 5) DM1 DMAOR DMARS0 C1MID5 C0MID5 DMARS1 C3MID5 C2MID5 DMARS2 C5MID5 C4MID5 TSTR TCRn (n = 0 to 2) TCORn (n = 0 to 2) TMU TCNTn (n = 0 to 2) Rev. 1.00 Dec. 27, 2005 Page 829 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT Bit 31/ 23/15/7 Bit 30/ 22/14/6 1Hz Bit 29/ 21/13/5 2Hz Bit 28/ 20/12/4 4Hz Bit 27/ 19/11/3 8Hz Bit 26/ 18/10/2 16Hz Bit 25/ 17/9/1 32Hz Bit 24/ 16/8/0 64Hz Module RTC 10-unit of second 10-unit of minute 10-unit of hour 1-unit of second 1-unit of minute 1-unit of hour 1-unit of date Day of week code 10-unit of date 10-unit of 1-unit of month month 100-unit of year 1-unit of year 1-unit of second 1-unit of minute 1-unit of hour 1-unit of date Day of week code 1000-unit of year 10-unit of year RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RYRAR ENB ENB ENB ENB ENB ENB 10-unit of second 10-unit of minute 10-unit of hour 10-unit of date 10-unit of 1-unit of month month 100-unit of year 1-unit of year 1000-unit of year 10-unit of year RCR1 RCR2 RCR3 SCFRDR_n (n = 0, 1) SCFTDR_n (n = 0, 1) SCSMR_n (n = 0, 1) SCSCR_n (n = 0, 1) CF PEF YAEN PES2 PES1 CIE PES0 AIE RTCEN ADJ RESET AF START SCIF C/A TIE CHR RIE PE TE O/E RE STOP REIE CKS1 CKE1 CKS0 CKE0 Rev. 1.00 Dec. 27, 2005 Page 830 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation SCFSR_n (n = 0, 1) SCBRR_n (n = 0, 1) SCFCR_n (n = 0, 1) SCFDR_n (n = 0, 1) SCLSR_n (n = 0, 1) SIMDR_n (n = 0, 1) SISCR_n (n = 0, 1) SITDAR_n (n = 0, 1) SIRDAR_n (n = 0, 1) SICDAR_n (n = 0, 1) SICTR_n (n = 0, 1) SIFCTR_n (n = 0, 1) SISTR_n (n = 0, 1) SIIER_n (n = 0, 1) Bit 31/ 23/15/7 PER3 ER Bit 30/ 22/14/6 PER2 TEND Bit 29/ 21/13/5 PER1 TDFE Bit 28/ 20/12/4 PER0 BRK Bit 27/ 19/11/3 FER3 FER Bit 26/ 18/10/2 FER2 PER Bit 25/ 17/9/1 FER1 RDF Bit 24/ 16/8/0 FER0 DR Module SCIF RTRG1 TRMD1 TXDIZ MSSEL TDLE TDRE RDLE RDRE CD0E CD1E SCKE TFWM2 RFWM2 RTRG0 TRMD0 LSBF MSIMM TLREP FSE TFWM1 RFWM1 TCRDY TTRG1 RCIM TFWM0 RFWM0 TFEMP TTRG0 T4 R4 REDG BRPS4 TFUA4 RFUA4 TDREQ FSERR MCE T3 R3 FL3 BRPS3 TDLA3 TDRA3 RDLA3 RDRA3 CD0A3 CD1A3 TFUA3 RFUA3 TFOVR RSTRG2 RSTRG1 RSTRG0 TFRST T2 R2 FL2 BRPS2 BRDV2 TDLA2 TDRA2 RDLA2 RDRA2 CD0A2 CD1A2 TFUA2 RFUA2 RCRDY TFUDR RFRST T1 R1 FL1 BRPS1 BRDV1 TDLA1 TDRA1 RDLA1 RDRA1 CD0A1 CD1A1 TXE TXRST TFUA1 RFUA1 RFFUL RFUDR LOOP T0 R0 ORER FL0 BRPS0 BRDV0 TDLA0 TDRA0 RDLA0 RDRA0 CD0A0 CD1A0 RXE RXRST TFUA0 RFUA0 RDREQ RFOVR SIOF TCRDYE TFEMPE TDREQE RCRDYE RFFULE RDREQE FSERRE TFOVRE TFUDRE RFUDRE RFOVRE Rev. 1.00 Dec. 27, 2005 Page 831 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation SITDR_n (n = 0, 1) Bit 31/ 23/15/7 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 SITDL8 SITDL0 SITDR8 SITDR0 SIRDL8 SIRDL0 SIRDR8 SIRDR0 SITC08 SITC00 SITC18 SITC10 SIRC08 SIRC00 SIRC18 SIRC10 ARST PRM ICD Module SIOF SITDL15 SITDL14 SITDL13 SITDL12 SITDL11 SITDL10 SITDL9 SITDL7 SITDL6 SITDL5 SITDL4 SITDL3 SITDL2 SITDL1 SITDR15 SITDR14 SITDR13 SITDR12 SITDR11 SITDR10 SITDR9 SITDR7 SIRDR_n (n = 0, 1) SITDR6 SITDR5 SITDR4 SITDR3 SITDR2 SITDR1 SIRDL15 SIRDL14 SIRDL13 SIRDL12 SIRDL11 SIRDL10 SIRDL9 SIRDL7 SIRDL6 SIRDL5 SIRDL4 SIRDL3 SIRDL2 SIRDL1 SIRDR15 SIRDR14 SIRDR13 SIRDR12 SIRDR11 SIRDR10 SIRDR9 SIRDR7 SITCR_n (n = 0, 1) SIRDR6 SIRDR5 SIRDR4 SIRDR3 SIRDR2 SIRDR1 SITC015 SITC014 SITC013 SITC012 SITC011 SITC010 SITC09 SITC07 SITC06 SITC05 SITC04 SITC03 SITC02 SITC01 SITC115 SITC114 SITC113 SITC112 SITC111 SITC110 SITC19 SITC17 SIRCR_n (n = 0, 1) SITC16 SITC15 SITC14 SITC13 SITC12 SITC11 SIRC015 SIRC014 SIRC013 SIRC012 SIRC011 SIRC010 SIRC09 SIRC07 SIRC06 SIRC05 SIRC04 SIRC03 SIRC02 SIRC01 SIRC115 SIRC114 SIRC113 SIRC112 SIRC111 SIRC110 SIRC19 SIRC17 ARSTR ECMRn (n = 0, 1) ECSRn (n = 0, 1) SIRC16 RE SIRC15 MCT TE SIRC14 PRCEF SIRC13 ILB SIRC12 ELB LCHNG SIRC11 MPDE DM MPD EtherC Rev. 1.00 Dec. 27, 2005 Page 832 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation ECSIPRn (n = 0, 1) Bit 31/ 23/15/7 Bit 30/ 22/14/6 MA46 MA38 MA30 MA22 MA14 MA6 RFL6 Bit 29/ 21/13/5 MA45 MA37 MA29 MA21 MA13 MA5 RFL5 Bit 28/ 20/12/4 MA44 MA36 MA28 MA20 MA12 MA4 RFL4 Bit 27/ 19/11/3 MDI MA43 MA35 MA27 MA19 MA11 MA3 RFL11 RFL3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 ICDIP MDC MA40 MA32 MA24 MA16 MA8 MA0 RFL8 RFL0 LMON Module EtherC LCHNGIP MPDIP PIRn (n = 0, 1) MDO MA42 MA34 MA26 MA18 MA10 MA2 RFL10 RFL2 MMD MA41 MA33 MA25 MA17 MA9 MA1 RFL9 RFL1 MAHRn (n = 0, 1) MA47 MA39 MA31 MA23 MALRn (n = 0, 1) MA15 MA7 RFLRn (n = 0, 1) RFL7 PSRn (n = 0, 1) TROCRn (n = 0, 1) TROC31 TROC30 TROC29 TROC28 TROC27 TROC26 TROC25 TROC24 TROC23 TROC22 TROC21 TROC20 TROC19 TROC18 TROC17 TROC16 TROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9 TROC7 TROC6 TROC5 TROC4 TROC3 TROC2 TROC1 TROC8 TROC0 Rev. 1.00 Dec. 27, 2005 Page 833 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation CDCRn (n = 0, 1) Bit 31/ 23/15/7 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module COSDC31 COSDC30 COSDC29 COSDC28 COSDC27 COSDC26 COSDC25 COSDC24 EtherC COSDC23 COSDC22 COSDC21 COSDC20 COSDC19 COSDC18 COSDC17 COSDC16 COSDC15 COSDC14 COSDC13 COSDC12 COSDC11 COSDC10 COSDC9 COSDC8 COSDC7 COSDC6 COSDC5 COSDC4 COSDC3 COSDC2 COSDC1 COSDC0 LCCRn (n = 0, 1) LCC31 LCC23 LCC15 LCC7 CNDCRn (n = 0, 1) LCC30 LCC22 LCC14 LCC6 LCC29 LCC21 LCC13 LCC5 LCC28 LCC20 LCC12 LCC4 LCC27 LCC19 LCC11 LCC3 LCC26 LCC18 LCC10 LCC2 LCC25 LCC17 LCC9 LCC1 LCC24 LCC16 LCC8 LCC0 CNDC31 CNDC30 CNDC29 CNDC28 CNDC27 CNDC26 CNDC25 CNDC24 CNDC23 CNDC22 CNDC21 CNDC20 CNDC19 CNDC18 CNDC17 CNDC16 CNDC15 CNDC14 CNDC13 CNDC12 CNDC11 CNDC10 CNDC9 CNDC7 CNDC6 CNDC5 CNDC4 CNDC3 CNDC2 CEFC26 CEFC18 CEFC10 CEFC2 FREC26 FREC18 FREC10 FREC2 TSFC26 TSFC18 TSFC10 TSFC2 TLFC26 TLFC18 TLFC10 TLFC2 CNDC1 CNDC8 CNDC0 CEFCRn (n = 0, 1) CEFC31 CEFC30 CEFC23 CEFC22 CEFC15 CEFC14 CEFC7 CEFC6 CEFC29 CEFC28 CEFC27 CEFC21 CEFC20 CEFC19 CEFC13 CEFC12 CEFC11 CEFC5 CEFC4 CEFC3 CEFC25 CEFC24 CEFC17 CEFC16 CEFC9 CEFC1 CEFC8 CEFC0 FRECRn (n = 0, 1) FREC31 FREC30 FREC23 FREC22 FREC15 FREC14 FREC7 FREC6 FREC29 FREC28 FREC27 FREC21 FREC20 FREC19 FREC13 FREC12 FREC11 FREC5 TSFC29 TSFC21 TSFC13 TSFC5 TLFC29 TLFC21 TLFC13 TLFC5 FREC4 TSFC28 TSFC20 TSFC12 TSFC4 TLFC28 TLFC20 TLFC12 TLFC4 FREC3 TSFC27 TSFC19 TSFC11 TSFC3 TLFC27 TLFC19 TLFC11 TLFC3 FREC25 FREC24 FREC17 FREC16 FREC9 FREC1 TSFC25 TSFC17 TSFC9 TSFC1 TLFC25 TLFC17 TLFC9 TLFC1 FREC8 FREC0 TSFC24 TSFC16 TSFC8 TSFC0 TLFC24 TLFC16 TLFC8 TLFC0 TSFRCRn (n = 0, 1) TSFC31 TSFC30 TSFC23 TSFC22 TSFC15 TSFC14 TSFC7 TSFC6 TLFC30 TLFC22 TLFC14 TLFC6 TLFRCRn (n = 0, 1) TLFC31 TLFC23 TLFC15 TLFC7 Rev. 1.00 Dec. 27, 2005 Page 834 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation RFCRn (n = 0, 1) Bit 31/ 23/15/7 RFC31 RFC23 RFC15 RFC7 Bit 30/ 22/14/6 RFC30 RFC22 RFC14 RFC6 Bit 29/ 21/13/5 RFC29 RFC21 RFC13 RFC5 Bit 28/ 20/12/4 RFC28 RFC20 RFC12 RFC4 Bit 27/ 19/11/3 RFC27 RFC19 RFC11 RFC3 Bit 26/ 18/10/2 RFC26 RFC18 RFC10 RFC2 Bit 25/ 17/9/1 RFC25 RFC17 RFC9 RFC1 Bit 24/ 16/8/0 RFC24 RFC16 RFC8 RFC0 Module EtherC MAFCRn (n = 0, 1) MAFC31 MAFC30 MAFC29 MAFC28 MAFC27 MAFC26 MAFC25 MAFC24 MAFC23 MAFC22 MAFC21 MAFC20 MAFC19 MAFC18 MAFC17 MAFC16 MAFC15 MAFC14 MAFC13 MAFC12 MAFC11 MAFC10 MAFC9 MAFC7 MAFC6 MAFC5 MAFC4 IPG4 MAFC3 IPG3 MAFC2 IPG2 FCM2 MAFC1 IPG1 FCM1 MAFC8 MAFC0 IPG0 CTRST FCM0 IPGRn (n = 0, 1) TSU_ CTRST TSU_ FWEN0 FWEN0 TSU_ FWEN1 FWEN1 TSU_FCM Rev. 1.00 Dec. 27, 2005 Page 835 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TSU_ BSYSL0 Bit 31/ 23/15/7 Bit 30/ 22/14/6 PRIMD02 Bit 29/ 21/13/5 BSYSL05 Bit 28/ 20/12/4 BSYSL04 Bit 27/ 19/11/3 BSYSL03 Bit 26/ 18/10/2 BSYSL02 Bit 25/ 17/9/1 BSYSL01 Bit 24/ 16/8/0 BSYSL00 Module EtherC TSU_ BSYSL1 BSYSL15 BSYSL14 BSYSL13 BSYSL12 BSYSL11 BSYSL10 TSU_ PRISL0 PRIMD01 PRIMD00 PRISL07 PRISL06 PRISL05 PRISL04 PRISL03 PRISL02 PRISL01 PRISL00 TSU_ PRISL1 PRIMD12 PRIMD11 PRIMD10 PRISL17 PRISL16 PRISL15 PRISL14 PRISL13 PRISL12 PRISL11 PRISL10 TSU_ FWSL0 TSU_ FWSL1 TSU_ FWSLC CAMSEL03 FW40 FW41 FW30 FW31 FW20 FW21 FW10 FW11 POSTENU POSTENL CAMSEL02 CAMSEL01 CAMSEL00 CAMSEL13 CAMSEL12 CAMSEL11 CAMSEL10 Rev. 1.00 Dec. 27, 2005 Page 836 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TSU_ QTAGM0 Bit 31/ 23/15/7 Bit 30/ 22/14/6 RBSY0 RBSY1 Bit 29/ 21/13/5 Bit 28/ 20/12/4 RINT50 RINT51 Bit 27/ 19/11/3 TINT40 RINT40 TINT41 RINT41 Bit 26/ 18/10/2 TINT30 RINT30 TINT31 RINT31 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module EtherC QTAGM01 QTAGM00 TSU_ QTAGM1 QTAGM11 QTAGM10 TSU_ FWSR OVF0 OVF1 TINT20 RINT20 TINT21 RINT21 TINT10 RINT10 TINT11 RINT11 TSU_ FWINMK OVFM0 OVFM1 TINTM40 TINTM30 TINTM20 TINTM10 RBSYM0 RINTM50 RINTM40 RINTM30 RINTM20 RINTM10 TINTM41 TINTM31 TINTM21 TINTM11 RBSYM1 RINTM51 RINTM41 RINTM31 RINTM21 RINTM11 QTAG026 QTAG018 QTAG010 QTAG002 QTAG126 QTAG118 QTAG110 QTAG102 QTAG025 QTAG017 QTAG009 QTAG001 QTAG125 QTAG117 QTAG109 QTAG101 QTAG024 QTAG016 QTAG008 QTAG000 QTAG124 QTAG116 QTAG108 QTAG100 TSU_ ADQT0 QTAG031 QTAG030 QTAG029 QTAG028 QTAG027 QTAG023 QTAG022 QTAG021 QTAG020 QTAG019 QTAG015 QTAG014 QTAG013 QTAG011 QTAG007 QTAG006 QTAG005 QTAG004 QTAG003 TSU_ ADQT1 QTAG131 QTAG130 QTAG129 QTAG128 QTAG127 QTAG123 QTAG122 QTAG121 QTAG120 QTAG119 QTAG115 QTAG114 QTAG113 QTAG111 QTAG107 QTAG106 QTAG105 QTAG104 QTAG103 TSU_ ADSBSY ADSBSY Rev. 1.00 Dec. 27, 2005 Page 837 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TSU_TEN Bit 31/ 23/15/7 TEN0 TEN8 TEN16 TEN24 Bit 30/ 22/14/6 TEN1 TEN9 TEN17 TEN25 POST02 POST22 POST42 POST62 POST82 POST102 POST122 POST142 POST162 POST182 POST202 POST222 POST242 POST262 POST282 POST302 Bit 29/ 21/13/5 TEN2 TEN10 TEN18 TEN26 POST01 POST21 POST41 POST61 POST81 POST101 POST121 POST141 POST161 POST181 POST201 POST221 POST241 POST261 POST281 POST301 Bit 28/ 20/12/4 TEN3 TEN11 TEN19 TEN27 Bit 27/ 19/11/3 TEN4 TEN12 TEN20 TEN28 Bit 26/ 18/10/2 TEN5 TEN13 TEN21 TEN29 POST12 POST32 POST52 POST72 POST92 POST112 POST132 POST152 POST172 POST192 POST212 POST232 POST252 POST272 POST292 POST312 Bit 25/ 17/9/1 TEN6 TEN14 TEN22 TEN30 POST11 POST31 POST51 POST71 POST91 POST111 POST131 POST151 POST171 POST191 POST211 POST231 POST251 POST271 POST291 POST311 Bit 24/ 16/8/0 TEN7 TEN15 TEN23 TEN31 POST10 POST30 POST50 POST70 POST90 POST110 POST130 POST150 POST170 POST190 POST210 POST230 POST250 POST270 POST290 POST310 Module EtherC TSU_ POST1 POST03 POST23 POST43 POST63 POST00 POST13 POST20 POST33 POST40 POST53 POST60 POST73 POST80 POST93 POST100 POST120 POST140 POST160 POST180 POST200 POST220 POST240 POST260 POST280 POST300 POST113 POST133 POST153 POST173 POST193 POST213 POST233 POST253 POST273 POST293 POST313 TSU_ POST2 POST83 POST103 POST123 POST143 TSU_ POST3 POST163 POST183 POST203 POST223 TSU_ POST4 POST243 POST263 POST283 POST303 TSU_ ADRHn31 ADRHn30 ADRHn29 ADRHn28 ADRHn27 ADRHn26 ADRHn25 ADRHn24 ADRHn ADRHn23 ADRHn22 ADRHn21 ADRHn20 ADRHn19 ADRHn18 ADRHn17 ADRHn16 (n = 0 to 31) ADRHn15 ADRHn14 ADRHn13 ADRHn12 ADRHn11 ADRHn10 ADRHn9 ADRHn8 ADRHn7 ADRHn6 ADRHn5 ADRHn4 ADRHn3 ADRHn2 ADRHn1 ADRHn0 TSU_ ADRLn (n = 0 to 31) ADRLn15 ADRLn14 ADRLn13 ADRLn12 ADRLn11 ADRLn10 ADRLn9 ADRLn1 ADRLn8 ADRLn0 ADRLn7 ADRLn6 ADRLn5 ADRLn4 ADRLn3 ADRLn2 Rev. 1.00 Dec. 27, 2005 Page 838 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TXNLCR0 Bit 31/ 23/15/7 NTC031 NTC023 NTC015 NTC007 Bit 30/ 22/14/6 NTC030 NTC022 NTC014 NTC006 TC030 TC022 TC014 TC006 NRC030 NRC022 NRC014 NRC006 RC030 RC022 RC014 RC006 NFC030 NFC022 NFC014 NFC006 FC030 FC022 FC014 FC006 NTC130 NTC122 NTC114 NTC106 Bit 29/ 21/13/5 NTC029 NTC021 NTC013 NTC005 TC029 TC021 TC013 TC005 NRC029 NRC021 NRC013 NRC005 RC029 RC021 RC013 RC005 NFC029 NFC021 NFC013 NFC005 FC029 FC021 FC013 FC005 NTC129 NTC121 NTC113 NTC105 Bit 28/ 20/12/4 NTC028 NTC020 NTC012 NTC004 TC028 TC020 TC012 TC004 NRC028 NRC020 NRC012 NRC004 RC028 RC020 RC012 RC004 NFC028 NFC020 NFC012 NFC004 FC028 FC020 FC012 FC004 NTC128 NTC120 NTC112 NTC104 Bit 27/ 19/11/3 NTC027 NTC019 NTC011 NTC003 TC027 TC019 TC011 TC003 NRC027 NRC019 NRC011 NRC003 RC027 RC019 RC011 RC003 NFC027 NFC019 NFC011 NFC003 FC027 FC019 FC011 FC003 NTC127 NTC119 NTC111 NTC103 Bit 26/ 18/10/2 NTC026 NTC018 NTC010 NTC002 TC026 TC018 TC010 TC002 NRC026 NRC018 NRC010 NRC002 RC026 RC018 RC010 RC002 NFC026 NFC018 NFC010 NFC002 FC026 FC018 FC010 FC002 NTC126 NTC118 NTC110 NTC102 Bit 25/ 17/9/1 NTC025 NTC017 NTC009 NTC001 TC025 TC017 TC009 TC001 NRC025 NRC017 NRC009 Bit 24/ 16/8/0 NTC024 NTC016 NTC008 NTC000 Module EtherC TXALCR0 TC031 TC023 TC015 TC007 TC024 TC016 TC008 TC000 NRC024 NRC016 NRC008 RXNLCR0 NRC031 NRC023 NRC015 NRC007 NRC001 NRC000 RC025 RC017 RC009 RC001 NFC025 NFC017 NFC009 NFC001 FC025 FC017 FC009 FC001 NTC125 NTC117 NTC109 NTC101 RC024 RC016 RC008 RC000 NFC024 NFC016 NFC008 NFC000 FC024 FC016 FC008 FC000 NTC124 NTC116 NTC108 NTC100 RXALCR0 RC031 RC023 RC015 RC007 FWNLCR0 NFC031 NFC023 NFC015 NFC007 FWALCR0 FC031 FC023 FC015 FC007 TXNLCR1 NTC131 NTC123 NTC115 NTC107 Rev. 1.00 Dec. 27, 2005 Page 839 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TXALCR1 Bit 31/ 23/15/7 TC131 TC123 TC115 TC107 Bit 30/ 22/14/6 TC130 TC122 TC114 TC106 Bit 29/ 21/13/5 TC129 TC121 TC113 TC105 Bit 28/ 20/12/4 TC128 TC120 TC112 TC104 Bit 27/ 19/11/3 TC127 TC119 TC111 TC103 Bit 26/ 18/10/2 TC126 TC118 TC110 TC102 Bit 25/ 17/9/1 TC125 TC117 TC109 TC101 Bit 24/ 16/8/0 TC124 TC116 TC108 TC100 Module EtherC RXNLCR1 NRC131 NRC130 NRC129 NRC128 NRC127 NRC126 NRC125 NRC124 NRC123 NRC122 NRC121 NRC120 NRC119 NRC118 NRC117 NRC116 NRC115 NRC114 NRC113 NRC112 NRC111 NRC110 NRC109 NRC108 NRC107 NRC106 NRC105 NRC104 NRC103 NRC102 NRC101 NRC100 RXALCR1 RC131 RC123 RC115 RC107 RC130 RC122 RC114 RC106 NFC130 NFC122 NFC114 NFC106 FC130 FC122 FC114 FC106 RC129 RC121 RC113 RC105 NFC129 NFC121 NFC113 NFC105 FC129 FC121 FC113 FC105 DL1 RC128 RC120 RC112 RC104 NFC128 NFC120 NFC112 NFC104 FC128 FC120 FC112 FC104 DL0 RC127 RC119 RC111 RC103 NFC127 NFC119 NFC111 NFC103 FC127 FC119 FC111 FC103 RC126 RC118 RC110 RC102 NFC126 NFC118 NFC110 NFC102 FC126 FC118 FC110 FC102 RC125 RC117 RC109 RC101 NFC125 NFC117 NFC109 NFC101 FC125 FC117 FC109 FC101 RC124 RC116 RC108 RC100 NFC124 NFC116 NFC108 NFC100 FC124 FC116 FC108 FC100 SWR TR E-DMAC FWNLCR1 NFC131 NFC123 NFC115 NFC107 FWALCR1 FC131 FC123 FC115 FC107 EDMRn (n = 0, 1) EDTRRn (n = 0, 1) Rev. 1.00 Dec. 27, 2005 Page 840 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation EDRRRn (n = 0, 1) Bit 31/ 23/15/7 Bit 30/ 22/14/6 TDLA30 TDLA22 TDLA14 TDLA6 RDLA30 RDLA22 RDLA14 RDLA6 TWB ECI TWBIP ECIIP Bit 29/ 21/13/5 TDLA29 TDLA21 TDLA13 TDLA5 RDLA29 RDLA21 RDLA13 RDLA5 TC TCIP MFC13 MFC5 Bit 28/ 20/12/4 TDLA28 TDLA20 TDLA12 TDLA4 RDLA28 RDLA20 RDLA12 RDLA4 TDE RRF TDEIP RRFIP MFC12 MFC4 Bit 27/ 19/11/3 TDLA27 TDLA19 TDLA11 TDLA3 RDLA27 RDLA19 RDLA11 RDLA3 TFUF CND RTLF TFUFIP CNDIP RTLFIP MFC11 MFC3 Bit 26/ 18/10/2 TDLA26 TDLA18 TDLA10 TDLA2 RDLA26 RDLA18 RDLA10 RDLA2 TABT FR DLC RTSF TABTIP FRIP DLCIP RTSFIP MFC10 MFC2 Bit 25/ 17/9/1 TDLA25 TDLA17 TDLA9 TDLA1 RDLA25 RDLA17 RDLA9 RDLA1 RABT RDE CD PRE RABTIP RDEIP CDIP PREIP MFC9 MFC1 Bit 24/ 16/8/0 RR TDLA24 TDLA16 TDLA8 TDLA0 RDLA24 RDLA16 RDLA8 RDLA0 RFCOF RFOF TRO CERF RFCOFIP Module E-DMAC TDLARn (n = 0, 1) TDLA31 TDLA23 TDLA15 TDLA7 RDLARn (n = 0, 1) RDLA31 RDLA23 RDLA15 RDLA7 EESRn (n = 0, 1) ADE RMAF EESIPRn (n = 0, 1) ADEIP RMAFIP RFOFIP TROIP CERFIP MFC8 MFC0 TRSCERn (n = 0, 1) RMAFCE RMFCRn (n = 0, 1) MFC15 MFC7 MFC14 MFC6 Rev. 1.00 Dec. 27, 2005 Page 841 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TFTRn (n = 0, 1) Bit 31/ 23/15/7 TFT7 Bit 30/ 22/14/6 TFT6 Bit 29/ 21/13/5 TFT5 Bit 28/ 20/12/4 TFT4 Bit 27/ 19/11/3 TFT3 FEC Bit 26/ 18/10/2 TFT10 TFT2 TFD2 RFD2 AEC Bit 25/ 17/9/1 TFT9 TFT1 TFD1 RFD1 Bit 24/ 16/8/0 TFT8 TFT0 TFD0 RFD0 RNC Module E-DMAC FDRn (n = 0, 1) RMCRn (n = 0, 1) EDOCRn (n = 0, 1) RBWARn (n = 0, 1) RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16 RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA9 RBWA7 RBWA6 RDFA30 RDFA22 RDFA14 RDFA6 TBRA30 TBRA22 TBRA14 TBRA6 RBWA5 RBWA4 RBWA3 RDFA27 RDFA19 RDFA11 RDFA3 TBRA27 TBRA19 TBRA11 TBRA3 RBWA2 RDFA26 RDFA18 RDFA10 RDFA2 TBRA26 TBRA18 TBRA10 TBRA2 RBWA1 RDFA25 RDFA17 RDFA9 RDFA1 TBRA25 TBRA17 TBRA9 TBRA1 RBWA8 RBWA0 RDFA24 RDFA16 RDFA8 RDFA0 TBRA24 TBRA16 TBRA8 TBRA0 RDFARn (n = 0, 1) RDFA31 RDFA23 RDFA15 RDFA7 RDFA29 RDFA28 RDFA21 RDFA20 RDFA13 RDFA12 RDFA5 TBRA29 TBRA21 TBRA13 TBRA5 RDFA4 TBRA28 TBRA20 TBRA12 TBRA4 TBRARn (n = 0, 1) TBRA31 TBRA23 TBRA15 TBRA7 Rev. 1.00 Dec. 27, 2005 Page 842 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TDFARn (n = 0, 1) Bit 31/ 23/15/7 TDFA31 TDFA23 TDFA15 TDFA7 Bit 30/ 22/14/6 TDFA30 TDFA22 TDFA14 TDFA6 Bit 29/ 21/13/5 TDFA29 TDFA21 TDFA13 TDFA5 Bit 28/ 20/12/4 TDFA28 TDFA20 TDFA12 TDFA4 Bit 27/ 19/11/3 TDFA27 TDFA19 TDFA11 TDFA3 Bit 26/ 18/10/2 TDFA26 TDFA18 TDFA10 TDFA2 RFF2 RFD2 Bit 25/ 17/9/1 TDFA25 TDFA17 TDFA9 TDFA1 RFF1 RFD1 Bit 24/ 16/8/0 TDFA24 TDFA16 TDFA8 TDFA0 RFF0 RFD0 TIS Module E-DMAC FCFTRn (n = 0, 1) TRIMDn (n = 0, 1) PACR PA7MD1 PA7MD0 PA6MD1 PA6MD0 PA5MD1 PA5MD0 PA4MD1 PA4MD0 PFC PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 PBCR PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 PCCR PC7MD1 PC7MD0 PC6MD1 PC6MD0 PC5MD1 PC5MD0 PC4MD1 PC4MD0 PC3MD1 PC3MD0 PC2MD1 PC2MD0 PC1MD1 PC1MD0 PC0MD1 PC0MD0 PETCR PET3MD PA6DT PB6DT PC6DT TI6 DID30 DID22 DID14 DID6 PET2MD PA5DT PB5DT PC5DT TI5 DID29 DID21 DID13 DID5 PA4DT PB4DT PC4DT TI4 DID28 DID20 DID12 DID4 PET1MD PA3DT PB3DT PC3DT TI3 DID27 DID19 DID11 DID3 PA2DT PB2DT PC2DT TI2 DID26 DID18 DID10 DID2 PET0MD PA1DT PB1DT PC1DT TI1 DID25 DID17 DID9 DID1 PA0DT PB0DT PC0DT TI0 DID24 DID16 DID8 DID0 H-UDI I/O port PADR PBDR PCDR SDIR PA7DT PB7DT PC7DT TI7 SDID/ SDIDH SDIDL DID31 DID23 DID15 DID7 Notes: 1. Bit names in the first row of CS0WCR show the names for the normal/byte-selection SRAM interface, in the second row for the burst ROM (asynchronous) interface, and in the third row for the burst ROM (synchronous) interface. Rev. 1.00 Dec. 27, 2005 Page 843 of 932 REJ09B0269-0100 Section 23 List of Registers 2. Bit names in the first rows of CS2WCR and CS3WCR show the names for the normal/byte-selection SRAM interface and in the second rows for the SDRAM interface. 3. Bit names in the first row of CS4WCR show the names for the normal/byte-selection SRAM interface and in the second row for the burst ROM (asynchronous) interface. 4. Bit names of CS5AWCR and CS6AWCR show the names for the normal/byte-selection SRAM interface. 5. Bit names in the first rows of CS5BWCR and CS6BWCR show the names for the normal/byte-selection SRAM interface and in the second rows for the PCMCIA interface. Rev. 1.00 Dec. 27, 2005 Page 844 of 932 REJ09B0269-0100 Section 23 List of Registers 23.3 Register States in Each Operating Mode Power-on Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained INTC Cache MMU Module Exception handling Register Abbreviation INTEVT INTEVT2 TRA EXPEVT TEA MMUCR PTEH PTEL TTB CCR1 CCR2 CCR3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI ICR0 ICR1 IRR0 IRR1 IRR2 IRR3 IRR4 Rev. 1.00 Dec. 27, 2005 Page 845 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation IRR5 IRR7 IRR8 BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR BASRA BASRB STBCR STBCR2 STBCR3 FRQCR WTCNT WTCSR CMNCR CS0BCR CS2BCR CS3BCR CS4BCR CS5ABCR CS5BBCR CS6ABCR Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Software standby Retained* Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained 2 Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module INTC UBC Power-down mode CPG BSC Rev. 1.00 Dec. 27, 2005 Page 846 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation CS6BBCR CS0WCR CS2WCR CS3WCR CS4WCR CS5AWCR CS5BWCR CS6AWCR CS6BWCR SDCR RTCSR RTCNT RTCOR SAR_n (n = 0 to 5) DAR_n (n = 0 to 5) DMATCR_n (n = 0 to 5) CHCR_n (n = 0 to 5) DMAOR DMARS0 DMARS1 DMARS2 TSTR TCOR_n (n = 0 to 2) TCNT_n (n = 0 to 2) TCR_n (n = 0 to 2) Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized* Retained Retained Retained 3 Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Initialized Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module BSC DMAC TMU Rev. 1.00 Dec. 27, 2005 Page 847 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RYRAR RCR1 RCR2 RCR3 SCSMR_n (n = 0, 1) SCBRR_n (n = 0, 1) SCSCR_n (n = 0, 1) SCFTDR_n (n = 0, 1) SCFSR_n (n = 0, 1) SCFRDR_n (n = 0, 1) SCFCR_n (n = 0, 1) Power-on 1 Reset* Retained Retained Retained Retained Retained Retained Retained Retained Retained* Retained* Retained* Retained* 4 4 Manual Reset*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized* Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized 5 Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module RTC 4 4 Retained*4 Retained* Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized 4 SCIF Rev. 1.00 Dec. 27, 2005 Page 848 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation SCFDR_n (n = 0, 1) SCLSR_n (n = 0, 1) SIMDR_n (n = 0, 1) SISCR_n (n = 0, 1) SITDAR_n (n = 0, 1) SIRDAR_n (n = 0, 1) SICDAR_n (n = 0, 1) SICTR_n (n = 0, 1) SIFCTR_n (n = 0, 1) SISTR_n (n = 0, 1) SIIER_n (n = 0, 1) SITDR_n (n = 0, 1) SIRDR_n (n = 0, 1) SITCR_n (n = 0, 1) SIRCR_n (n = 0, 1) ECMRn (n = 0, 1) ECSRn (n = 0, 1) ECSIPRn (n = 0, 1) Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module SCIF SIOF EtherC Rev. 1.00 Dec. 27, 2005 Page 849 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation PIRn (n = 0, 1) MAHRn (n = 0, 1) MALRn (n = 0, 1) RFLRn (n = 0, 1) PSRn (n = 0, 1) TROCRn (n = 0, 1) CDCRn (n = 0, 1) LCCRn (n = 0, 1) CNDCRn (n = 0, 1) CEFCRn (n = 0, 1) FRECRn (n = 0, 1) TSFRCRn (n = 0, 1) TLFRCRn (n = 0, 1) RFCRn (n = 0, 1) MAFCRn (n = 0, 1) IPGRn (n = 0, 1) ARSTR TSU_CTRST TSU_FWEN0 TSU_FWEN1 Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module EtherC Rev. 1.00 Dec. 27, 2005 Page 850 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TSU_FCM TSU_BSYSL0 TSU_BSYSL1 TSU_PRISL0 TSU_PRISL1 TSU_FWSL0 TSU_FWSL1 TSU_FWSLC Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module EtherC TSU_QTAGM0 Initialized TSU_QTAGM1 Initialized TSU_ADQT0 TSU_ADQT1 TSU_FWSR Initialized Initialized Initialized TSU_FWINMK Initialized TSU_ADSBSY Initialized TSU_TEN TSU_POST1 TSU_POST2 TSU_POST3 TSU_POST4 TXNLCR0 TXALCR0 RXNLCR0 RXALCR0 FWNLCR0 FWALCR0 TXNLCR1 TXALCR1 RXNLCR1 RXALCR1 FWNLCR1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Dec. 27, 2005 Page 851 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation FWALCR1 TSU_ADRHn (n = 0 to 31) TSU_ADRLn (n = 0 to 31) EDMRn (n = 0, 1) EDTRRn (n = 0, 1) EDRRRn (n = 0, 1) TDLARn (n = 0, 1) RDLARn (n = 0, 1) EESRn (n = 0, 1) EESIPRn (n = 0, 1) TRSCERn (n = 0, 1) RMFCRn (n = 0, 1) TFTRn (n = 0, 1) FDRn (n = 0, 1) RMCRn (n = 0, 1) EDOCRn (n = 0, 1) RBWARn (n = 0, 1) RDFARn (n = 0, 1) Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module EtherC E-DMAC Rev. 1.00 Dec. 27, 2005 Page 852 of 932 REJ09B0269-0100 Section 23 List of Registers Register Abbreviation TBRARn (n = 0, 1) TDFARn (n = 0, 1) FCFTRn (n = 0, 1) TRIMDn (n = 0, 1) PACR PBCR PCCR PETCR PADR PBDR PCDR SDIR SDID/SDIDH SDIDL Power-on 1 Reset* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Manual Reset*1 Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module E-DMAC PFC I/O port H-UDI Notes: 1. For the initial values of each register, see the sections for the corresponding modules. If the initial value is undefined, it is shown as initialized since the data is not retained. 2. Some bits are initialized in standby mode. See section 8, Interrupt Controller (INTC), for details. 3. If the multiplication rate of PLL1 is modified, this register is initialized. 4. Some bits are initialized by a power-on reset. See section 15, Realtime Clock (RTC), for details. 5. Some bits are initialized by a manual reset. See section 15, Realtime Clock (RTC), for details. Rev. 1.00 Dec. 27, 2005 Page 853 of 932 REJ09B0269-0100 Section 23 List of Registers Rev. 1.00 Dec. 27, 2005 Page 854 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 shows the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Power supply voltage (internal) Symbol VCCQ VCCQ-RTC VCC VCC-PLL1 VCC-PLL2 Vin Topr Tstg Rating -0.3 to 4.6 -0.3 to 2.1 Unit V V Input voltage Operating temperature Storage temperature -0.3 to VCCQ + 0.3 -20 to 75 -55 to 125 V C C Caution: * Operating the chip in excess of the absolute maximum rating may result in permanent damage. * Order of turning on 1.5 V power (Vcc, Vcc-PLL1, Vcc-PLL2) and 3.3 V power (VccQ, VccQRTC): 1. The 3.3 V power and the 1.5 V power should be turned on simultaneously or the 3.3 V power should be tuned on first. When the 3.3 V is turned on first, turn on the 1.5 V power within 1 ms. It is recommended that this interval will be as short as possible. 2. Until voltage is applied to all power supplies and a low level is input at the RESETP pin, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. 3. When the power is turned on, make sure that the voltage of the 1.5 V power is lower than that of the 3.3 V power. Rev. 1.00 Dec. 27, 2005 Page 855 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics * Power-off order 1. In the reverse order of powering-on, first turn off the 1.5 V power, then turn off the 3.3 V power within 1 ms. It is recommended that this interval will be as short as possible. 2. Pin states are undefined while only the 1.5 V power is off. The system design must ensure that these undefined states do not cause erroneous system operation. 3. When the power is turned off, make sure that the voltage of the 1.5 V power is lower than that of the 3.3 V power. Waveforms and recommended times at power on/off are shown in Figure 24.1. VccQ: 3.3 V power VccQ (min) voltage Vcc: 1.5 V power tpwu Vcc (min) voltage Vcc/2 level voltage GND tpwd tunc States undefined Normal operation term term Clock oscillation started VccQ (min) Oscillation settling time (10 ms) attain time Cancel the power-on reset and Vcc (min) go to normal operation attain time Operation stopped Figure 24.1 Power On/Off Sequence Recommended Power On/Off Times Item VccQ to Vcc power-on time interval VccQ to Vcc power-off time interval State undefined term Symbol tpwu tpwd tunc Max. Permitted Value 1 1 10 Unit ms ms ms Note: The recommended times shown above do not require strict settings. The state undefined term indicates that pins are at the power rising stage. The pin state is stabilized at VccQ (min.) attain time. However, a power-on reset (RESETP) is accepted successfully only after VccQ (min.) attain time and clock oscillation settling time. Set the state undefined term less than 10 ms. Rev. 1.00 Dec. 27, 2005 Page 856 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.2 DC Characteristics Tables 24.2 and 24.3 list DC characteristics. Table 24.2 DC Characteristics (1) (Condition: Ta = -20 to 75C) Item Power supply voltage Symbol Min. Typ. 3.3 1.5 Max. 3.6 1.6 Unit V V Measurement Conditions VCCQ, 3.0 VCCQ-RTC 1.4 VCC, VCC-PLL1 VCC-PLL2 Current Normal consumption operation ICC ICCQ -- -- -- -- -- -- 250 40 110 4 1500 75 330 70 160 7 2600 230 mA mA mA A VCC = 1.5 V I = 200 MHz B = 66.67 MHz VCCQ = 3.3 V B = 66.67 MHz Ta = 25C (RTC on) VCCQ = 3.3 V VCC = 1.5 V In sleep mode* In standby mode ICC ICCQ ICC ICCQ ICC ICCQ -- -- 1500 75 2600 230 A Ta = 25C (RTC off) VCCQ = 3.3 V VCC = 1.5 V Input leak current Three-state leak current Pull-up resistance Pin capacitance Note: * All input pins I/O, all output pins (off condition) Port pin All pins | Iin | | ISTI | -- -- -- -- 1.0 1.0 A A Vin = 0.5 to VCCQ - 0.5 V Vin = 0.5 to VCCQ - 0.5 V Rpull C 20 -- 60 -- 180 20 k pF No external bus cycles except refresh cycles. Rev. 1.00 Dec. 27, 2005 Page 857 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Table 24.2 DC Characteristics (2) (Condition: Ta = -20 to 75C) Item Input high voltage RESETP, RESETM, NMI IRQ5 to IRQ0, MD5 to MD0, ASEMD0, TRST, EXTAL, CKIO EXTAL2 Symbol Min. VIH Typ. Max. Measurement Unit Conditions VCCQ x 0.9 -- VCCQ + 0.3 V -- -- -- When this pin is not connected to the crystal resonator, this pin should be connected to the VCCQ pin (pulled up). Other input pins Input low RESETP, voltage RESETM, NMI IRQ5 to IRQ0, MD5 to MD0, ASEMD0, TRST, EXTAL, CKIO EXTAL2 VIL 2.0 -0.3 -- -- VCCQ + 0.3 VCCQ x 0.1 V -- -- -- When this pin is not connected to the crystal resonator, this pin should be connected to the VCCQ pin (pulled up). Other input pins Output high voltage Output low voltage All output pins VOH -0.3 2.4 -- -- VCCQ x 0.2 -- V VCCQ = 3.0 V, IOH = -2 mA VCCQ = 3.0 V, IOL = 2 mA All output pins VOL -- -- 0.55 V Rev. 1.00 Dec. 27, 2005 Page 858 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Notes: 1. Even when the RTC is not used, power must be supplied between VCCQ-RTC and VSSQRTC. 2. Current consumption values are for VIH min. = VCCQ - 0.5 V and VIL max. = 0.5 V with all output pins unloaded. Table 24.3 Permitted Output Current Values (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH (-IOH) Min. -- -- -- -- Typ. -- -- -- -- Max. 2.0 120 2.0 40 Unit mA mA mA mA Caution: To ensure LSI reliability, do not exceed the value for output current given in Table 24.3. 24.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 24.4 Maximum Operating Frequencies (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Item Operating frequency CPU, cache (I) External bus (B) Peripheral module (P) Symbol f Min. 33.34 33.34 8.34 Typ. -- -- -- Max. 200 66.67 33.34 Unit MHz Remarks Rev. 1.00 Dec. 27, 2005 Page 859 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.1 Clock Timing Table 24.5 Clock Timing (Condition: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C, maximum external bus operating frequency: 66.67 MHz) Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time RESETP assert time RESETM assert time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK2OR tCK2OF tOSC1 tRESPS tRESPW tRESMW tOSC2 tOSC3 tOSC4 Min. 10 15 1.5 1.5 -- -- 33.34 15 3 3 -- -- 33.34 15 3 3 -- -- -- -- -- 10 20 20 20 10 10 11 Max. 100 -- -- 6 6 66.67 MHz 30 -- -- 4 4 66.67 MHz 30 -- -- 4 4 2.5 7 7 -- -- -- -- -- -- -- ms ns tcyc tcyc ms ms ms 24.5 24.5 24.5, 24.6 24.6 24.6 24.7 24.8 ns 24.4 ns 24.3 Unit ns Figure 24.2 66.67 MHz Rev. 1.00 Dec. 27, 2005 Page 860 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Item PLL synchronization settling time 1 PLL synchronization settling time 2 Interrupt determination time (RTC used and standby mode) Symbol tPLL1 tPLL2 tIRLSTB Min. 100 100 100 Max. -- -- -- Unit s s s Figure 24.9, 24.10 24.11 24.10 tEXcyc EXTAL* (input) 1/2 VCCQ tEXH tEXL VIH 1/2 VCCQ tEXR VIH VIH VIL tEXF VIL Note: * The clock input from the EXTAL pin. Figure 24.2 EXTAL Clock Input Timing tCKIcyc CKIO (input) tCKIH 1/2 VCCQ VIH VIH VIL tCKIL VIH 1/2 VCCQ tCKIR VIL tCKIF Figure 24.3 CKIO Clock Input Timing Rev. 1.00 Dec. 27, 2005 Page 861 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics tcyc tCKOH CKIO (output) VOH VOH VOL VOL tCKOL VOH 1/2VCCQ 1/2VCCQ tCKOF tCKOR tCK2D tCK2D CKIO2 (output) VOH tCK2OF tCK2OR Figure 24.4 CKIO Clock Output Timing Stable oscillation CKIO, internal clock VCC VCC min tOSC1 RESETP Note: Oscillation settling time when on-chip oscillator is used tRESPW tRESPS Figure 24.5 Power-On Oscillation Settling Time Standby CKIO, internal clock tOSC2 RESETP RESETM Note: Oscillation settling time when on-chip oscillator is used Stable oscillation tRESPW tRESMW Figure 24.6 Oscillation Settling Time at Standby Return (Return by Reset) Rev. 1.00 Dec. 27, 2005 Page 862 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Standby CKIO, internal clock tOSC3 Stable oscillation NMI Note: Oscillation settling time when on-chip oscillator is used Figure 24.7 Oscillation Settling Time at Standby Return (Return by NMI) Standby CKIO, internal clock tOSC4 IRL3 to IRL0 IRQ5 to IRQ0 Stable oscillation Note: Oscillation settling time when on-chip oscillator is used in oscillation stop mode Figure 24.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0 and IRL3 to IRL0) Reset or NMI interrupt request Stable input clock EXTAL input, CKIO input PLL synchronization PLL output, CKIO output Stable input clock tPLL1 PLL synchronization Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: PLL oscillation settling time when clock is input from EXTAL pin Figure 24.9 PLL Synchronization Settling Time by Reset or NMI Rev. 1.00 Dec. 27, 2005 Page 863 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics IRL3 to IRL0/IRQ5 to IRQ0 interrupt request Stable input clock EXTAL input, CKIO input PLL synchronization PLL output, CKIO output Stable input clock tIRLSTB tPLL1 PLL synchronization Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin in oscillation continuous mode. Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts Multiplication ratio modified EXTAL input*1 (CKIO input) tPLL2 CKIO (PLL output) output*2 Internal clock Notes: 1. CKIO input in clock mode 7 2. PLL output except in clock mode 7 Figure 24.11 PLL Synchronization Settling Time when Frequency Multiplication Ratio Modified Rev. 1.00 Dec. 27, 2005 Page 864 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.2 Control Signal Timing Table 24.6 Control Signal Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) 66.67 MHz*2 Item RESETP pulse width RESETP setup time* RESETM setup time BREQ setup time BREQ hold time NMI setup time*1 NMI hold time IRQ5 to IRQ0 setup time* IRQ5 to IRQ0 hold time BACK delay time STATUS1, STATUS0 delay time IRQOUT delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 1 1 Symbol tRESPW tRESPS tRESMW tRESMS tBREQS tBREQH tNMIS tNMIH tIRQS tIRQH tBACKD tSTD tIRQOTD tBOFF1 tBOFF2 tBON1 tBON2 Min. 20* 20 20* 10 4 3 Max. -- -- -- -- Unit tcyc ns tcyc ns Figure 24.12 RESETM pulse width 1/2 tcyc+10 -- 1/2 tcyc+3 10 3 10 3 -- -- -- 0 0 0 0 -- -- -- -- -- 1/2 tcyc+13 18 1/2 tcyc+12 30 30 30 30 24.14 24.13 24.14 24.15 24.16 24.14, 24.15 Notes: tcyc is the external bus clock cycle (B clock cycle). 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock rise when the setup shown is kept. When the setup cannot be kept, detection can be delayed until the next clock rises. 2. The upper limit of the external bus clock is 66.67 MHz. 3. In standby mode, tRESPW = tOSC2 (10 ms). When the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, tRESPW = tPLL1 (100 s). 4. In standby mode, tRESMW = tOSC2 (10 ms). When the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, RESETM must be kept low until STATUS (0-1) changes to reset (HH). Rev. 1.00 Dec. 27, 2005 Page 865 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics CKIO tRESPS tRESMS RESETP RESETM tRESPW tRESMW tRESPS tRESMS Figure 24.12 Reset Input Timing CKIO tNMIH NMI tIRQH IRQ5 to IRQ0 VIL tNMIS VIH VIL tIRQS VIH Figure 24.13 Interrupt Signal Input Timing CKIO tBREQH tBREQS BREQ tBACKD BACK tBOFF1 A25 to A0, D31 to D0 RD, RD/WR, RAS, CAS, CSn, WEn, BS, CKE tBON1 tBACKD tBREQH tBREQS tBOFF2 tBON2 Figure 24.14 Bus Release Timing Rev. 1.00 Dec. 27, 2005 Page 866 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Normal mode Standby mode Normal mode CKIO tSTD STATUS 0 STATUS 1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS, CKE tSTD tBON2 tBOFF1 tBON1 A25 to A0, D31 to D0 Figure 24.15 Pin Drive Timing at Standby CKIO tIRQOTD IRQOUT Figure 24.16 IRQOUT Output Delay Time Rev. 1.00 Dec. 27, 2005 Page 867 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.3 AC Bus Timing Table 24.7 Bus Timing (1) (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C, clock mode 0/1/2/4/5/6/7) 66.67 MHz Item Address delay time 1 Address delay time 2 Address setup time Address hold time BS delay time CS delay time 1 Read/write delay time 1 Read strobe delay time Read data setup time 1 Read data setup time 2 Read data setup time 3 Read data hold time 1 Read data hold time 2 Read data hold time 3 Write enable delay time Write data delay time 1 Write data delay time 2 Write data hold time 1 Write data hold time 2 Symbol Min. tAD1 tAD2 tAS tAH tBSD tCSD1 tRWD1 tRSD tRDS1 tRDS2 tRDS3 tRDH1 tRDH2 tRDH3 tWED tWDD1 tWDD2 tWDH1 tWDH2 1 -- 0 0 -- 1 1 -- 1/2 tcyc+6 6 1/2 tcyc+6 0 2 0 -- -- -- 1 1 Max. 12 1/2 tcyc+12 -- -- 10 10 10 1/2 tcyc+10 -- -- -- -- -- -- 1/2 tcyc+10 12 12 -- -- 24.17 to 24.21, 24.39 to 24.40 24.17 to 24.20, 24.39 to 24.42 24.22 to 24.25, 24.30 to 24.32 24.21 24.17 to 24.20, 24.39 to 24.42 24.22 to 24.25, 24.30 to 24.32 24.21 24.17 to 24.21, 24.39 to 24.40 24.17 to 24.20, 24.39 to 24.42 24.26 to 24.29, 24.33 to 24.35 24.17 to 24.20 24.26 to 24.29, 24.33 to 24.35 24.17 to 24.35, 24.39 to 24.42 24.17 to 24.42 Unit ns Figure 24.17 to 24.42 24.21 24.17 to 24.20 Rev. 1.00 Dec. 27, 2005 Page 868 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 66.67 MHz Item Write data hold time 4 Write data hold time 5 WAIT setup time WAIT hold time RAS delay time 1 CAS delay time 1 DQM delay time 1 CKE delay time 1 DACK delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time REFOUT delay time Symbol Min. tWDH4 tWDH5 tWTS tWTH tRASD1 tCASD1 tDQMD1 tCKED1 tDACD tICRSD tICWSD tIO16S tIO16H tREFOD 0 1 1/2 tcyc+6 1/2 tcyc+2 1 1 1 1 -- -- -- Max. -- -- -- -- 10 10 10 10 10 1/2 tcyc+12 1/2 tcyc+12 24.42 -- 1/2 tcyc+12 24.43 24.22 to 24.35 24.37 24.17 to 24.35 24.41, 24.42 ns Unit Figure 24.17 to 24.20 24.39 to 24.42 24.18 to 24.21, 24.40, 24.42 24.22 to 24.38 1/2 tcyc+12 -- 1/2 tcyc+4 -- Rev. 1.00 Dec. 27, 2005 Page 869 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.4 Basic Timing T1 CKIO tAD1 A25 to A0 tAS tCSD1 CSn tCSD1 tAD1 T2 tRWD1 RD/WR tRSD RD tRSD tRWD1 tAH tRDH1 Read D31 to D0 tRDS1 tWED WEn tWED tAH Write D31 to D0 tWDD1 tWDH1 tWDH4 tBSD BS tDACD DACKn* tDACD tBSD Note: * DACKn is a waveform when active-low is specified. Figure 24.17 Basic Bus Cycle (No Wait) Rev. 1.00 Dec. 27, 2005 Page 870 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics T1 CKIO Tw T2 tAD1 A25 to A0 tAD1 tAS tCSD1 CSn tCSD1 tRWD1 RD/WR tRWD1 tRSD RD tRSD tAH tRDH1 tRDS1 Read D31 to D0 tWED WEn tWED tAH Write D31 to D0 tWDD1 tWDH1 tBSD BS tBSD tWDH4 tDACD DACKn* tDACD tWTH tWTS WAIT Note: * DACKn is a waveform when active-low is specified. Figure 24.18 Basic Bus Cycle (One Software Wait) Rev. 1.00 Dec. 27, 2005 Page 871 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics T1 CKIO tAD1 A25 to A0 tAS tCSD1 CSn TwX T2 tAD1 tCSD1 tRWD1 RD/WR tRSD RD tRSD tRWD1 tAH tRDH1 Read D31 to D0 tRDS1 tWED WEn tWED tAH Write D31 to D0 tWDD1 tWDH1 tWDH4 tBSD BS tDACD DACKn* tWTH tWTS WAIT tWTH tWTS tDACD tBSD Note: * DACKn is a waveform when active-low is specified. Figure 24.19 Basic Bus Cycle (One External Wait) Rev. 1.00 Dec. 27, 2005 Page 872 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics T1 Tw T2 Tnop T1 Tw T2 Tnop CKIO tAD1 tAD1 tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 tAS tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tRWD1 RD/WR tRSD tRSD tAH tRSD tRSD tAH RD tRDH1 tRDS1 tRDS1 tRDH1 Read D15 to D0 tWED tWED tAH tWED tWED tAH WEn Write D15 to D0 tWDD1 tWDH1 tWDD1 tWDH1 tWDH4 tBSD tBSD tBSD tBSD tWDH4 BS tDACD tDACD tDACD tDACD * DACKn tWTH tWTS tWTH tWTS WAIT Note: * DACKn is a waveform when active-low is specified. Figure 24.20 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM bit = 0), No Idle Cycle Setting) Rev. 1.00 Dec. 27, 2005 Page 873 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.5 Burst ROM Timing T1 Tw Twx T2B Twb T2B CKIO tAD1 A25 to A0 tAD2 tAD2 tBSD BS tBSD tCSD1 CSn tCSD1 tRWD1 RD/WR tRWD1 tRSD RD tRSD tRDS3 tRDH3*1 D31 to D0 tRDS3 tRDH3*1 tWED WEn tWED tDACD DACKn*2 tDACD tWTH tWTS WAIT tWTH tWTS Notes: 1. tRDH3 is specified by earlier one of change of A25 to A0 or the RD rising edge. 2. DACKn is a waveform when active-low is specified. Figure 24.21 Burst ROM Read Cycle (One Access Wait, One External Wait, One Burst Wait, Two Bursts) Rev. 1.00 Dec. 27, 2005 Page 874 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.6 Synchronous DRAM Timing Tr CKIO Tc1 Tcw Td1 Tde tAD1 A25 to A0 tAD1 Column address tAD1 Row address tAD1 A12/A11*1 tAD1 tAD1 Read A command tCSD1 CSn tCSD1 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRWD1 tRASD1 tCASD1 tDQMD1 tRDS2 D31 to D0 tBSD BS (High) tDACD DACKn*2 tRDH2 tBSD tBSD CKE tDACD tDACD Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 875 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1 Trw Tc1 Tcw Td1 Tde Tap tAD1 Row address Column address tAD1 tAD1 tAD1 Read A command tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRDS2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD tCASD1 tRASD1 tCSD1 tRWD1 tDQMD1 tRDH2 CKE tDACD Figure 24.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 876 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde tAD1 A25 to A0 Row address tAD1 tAD1 Column address tAD1 tAD1 (1 to 4) tAD1 tAD1 A12/A11*1 tAD1 Read command tAD1 tAD1 Read A command tCSD1 CSn tCSD1 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 tRWD1 tRASD1 tCASD1 tDQMD1 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.24 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4), (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 877 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO tAD1 A25 to A0 tAD1 A12/A11*1 Trw Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde tAD1 Row address tAD1 tAD1 tAD1 Column address tAD1 (1 to 4) tAD1 tAD1 tAD1 Read command Read A command tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD tCASD1 tRASD1 tCSD1 tRWD1 tDQMD1 tRDS2 tRDH2 CKE tDACD Figure 24.25 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4), (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 878 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Tc1 Trwl tAD1 A25 to A0 tAD1 Row address Column address tAD1 tAD1 A12/A11*1 tAD1 tAD1 Write A command tCSD1 CSn tCSD1 tRWD1 RD/WR tRASD1 RAS tRWD1 tRWD1 tRASD1 tRASD1 tCASD1 CAS tDQMD1 DQMxx tWDD2 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.26 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 879 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Trw Trw Tc1 Trwl tAD1 A25 to A0 Row address tAD1 Column address tAD1 tAD1 A12/A11*1 tAD1 Write A command tAD1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tRASD1 tRWD1 tCSD1 tRWD1 tRASD1 tCASD1 CAS tDQMD1 DQMxx tWDD2 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 880 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO tAD1 A25 to A0 tAD1 *1 A12/A11 tAD1 Row address Tc1 Tc2 Tc3 Tc4 Trwl tAD1 Column address tAD1 (1-4) tAD1 tAD1 tAD1 Write command tAD1 Write A command tAD1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tWDD2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tWDH2 tWDD2 tRASD1 tRWD1 tCSD1 tRWD1 tRASD1 tCASD1 tDQMD1 tWDH2 tBSD CKE tDACD Figure 24.28 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4), (Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 881 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl tAD1 A25 to A0 Row address tAD1 tAD1 Column address tAD1 (1-4) tAD1 tAD1 tAD1 A12/A11 *1 tAD1 Write command tAD1 Write A command tAD1 tCSD1 CSn tCSD1 tRWD1 RD/WR tRASD1 RAS tRASD1 tRWD1 tRWD1 tRASD1 tCASD1 CAS tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD *2 DACKn tBSD CKE tDACD Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.29 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4), (Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 882 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde tAD1 A25 to A0 Row address tAD1 tAD1 Column address tAD1 tAD1 (1-4) tAD1 tAD1 A12/A11*1 tAD1 Read command tAD1 tAD1 tCSD1 CSn tCSD1 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRDS2 tRDH2 tRWD1 tRASD1 tCASD1 tDQMD1 tRDS2 tRDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, ACTV + READ Commands, CAS Latency = 2, TRCD = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 883 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tc1 CKIO tAD1 A25 to A0 Column address Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde tAD1 (1-4) tAD1 tAD1 A12/A11*1 Read command tAD1 tAD1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS (High) CKE tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD tCASD1 tCSD1 tCSD1 tRWD1 tRASD1 tCASD1 tDQMD1 tDQMD1 tRDS2 tRDH2 tBSD tDACD tDACD Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, READ Command, Same Row Address, CAS Latency = 2, TRCD = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 884 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS Tpw Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde tAD1 Row address tAD1 Column address tAD1 tAD1 (1-4) tAD1 tAD1 tAD1 Read command tAD1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tRASD1 tRASD1 tCASD1 CAS tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 tCASD1 tCASD1 tDQMD1 tDQMD1 tRDS2 tRDH2 tBSD tBSD CKE tDACD tDACD Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (Single Read x 4) (Bank Active Mode, PRE + ACTV + READ Commands, Different Row Address, CAS Latency = 2, TRCD = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 885 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO Tc1 Tc2 Tc3 Tc4 tAD1 A25 to A0 tAD1 tAD1 Column address tAD1 (1-4) tAD1 tAD1 Row address tAD1 A12/A11*1 tAD1 Write command tAD1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.33 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, ACTV + WRITE Commands, TRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 886 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tnop CKIO Tc1 Tc2 Tc3 Tc4 tAD1 A25 to A0 tAD1 Column address tAD1 (1-4) tAD1 tAD1 tAD1 A12/A11*1 tAD1 Write command tAD1 tCSD1 CSn tCSD1 tRWD1 RD/WR tRWD1 tRWD1 tRASD1 RAS tCASD1 CAS tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, WRITE Command, Same Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 887 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO Tpw Tr Tc1 Tc2 Tc3 Tc4 tAD1 A25 to A0 Row address tAD1 tAD1 Column address tAD1 (1-4) tAD1 tAD1 tAD1 A12/A11*1 tAD1 tAD1 Write command tAD1 tCSD1 CSn tCSD1 tRWD1 RD/WR tRWD1 tRWD1 tRWD1 tRASD1 RAS tRASD1 tRASD1 tRASD1 tRASD1 tCASD1 CAS tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tCASD1 tDQMD1 tWDH2 D31 to D0 tBSD BS (High) tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. tBSD CKE tDACD Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (Single Write x 4) (Bank Active Mode, PRE + ACTV + WRITE Commands, Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00 Dec. 27, 2005 Page 888 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO Tpw Trr Trc Trc Trc tAD1 A25 to A0 tAD1 tAD1 A12/A11*1 tAD1 tCSD1 CSn tCSD1 tCSD1 tCSD1 tRWD1 RD/WR tRWD1 tRWD1 tRASD1 RAS tRASD1 tRASD1 tRASD1 tCASD1 CAS DQMxx tCASD1 D31 to D0 (Hi-Z) BS (High) CKE DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 889 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO tAD1 A25 to A0 tAD1 A12/A11*1 Tpw Trr Trc Trc Trc Trc Trc tAD1 tAD1 tCSD1 CSn tRWD1 RD/WR tRASD1 RAS tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tRASD1 tCASD1 CAS tCASD1 DQMxx (Hi-Z) D31 to D0 BS CKE tCKED1 tCKED1 DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 890 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO PALL tAD1 A25 to A0 tAD1 A12/A11*1 Tpw Trr Trc Trc Trr Trc Trc Tmw Tde REF REF MRS tAD1 tAD1 tAD1 tCSD1 CSn tRWD1 RD/WR tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tRWD1 tRWD1 tRASD1 tRASD1 tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tRASD1 tRASD1 tRASD1 tRASD1 tCASD1 tCASD1 tCASD1 tCASD1 DQMxx (Hi-Z) D31 to D0 BS CKE DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle) Rev. 1.00 Dec. 27, 2005 Page 891 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tpcm1 CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR tRSD RD Read Tpcm1w Tpcm1w Tpcm1w Tpcm2 tAD1 tCSD1 tRWD1 tRSD tRDH1 tRDS1 D15 to D0 tWED WE Write tWED tWDH5 tWDD1 tWDH1 D15 to D0 tBSD BS tBSD Figure 24.39 PCMCIA Memory Card Interface Bus Timing Rev. 1.00 Dec. 27, 2005 Page 892 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR tRSD RD Read tAD1 tCSD1 tRWD1 tICRSD tRDH1 tRDS1 D15 to D0 tWED WE Write tWED tWDH5 tWDD1 tWDH1 D15 to D0 tBSD BS tBSD tWTH tWTS tWTH tWTS WAIT Figure 24.40 PCMCIA Memory Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, One Software Wait, One Hardware Wait) Rev. 1.00 Dec. 27, 2005 Page 893 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tpci1 CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR tICRSD ICIORD Read Tpci1w Tpci1w Tpci1w Tpci2 tAD1 tCSD1 tRWD1 tICRSD tRDH1 tRDS1 D15 to D0 tICWSD ICIOWE Write tICWSD tWDH5 tWDD1 tWDH1 D15 to D0 tBSD BS tBSD Figure 24.41 PCMCIA I/O Card Interface Bus Timing Rev. 1.00 Dec. 27, 2005 Page 894 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tpci0 CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w tAD1 tCSD1 tRWD1 tICRSD ICIORD Read D15 to D0 tICWSD ICIOWE Write D15 to D0 tBSD BS tBSD tWTH tWTS WAIT tIO16S IOIS16 tIO16H tWTH tWTS tICRSD tRDH1 tRDS1 tICWSD tWDH5 tWDH1 tWDD1 Figure 24.42 PCMCIA I/O Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, One Software Wait, One Hardware Wait) CKIO tREFOD REFOUT Figure 24.43 REFOUT Delay Time Rev. 1.00 Dec. 27, 2005 Page 895 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Table 24.8 Bus Timing (2) (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C, clock mode 0/1/2/4/5/6/7) Item Address delay time 3 CS delay time 2 Read/write delay time 2 Read data setup time 4 Read data hold time 4 Write data delay time 3 Write data hold time 3 RAS delay time 2 CAS delay time 2 DQM delay time 2 CKE delay time 2 Symbol Min. tAD3 tCSD2 tRWD2 tRDS4 tRDH4 tWDD3 tWDH3 tRASD2 tCASD2 tDQMD2 tCKED2 1/2 tcyc 1/2 tcyc 1/2 tcyc 1/2 tcyc+6 0 -- 1/2 tcyc 1/2 tcyc 1/2 tcyc 1/2 tcyc 1/2 tcyc Max. Unit Figure 24.44 to 24.47 24.44 to 24.47 24.44 to 24.47 24.44 24.44 24.44 24.44 24.44 to 24.47 24.44 to 24.47 24.44 24.46 1/2 tcyc+12 ns 1/2 tcyc+10 1/2 tcyc+10 -- -- 1/2 tcyc+12 -- 1/2 tcyc+10 1/2 tcyc+10 1/2 tcyc+10 1/2 tcyc+10 Rev. 1.00 Dec. 27, 2005 Page 896 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tr CKIO tAD3 A25 to A0 tAD3 A12/A11*1 tCSD2 CSn tRWD2 RD/WR tRASD2 RAS Tc1 Tw Td1 Tde Tap Tr Tc1 Tnop Trwl Tap tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tCSD2 tCSD2 tCSD2 tRWD2 tRWD2 tRASD2 tRASD2 tRASD2 tCASD2 CAS tDQMD2 DQMxx tCASD2 tCASD2 tCASD2 tDQMD2 tDQMD2 tDQMD2 tRDS4 tRDH4 D31 to D0 tBSD BS (High) tWDD3 tWDH3 tBSD tBSD tBSD CKE tDACD tDACD tDACD tDACD DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.44 Access Timing in Low-Frequency Mode (Auto Precharge) Rev. 1.00 Dec. 27, 2005 Page 897 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO Tpw Trr Trc Trc Trc tAD3 A25 to A0 tAD3 tAD3 A12/A11*1 tAD3 tCSD2 CSn tRWD2 RD/WR tRASD2 RAS tCSD2 tCSD2 tCSD2 tRWD2 tRWD2 tRASD2 tRASD2 tRASD2 tCASD2 CAS DQMxx tCASD2 D31 to D0 (Hi-Z) BS (High) CKE DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.45 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode) Rev. 1.00 Dec. 27, 2005 Page 898 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO Tpw Trr Trc Trc Trc Trc Trc tAD3 A25 to A0 tAD3 tAD3 A12/A11*1 tAD3 tCSD2 CSn tCSD2 tCSD2 tCSD2 tRWD2 RD/WR tRWD2 tRWD2 tRASD2 RAS tRASD2 tRASD2 tRASD2 tCASD2 CAS tCASD2 DQMxx (Hi-Z) D31 to D0 BS tCKED2 tCKED2 CKE DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.46 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode) Rev. 1.00 Dec. 27, 2005 Page 899 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics Tp CKIO PALL tAD3 A25 to A0 tAD3 A12/A11*1 Tpw Trr Trc Trc Trr Trc Trc Tmw Tde REF REF MRS tAD3 tAD3 tAD3 tCSD2 CSn tRWD2 RD/WR tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tRWD2 tRWD2 tRWD2 tRWD2 tRASD2 tRASD2 tRASD2 tRASD2 RAS tCASD2 tCASD2 CAS tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 tCASD2 tCASD2 DQMxx (Hi-Z) D31 to D0 BS CKE DACKn*2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.47 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle, Low-Frequency Mode) Rev. 1.00 Dec. 27, 2005 Page 900 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.7 DMAC Signal Timing Table 24.9 DMAC Signal Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Module DMAC Item DREQn setup time DREQn hold time TENDn, DACKn delay time Symbol tDRQS tDRQH tDACD Min. 10 3 -- Max. -- -- 10 24.49 Unit ns Figure 24.48 CKIO tDRQS tDRQH DREQn Figure 24.48 DREQn Input Timing CKIO tDACD TENDn DACKn tDACD Figure 24.49 TENDn, DACKn Output Timing Rev. 1.00 Dec. 27, 2005 Page 901 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.8 RTC Signal Timing Table 24.10 RTC Signal Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Module RTC Item Oscillation settling time Symbol tROSC Min. 3 Max. -- Unit s Figure 24.50 Stable oscillation RTC crystal oscillator VCC VCCmin tROSC Figure 24.50 Oscillation Settling Time when RTC Crystal Oscillator is Turned On Rev. 1.00 Dec. 27, 2005 Page 902 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.9 SCIF Module Signal Timing Table 24.11 SCIF Module Signal Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Module SCIF0, SCIF1 Item Input clock cycle Symbol Clock tScyc synchronization Asynchronization Input clock rise time Input clock fall time Input clock pulse width Transmission data delay time Receive data setup time (clock synchronization) Receive data hold time (clock synchronization) RTS delay time CTS setup time (clock synchronization) CTS hold time (clock synchronization) tSCKR tSCKF tSCKW tTXD tRXS tRXH tRTSD tCTSS tCTSH Min. 12 4 -- -- 0.4 -- 2 tPcyc* 2 tPcyc* -- 100 100 Max. -- -- 1.5 1.5 0.6 3 tPcyc* + 50 -- -- 100 -- -- tScyc ns 24.52 24.51 Unit tPcyc Figure 24.51 24.52 Note: * tPcyc indicates a peripheral clock (P) cycle. tSCKW SCIFnCK tSCKR tSCKF tScyc Figure 24.51 SCIFnCK Input Clock Timing Rev. 1.00 Dec. 27, 2005 Page 903 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics tScyc SCIFnCK tTXD TxD (data transmission) RxD (data reception) RTS tCTSS tCTSH CTS tRXS tRXH tRTSD Figure 24.52 SCIF Input/Output Timing in Clock Synchronous Mode 24.3.10 SIOF Module Signal Timing Table 24.12 SIOF Module Signal Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Item SIOMCLK clock input cycle time SIOMCLK input high-level width SIOMCLK input low-level width SCK_SIO clock cycle time SCK_SIO output high-level width SCK_SIO output low-level width SIOFSYNC output delay time SCK_SIO input high-level width SCK_SIO input low-level width SIOFSYNC input setup time SIOFSYNC input hold time TXD_SIO output delay time RXD_SIO input setup time RXD_SIO input hold time Symbol tMcyc tMWH tMWL tSIcyc tSWHO tSWLO tFSD tSWHI tSWLI tFSS tFSH tSTDD tSRDS tSRDH Min. 30 0.4 x tMcyc 0.4 x tMcyc 2 x tPcyc 0.4 x tSIcyc 0.4 x tSIcyc -- 0.4 x tSIcyc 0.4 x tSIcyc 20 20 -- 20 20 Max. -- -- -- -- -- -- 20 -- -- -- -- 20 -- -- 24.54 to 24.58 24.58 24.54 to 24.58 24.54 to 24.57 Unit ns Figure 24.53 Note: tPcyc is the cycle time (ns) of the peripheral clock (P). Rev. 1.00 Dec. 27, 2005 Page 904 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics tMCYC SIOMCLK tMWH tMWL Figure 24.53 SIOMCLK Input Timing tSICYC tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD TXD_SIO tSRDS RXD_SIO tSRDH Figure 24.54 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time) Rev. 1.00 Dec. 27, 2005 Page 905 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics tSIcyc tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD TXD_SIO tSRDS RXD_SIO tSRDH Figure 24.55 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time) tSIcyc tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD TXD_SIO tSRDS RXD_SIO tSRDH tSTDD tSTDD tSTDD Figure 24.56 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time) Rev. 1.00 Dec. 27, 2005 Page 906 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics tSIcyc tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD tSTDD tSTDD TXD_SIO tSRDS RXD_SIO tSRDH Figure 24.57 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time) tSIcyc tSWHI tSWLI SCK_SIO (input) tFSS tFSH SIOFSYNC (input) tSTDD tSTDD TXD_SIO tSRDS RXD_SIO tSRDH Figure 24.58 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2) Rev. 1.00 Dec. 27, 2005 Page 907 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.11 Ethernet Controller Timing Table 24.13 Ethernet Controller Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Item TX-CLK cycle time TX-EN output delay time ETXD[3:0] output delay time CRS setup time CRS hold time COL setup time COL hold time RX-CLK cycle time RX-DV setup time RX-DV hold time ERXD[3:0] setup time ERXD[3:0] hold time RX-ER setup time RX-ER hold time MDIO setup time MDIO hold time MDIO output data hold time* WOL output delay time EXOUT output delay time CAMSEN setup time CAMSEN hold time ARBUSY output delay time Note: * Symbol tTcyc tTEND tETDD tCRSS tCRSH tCOLS tCOLH tRcyc tRDVS tRDVH tERDS tERDH tRERS tRERH tMDIOS tMDIOH tMDIODH tWOLD tEXOUTD tCAMS tCAMH tARBYD Min. 40 3 3 10 10 10 10 40 10 3 10 3 10 3 10 10 5 1 1 10 3 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- 20 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 18 18 28 -- -- 1/2 tcyc+12 24.68 24.64 24.65 24.66 24.67 24.63 24.62 24.61 24.60 Unit ns Figure 24.59 The user must ensure that the code satisfies this condition. Rev. 1.00 Dec. 27, 2005 Page 908 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics TX-CLK tTEND TX-EN tETDD ETXD[3:0] Preamble SFD DATA CRC TX-ER tCRSS CRS tCRSH COL Figure 24.59 MII Transmit Timing (Normal Operation) TX-CLK TX-EN ETXD[3:0] Preamble JAM TX-ER CRS tCOLS COL tCOLH Figure 24.60 MII Transmit Timing (Case of Conflict) Rev. 1.00 Dec. 27, 2005 Page 909 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics RX-CLK tRDVS RX-DV tERDH tERDS ERXD[3:0] Preamble SFD DATA CRC tRDVH RX-ER Figure 24.61 MII Receive Timing (Normal Operation) RX-CLK RX-DV ERXD[3:0] Preamble SFD DATA tRERS tRERH XXXX RX-ER Figure 24.62 MII Receive Timing (Case of Error) MDC tMDIOS MDIO tMDIOH Figure 24.63 MDIO Input Timing MDC tMDIODH MDIO Figure 24.64 MDIO Output Timing Rev. 1.00 Dec. 27, 2005 Page 910 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics RX-CLK tWOLD WOL Figure 24.65 WOL Output Timing CKIO tEXOUTD EXOUT Figure 24.66 EXOUT Output Timing RX-CLK RX-DV ERXD[3:0] Preamble SFD Dest Address Source Address DATA tCAMS CAMSEN tCAMH Figure 24.67 CAMSEN Input Timing CKIO tARBYD ARBUSY Figure 24.68 ARBUBY Output Timing Rev. 1.00 Dec. 27, 2005 Page 911 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.12 Port Input/Output Timing Table 24.14 Port Input/Output Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Module Item Port Output data delay time Input data setup time Symbol tPORTD Min. -- 15 tcyc+15 3 x tcyc+15 tPORTH 8 Max. 17 -- -- -- -- Unit ns Figure 24.69 B:P clock ratio = 1:1 tPORTS B:P clock ratio = 2:1 B:P clock ratio = 4:1 Input data hold time Note: tcyc is the output cycle time of the CKIO clock. CKIO tPORTS Port 7 to 0 (read) tPORTH tPORTD Port 7 to 0 (write) Figure 24.69 I/O Port Timing Rev. 1.00 Dec. 27, 2005 Page 912 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.13 H-UDI Related Pin Timing Table 24.15 H-UDI Related Pin Timing (Conditions: VCCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, VSSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = -20 to 75C) Item TCK cycle time TCK high-pulse width TCK low-pulse width TCK rise/fall time TRST setup time TRST hold time TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time ASEMD0 setup time ASEMD0 hold time ASEBRKAK delay time Symbol tTCKcyc tTCKH tTCKL tTCKR/tTCKF tTRSTS tTRSTH tTDIS tTDIH tTMSS tTMSH tTDOD tASEMD0S tASEMD0H tASBRAKD Min. 50 12 12 -- 12 50 10 10 10 10 -- 12 12 -- Max. -- -- -- 4 -- -- -- -- -- -- 15 -- -- 15 Unit ns ns ns ns ns tcyc ns ns ns ns ns ns ns ns 24.74 24.73 24.72 24.71 Figure 24.70 tTCKcyc tTCKH tTCKL VIH 1/2 VCCQ tTCKR 1/2 VCCQ VIH VIH VIL tTCKF VIL Figure 24.70 TCK Input Timing Rev. 1.00 Dec. 27, 2005 Page 913 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics RESETP tTRSTS TRST tTRSTH Figure 24.71 TRST Input Timing (Reset Hold) tTCKcyc TCK tTDIS TDI tTDIH tTMSS TMS tTMSH tTDOD TDO Figure 24.72 H-UDI Data Transfer Timing RESETP tASEMD0S ASEMD0 tASEMD0H Figure 24.73 ASEMD0 Input Timing CKIO tASBRAKD ASEBRKAK Figure 24.74 ASEBRKAK Delay Time Rev. 1.00 Dec. 27, 2005 Page 914 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.3.14 AC Characteristics Measurement Conditions * I/O signal reference level: VCCQ/2 (VCCQ = 3.0 to 3.6 V, VCC = 1.4 to 1.6 V) * Input pulse level: VSSQ to 3.0 V (where RESETP, RESETM, ASEMD0, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VSSQ to VCCQ) * Input rise and fall times: 1 ns IOL LSI output pin CL V Output load switching reference voltage VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pF: CKIO, RAS, CAS, CS0, CS2 to CS6B, BACK 50 pF: All other pins 2. IOL = 2 mA, IOH = -2 mA Figure 24.75 Output Load Circuit Rev. 1.00 Dec. 27, 2005 Page 915 of 932 REJ09B0269-0100 Section 24 Electrical Characteristics 24.4 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI's pins is shown below. The graph shown in Figure 24.76 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in Figure 24.76, the graph will not be a straight line. +4.0 ns +3.0 ns Delay Time [ns] +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF Load Capacitance [pF] +50 pF Figure 24.76 Load Capacitance vs. Delay Time Rev. 1.00 Dec. 27, 2005 Page 916 of 932 REJ09B0269-0100 Appendix Appendix A. Pin States and States of Unused Pins Reset Pin Name REFOUT/IRQOUT/ ARBUSY I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins O/O/O H I O O O O O I O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO I O H H H H I H H Z Z Z Z Z Z Z Z Z Z Z Z Z Z H i O H H H H I H H Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z HZ* 4 H I O O O O O I 4 H I L Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Open Pull-up Open Open Open Open Open Pull-up Open Open Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up BREQ BACK CS0 CS4 CS5A CS6A WAIT RD BS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 HZ*4 HZ* HZ* Z HZ* HZ* Z Z Z Z Z Z Z Z Z Z Z Z Z Z 4 4 4 O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO Rev. 1.00 Dec. 27, 2005 Page 917 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O PowerManual on Reset Reset Power-Down States Software Standby Sleep Release of Bus Handling of Unused Mastership Pins D14 D15 WE0 (BE0)/DQMLL WE1(BE1)/DQMLU /WE IO IO O/O Z Z H Z Z H H H 1 Z Z HZ* HZ* 4 4 IO IO O O O 1 Z Z Z Z Z 1 Pull-up Pull-up Open Open Open 4 1 O/O/O H RD/WR CKIO CAS CKE RAS CS2 CS3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 O IO O O O O O O O O O O O O O O O O O O O O O O O H IO* H H H H H O O O O O O O O O O O O O O O O O O HZ*4 4 1 Z* IO* H O H H H O O O O O O O O O O O O O O O O O O Z* IO* HZ* HZ* HZ* 4 4 4 IO* O O O O O O O O O O O O O O O O O O O O O O O Z* IO* HZ* 4 5 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open OZ* HZ* Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 4 4 HZ* 4 HZ*4 OZ* OZ* OZ* OZ* OZ* OZ* OZ* 5 5 5 5 5 5 5 OZ*5 OZ* OZ* OZ* OZ* OZ* OZ* OZ* 5 5 5 5 5 5 5 OZ*5 OZ* OZ* 5 5 Rev. 1.00 Dec. 27, 2005 Page 918 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins WE2 (BE2)/ DQMUL/ICIORD O/O/O H H Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z O O O O O O O O V V H H Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z O O O O O O O O P* Z P* I 2 2 HZ*4 HZ*4 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z OZ* OZ* OZ* OZ* OZ* OZ* 5 5 O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O P* 2 2 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z P* Z P* I 2 2 Open Open Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Open Open Open Open Open Open Open Open Open Open WE3 (BE3)/ O/O/O DQMUU/ICIOWR D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A18 A19 A20 A21 A22 A23 A24 A25 PTB0 PTB1/CTS1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O IO IO/I 5 5 5 5 OZ*5 OZ* 3 3 5 K* Z K* Z P* I Rev. 1.00 Dec. 27, 2005 Page 919 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins PTB2/RTS1 PTB3/RXD1 PTB4/TXD1 PTB5/SCIF1CK PTB6/CTS0 PTB7/RTS0 PTA0/RXD0 PTA1/TXD0 PTA2/SCIF0CK IO/O IO/I IO/O IO/IO IO/I IO/O IO/I IO/O IO/IO V V V V V V V V V V V V V V I I O O O O O I O I I I I I I I P*2O P* Z P* Z P* Z P*2I P* O P* Z P* Z P* Z P* I P* I P* I P*2O P* I I I O O O O O I O I I I I I I I 2 2 2 2 2 2 2 2 2 2 2 K*3Z K* Z K* Z K* Z K*3Z K* Z K* Z K* Z K* Z K* Z K* Z K* Z K*3Z K* Z Z Z O O O O O Z O Z Z Z Z Z Z Z 3 3 3 3 3 3 3 3 3 3 3 P*2O P* I P* O P P*2I P* O P* I P* O P P P* I P* I P*2O P I I O O O O O I O I I I I I I I 2 2 2 2 2 2 2 P*2O P* Z P* Z P* Z P*2I P* O P* Z P* Z P* Z P* I P* I P* I P*2O P* I I I O O O O O I O I I I I I I I 2 2 2 2 2 2 2 2 2 2 2 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pull-down Pull-down Open Open Open Open Open Pull-down Open Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down PTA3/SCK_SIO0 IO/IO PTA4/SIOMCLK0 IO/I PTA5/RXD_SIO0 IO/I PTA6/TXD_SIO0 IO/O PTA7/SIOFSYNC0 IO/IO I I O O O O O I O I I I I I I I CRS1 COL1 ETXD13 ETXD12 ETXD11 ETXD10 TX-EN1 TX-CLK1 TX-ER1 RX-ER1 RX-CLK1 RX-DV1 ERXD10 ERXD11 ERXD12 ERXD13 Rev. 1.00 Dec. 27, 2005 Page 920 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins MDC1 MDIO1 WOL1 LNKSTA1 EXOUT1/TEND1 CAMSEN1/IRQ5 CRS0 COL0 ETXD03 ETXD02 ETXD01 ETXD00 TX-EN0 TX-CLK0 TX-ER0 RX-ER0 RX-CLK0 RX-DV0 ERXD00 ERXD01 ERXD02 ERXD03 MDC0 MDIO0 WOL0 LNKSTA0 EXOUT0/TEND0 CAMSEN0/IRQ4 MD4 O IO O I O/O I/I I I O O O O O I O I I I I I I I O IO O I O/O I/I I O I O I O I I I O O O O O I O I I I I I I I O I O I O I I O I O I O I I I O O O O O I O I I I I I I I O I O I O I i O Z O Z O ZI*6 Z Z O O O O O Z O Z Z Z Z Z Z Z O Z O Z O ZI* Z 6 O I O I O I I I O O O O O I O I I I I I I I O I O I O I I O I O I O I I I O O O O O I O I I I I I I I O I O I O I i Open Pull-down Open Pull-down Open Pull-down Pull-down Pull-down Open Open Open Open Open Pull-down Open Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Open Pull-down Open Pull-down Open Pull-down Must be used Rev. 1.00 Dec. 27, 2005 Page 921 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins MD5 XTAL2 EXTAL2 ASEMD0 TDI TMS TDO TRST TCK ASEBRKAK AUDSYNC AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 RESETM RESETP NMI IRQ0/IRL0 IRQ1/IRL1 IRQ2/IRL2 IRQ3/IRL3 STATUS0 STATUS1 CKIO2 DACK0 I O I I I I O I I O O O O O O O I I I I I I I O O O O I O I M M M Z M M V Z O Z Z Z Z I I I Z Z Z Z H H O Z i O I V M M Z M M O O O O O O O I I I I I I I H H O O I O I Z V V Z V V O O O O O O O I I I I I I I H L OZ* Z 5 I O I V M M O M M O O O O O O O I I I I I I I L H O O i O I V M M Z M M O O O O O O O I I I I I I I L L OZ* O 5 Must be used Open Pull-up Must be used Open Open Open Must be used Open Open Open Open Open Open Open Open Pull-up Must be used Pull-up Pull-up Pull-up Pull-up Pull-up Open Open Open Open Rev. 1.00 Dec. 27, 2005 Page 922 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins DACK1 DREQ0 DREQ1 O I I Z I I V V V V V V V V H H I I I I O I O Z Z P* I P*2I P* I P* O P* I P* O P* O P* I H H i i i i O I 2 2 2 2 2 2 2 Z Z Z K* Z K*3Z K* Z K* Z K* Z K* H K* H K* Z HZ* 4 3 3 3 3 3 3 3 O I I P P*2I P* I P* O P P* O P* O P* I O O I I I I O I 2 2 2 2 2 O I I P* I P*2I P* I P* O P* I P* Z P* Z P* I Z Z i i i i O I 2 2 2 2 2 2 2 Open Pull-up Pull-up Open Open Open Open Open Open Open Open Open Open Must be used Must be used Must be used Must be used Open Pull-up VccQ VssQ Vcc Vss VccQ VssQ Vcc*7 PTC0/SCK_SIO1 IO/IO PTC1/SIOMCLK1 IO/I PTC2/RXD_SIO1 IO/I PTC3/TXD_SIO1 IO/O PTC4/SIOFSYNC1 IO/IO IO/O IO/O IO/I O/O O/O I I I I O I PTC5/CE2A PTC6/CE2B PTC7/IOIS16 CS5B/CE1A CS6B/CE1B MD0 MD1 MD2 MD3 XTAL EXTAL VccQ VssQ Vcc Vss VccQ-RTC VssQ-RTC Vcc-PLL1 HZ*4 I I I Z O I Rev. 1.00 Dec. 27, 2005 Page 923 of 932 REJ09B0269-0100 Appendix Reset Pin Name I/O Power-on Manual Reset Reset Power-Down States Software Standby Sleep Release of Bus Mastership Handling of Unused Pins Vss-PLL1 Vcc-PLL2 Vss-PLL2 Vss*7 Vcc*7 Vss*7 [Legend] I: Input state i: Input state (however, input is fixed by the internal logic) O: Output state (undefined although the level is high or low) L: Low-level output H: High-level output Z: High impedance (input or output buffer off) V: Input/output buffer off, pull-up on M: Input buffer on, output buffer off, pull-up on K: Output buffer on or input buffer off (pull-up on or off), depending on register settings P: Input or output depending on register settings Notes: 1. 2. 3. 4. 5. 6. 7. Depends on clock mode. The state is P when the port function is used. The state is K when the port function is used. The state is Z or H depending on register settings. The state is Z or O depending on register settings. The state is Z when the Ethernet controller function is used. To avoid the power friction, Vcc-PLL1, Vcc-PLL2, Vss-PLL1, Vss-PLL2, and other Vcc and Vss should be wired in three independent patterns from the board power-supply source. Rev. 1.00 Dec. 27, 2005 Page 924 of 932 REJ09B0269-0100 Appendix B. Package Dimensions Figure B.1 and Figure B.2 show the SH7712 package dimensions. Rev. 1.00 Dec. 27, 2005 Page 925 of 932 REJ09B0269-0100 Appendix E *2 HE c1 c ZE A A2 c e y bp x M *3 A1 REJ09B0269-0100 RENESAS Code PRQP0256LA-B Previous Code FP-256G/FP-256GV MASS[Typ.] 5.4g HD *1 JEITA Package Code P-HQFP256-28x28-0.40 D 129 128 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 192 Rev. 1.00 Dec. 27, 2005 Page 926 of 932 bp b1 Reference Symbol 193 Dimension in Millimeters Min Nom Max 256 64 65 Terminal cross section D E A2 HD HE 30.4 30.4 A A1 bp 0.25 0.13 28 28 3.20 30.6 30.6 30.8 30.8 3.95 0.40 0.18 0.50 0.23 1 ZD F L L1 b1 c c1 0.12 0.16 0.17 0.15 0.22 Detail F e x y ZD ZE L L1 0 0.4 Figure B.1 Package Dimensions (HQFP2828-256 (FP-256G/GV)) 0.3 8 0.11 0.08 1.40 1.40 0.5 1.3 0.7 Appendix JEITA Package Code P-LFBGA256-17x17-0.80 RENESAS Code PLBG0256GA-A Previous Code BP-256H/BP-256HV MASS[Typ.] 0.6g wSA D wSB x4 v y1 S S E yS e A ZD Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 1011121314151617181920 b x M S A B e A1 A B Reference Dimension in Millimeters Symbol Min Nom Max D E 17.0 17.0 0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45 v w A A1 ZE e b x y y1 SD SE ZD ZE 0.9 0.9 Figure B.2 Package Dimensions (P-LFBGA1717-256 (BP-256H/HV)) Rev. 1.00 Dec. 27, 2005 Page 927 of 932 REJ09B0269-0100 Appendix Rev. 1.00 Dec. 27, 2005 Page 928 of 932 REJ09B0269-0100 Index Numerics 16-bit/32-bit displacement ........................ 45 G General registers ....................................... 32 Global base register (GBR)....................... 40 A Absolute addresses ................................... 45 Acceptance priority and test priority ...... 162 Address space identifier (ASID)............. 189 Address transition ................................... 188 Auto-refreshing....................................... 429 Auto-request mode ................................. 477 I Instruction length ...................................... 44 IPG settings............................................. 723 L Literal constant.......................................... 45 Little endian mode .................................... 43 Load/sStore architecture ........................... 44 Low-power consumption state .................. 27 B Baud rate generator (BRG)..................... 613 Big endian mode....................................... 42 C Control by slot position .......................... 620 Control registers ....................................... 32 M Magic packet........................................... 722 MII registers.................................... 719, 720 Modulo register (MOD) ............................ 75 Multiplexed pins ..................................... 779 Multiply and accumulate registers ............ 36 D Delayed branching .................................... 44 Double data transfer instructions .............. 94 DSP registers .................................... 77, 106 O On-chip peripheral module request......... 478 E Exception handling state........................... 27 Exception request of instruction synchronous type and instruction asynchronous type .................................. 161 Extension of status register (SR) .............. 74 External request mode .................... 477, 487 P P0/U0 area................................................. 29 P1 area....................................................... 29 P2 area....................................................... 29 P3 area....................................................... 29 P4 area....................................................... 29 Physical address space ............................ 188 Procedure register ..................................... 36 Rev. 1.00 Dec. 27, 2005 Page 929 of 932 REJ09B0269-0100 Program counter ....................................... 32 Program execution state............................ 27 Q Qtags....................................................... 723 R Receive descriptor .................................. 760 receive FIFO overflow alert signal ......... 773 Re-execution type and processingcompletion type exceptions .................... 161 Registers ARSTR ............................... 644, 815, 850 BAMRA ............................. 267, 809, 846 BAMRB.............................. 270, 809, 846 BARA................................. 266, 809, 846 BARB ................................. 269, 809, 846 BASRA............................... 280, 809, 846 BASRB............................... 281, 809, 846 BBRA ................................. 267, 809, 846 BBRB ................................. 272, 809, 846 BDMRB.............................. 271, 809, 846 BDRB ................................. 270, 809, 846 BETR.................................. 278, 809, 846 BRCR ................................. 274, 809, 846 BRDR ................................. 280, 809, 846 BRSR.................................. 279, 809, 846 CCR1 .................................. 217, 808, 845 CCR2 .................................. 218, 808, 845 CCR3 .................................. 221, 808, 845 CDCR ................................. 654, 814, 850 CEFCR ............................... 655, 814, 850 CHCR ................................. 464, 810, 847 CMNCR.............................. 342, 809, 846 CNDCR .............................. 654, 814, 850 CSnBCR ............................. 345, 809, 846 CSnWCR ............................ 351, 810, 847 DAR.................................... 463, 810, 847 Rev. 1.00 Dec. 27, 2005 Page 930 of 932 REJ09B0269-0100 DMAOR ............................. 469, 811, 847 DMARS .............................. 471, 811, 847 DMATCR ........................... 464, 810, 847 ECMR ................................. 645, 813, 849 ECSIPR............................... 649, 813, 849 ECSR .................................. 648, 813, 849 EDMR................................. 730, 818, 852 EDOCR............................... 749, 818, 852 EDRRR ............................... 732, 818, 852 EDTRR ............................... 731, 818, 852 EESIPR ............................... 740, 818, 852 EESR................................... 734, 818, 852 EXPEVT ............................. 157, 808, 845 FCFTR ................................ 751, 818, 853 FDR..................................... 747, 818, 852 FRECR................................ 655, 814, 850 FRQCR ............................... 320, 809, 846 FWALCR............................ 702, 816, 851 FWNLCR............................ 701, 816, 851 ICR0.................................... 248, 808, 845 ICR1.................................... 249, 808, 845 INTEVT.............................. 157, 808, 845 INTEVT2............................ 158, 808, 845 IPGR ................................... 657, 814, 850 IPR ...................................... 246, 808, 845 IRR0.................................... 251, 809, 845 IRR1.................................... 251, 809, 845 IRR2.................................... 253, 809, 845 IRR3.................................... 254, 809, 845 IRR4.................................... 255, 809, 845 IRR5.................................... 256, 809, 846 IRR7.................................... 257, 809, 846 IRR8.................................... 258, 809, 846 LCCR.................................. 654, 814, 850 MAFCR .............................. 657, 814, 850 MAHR ................................ 651, 814, 850 MALR................................. 651, 814, 850 MMUCR ............................. 191, 808, 845 PACR.................................. 781, 819, 853 PADR.................................. 787, 819, 853 PBCR.................................. 782, 819, 853 PBDR.................................. 788, 819, 853 PCCR.................................. 783, 819, 853 PCDR.................................. 790, 819, 853 PETCR................................ 784, 819, 853 PIR...................................... 650, 813, 850 PSR ..................................... 653, 814, 850 PTEH .................................. 190, 808, 845 PTEL................................... 191, 808, 845 R64CNT ............................. 508, 811, 848 RBWAR ............................. 750, 818, 852 RCR1 .................................. 520, 812, 848 RCR2 .................................. 522, 812, 848 RCR3 .................................. 524, 812, 848 RDAYAR ........................... 517, 812, 848 RDAYCNT......................... 512, 812, 848 RDFAR............................... 750, 818, 852 RDLAR............................... 734, 818, 852 RFCR.................................. 656, 814, 850 RFLR .................................. 652, 814, 850 RHRAR .............................. 515, 812, 848 RHRCNT ............................ 509, 811, 848 RMCR................................. 748, 818, 852 RMFCR .............................. 744, 818, 852 RMINAR ............................ 514, 812, 848 RMINCNT.......................... 509, 811, 848 RMONAR........................... 518, 812, 848 RMONCNT ........................ 512, 812, 848 RSECAR............................. 514, 812, 848 RSECCNT .......................... 508, 811, 848 RTCNT ............................... 382, 810, 847 RTCOR............................... 383, 810, 847 RTCSR ............................... 381, 810, 847 RWKAR ............................. 516, 812, 848 RWKCNT........................... 510, 812, 848 RXALCR............................ 701, 816, 851 RXNLCR............................ 700, 816, 851 RYRAR .............................. 519, 812, 848 RYRCNT ............................ 513, 812, 848 SAR .................................... 463, 810, 847 SCBRR................................ 553, 812, 848 SCFCR ................................ 554, 812, 848 SCFDR................................ 556, 812, 849 SCFRDR ............................. 536, 812, 848 SCFSR ................................ 545, 812, 848 SCFTDR ............................. 537, 812, 848 SCLSR ................................ 558, 812, 849 SCRSR ................................................ 536 SCSCR ................................ 541, 812, 848 SCSMR ............................... 537, 812, 848 SCTSR ................................................ 537 SDBPR................................................ 793 SDBSR................................................ 794 SDCR .................................. 378, 810, 847 SDID ................................... 801, 820, 853 SDIR ................................... 793, 820, 853 SICDAR.............................. 596, 813, 849 SICTR ................................. 598, 813, 849 SIFCTR............................... 601, 813, 849 SIIER .................................. 607, 813, 849 SIMDR................................ 591, 813, 849 SIRCR................................. 612, 813, 849 SIRDAR.............................. 595, 813, 849 SIRDR................................. 610, 813, 849 SISCR ................................. 593, 813, 849 SISTR.................................. 603, 813, 849 SITCR ................................. 611, 813, 849 SITDAR .............................. 594, 813, 849 SITDR................................. 609, 813, 849 STBCR................................ 298, 809, 846 STBCR2.............................. 300, 809, 846 STBCR3.............................. 301, 809, 846 TBRAR ............................... 750, 818, 853 TCNT .................................. 499, 811, 847 TCOR.................................. 499, 811, 847 TCR..................................... 498, 811, 847 TDFAR ............................... 751, 818, 853 TDLAR ............................... 733, 818, 852 TEA..................................... 158, 808, 845 TFTR................................... 745, 818, 852 Rev. 1.00 Dec. 27, 2005 Page 931 of 932 REJ09B0269-0100 TLFRCR ............................. 656, 814, 850 TRA .................................... 156, 808, 845 TRIMD ............................... 753, 818, 853 TROCR............................... 653, 814, 850 TRSCER ............................. 743, 818, 852 TSFRCR ............................. 655, 814, 850 TSTR .................................. 497, 811, 847 TSU_ADQT0 ..................... 679, 815, 851 TSU_ADQT1 ..................... 680, 815, 851 TSU_ADRH ....................... 698, 816, 852 TSU_ADRL........................ 699, 816, 852 TSU_ADSBSY................... 681, 815, 851 TSU_BSYSL0 .................... 661, 815, 851 TSU_BSYSL1 .................... 662, 815, 851 TSU_CTRST ...................... 658, 815, 850 TSU_FCM .......................... 660, 815, 851 TSU_FWEN0 ..................... 658, 815, 850 TSU_FWEN1 ..................... 659, 815, 850 TSU_FWINMK .................. 675, 815, 851 TSU_FWSL0...................... 666, 815, 851 TSU_FWSL1...................... 667, 815, 851 TSU_FWSLC ..................... 669, 815, 851 TSU_FWSR........................ 673, 815, 851 TSU_POST1....................... 686, 815, 851 TSU_POST2....................... 689, 815, 851 TSU_POST3....................... 692, 815, 851 TSU_POST4....................... 695, 815, 851 TSU_PRISL0...................... 663, 815, 851 TSU_PRISL1...................... 664, 815, 851 TSU_QTAGM0 .................. 671, 815, 851 TSU_QTAGM1 .................. 672, 815, 851 TSU_TEN........................... 682, 815, 851 TTB .................................... 191, 808, 845 TXALCR ............................ 700, 815, 851 TXNLCR ............................ 699, 815, 851 WTCNT .............................. 324, 809, 846 WTCSR............................... 324, 809, 846 Registers addresses ................................. 807 Registers bits........................................... 807 Registers states........................................ 807 Repeat end register (RE)........................... 75 Repeat start register (RS) .......................... 75 Reset state ................................................. 27 Round-robin mode .................................. 480 S Save program counter (SPC) .................... 40 Save status register (SSR)......................... 40 Secondary FS .......................................... 621 Self-refreshing ........................................ 430 Single data transfer instructions................ 95 Single virtual memory mode and multiple virtual memory mode................ 189 Software standby mode........................... 303 Status register (SR) ................................... 38 System control instructions....................... 95 System registers ........................................ 32 T T bit........................................................... 44 the RTC crystal oscillator circuit ............ 528 Transmit descriptor ................................. 754 V Vector base register (VBR)....................... 40 Virtual address space .............................. 183 Rev. 1.00 Dec. 27, 2005 Page 932 of 932 REJ09B0269-0100 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7712 Publication Date: Rev.1.00, Dec. 27, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 5.0 SH7712 Hardware Manual |
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